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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: dmu_clu_crm_pktctlfsm.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module dmu_clu_crm_pktctlfsm | |
| 36 | ( | |
| 37 | // clock/reset | |
| 38 | clk, | |
| 39 | rst_l, | |
| 40 | ||
| 41 | // fsm inputs | |
| 42 | dcr_fifo_empty, | |
| 43 | pcr_fifo_empty, | |
| 44 | urr_fifo_empty, | |
| 45 | dcr_grnt, | |
| 46 | pcr_grnt, | |
| 47 | urr_grnt, | |
| 48 | cm2cl_rcd_full, | |
| 49 | done_psb_op, | |
| 50 | pcr_typ, | |
| 51 | mdo_vld, | |
| 52 | drd_vld, | |
| 53 | tdr_vld, | |
| 54 | dcr_clsts, | |
| 55 | ||
| 56 | // fsm outputs | |
| 57 | dcr_req, | |
| 58 | pcr_req, | |
| 59 | urr_req, | |
| 60 | dcr_deq, | |
| 61 | pcr_deq, | |
| 62 | urr_deq, | |
| 63 | grnt_lck, | |
| 64 | pkt_sel, | |
| 65 | epr_ld, | |
| 66 | cl2cm_rcd_enq, | |
| 67 | crm2ctm_tag_enq, | |
| 68 | crm2ctm_rcd_deq, | |
| 69 | start_psb_op, | |
| 70 | psb_op_typ, | |
| 71 | psb_ld, | |
| 72 | trn_sel, | |
| 73 | ||
| 74 | // debug port | |
| 75 | pktctlfsm_state, | |
| 76 | ||
| 77 | // idle checker port | |
| 78 | pktctlfsm_idle | |
| 79 | ); | |
| 80 | ||
| 81 | // synopsys sync_set_reset "rst_l" | |
| 82 | ||
| 83 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
| 84 | ||
| 85 | // -------------------------------------------------------- | |
| 86 | // State Number | |
| 87 | // -------------------------------------------------------- | |
| 88 | ||
| 89 | parameter STATE_NUM = 12; | |
| 90 | ||
| 91 | // -------------------------------------------------------- | |
| 92 | // State Declarations | |
| 93 | // -------------------------------------------------------- | |
| 94 | ||
| 95 | parameter // summit enum cur_enum | |
| 96 | IDLE = 0, | |
| 97 | DMA_RD = 1, | |
| 98 | DMA_RD_WAIT1 = 2, | |
| 99 | MDO_CPL = 3, | |
| 100 | PIO_RD = 4, | |
| 101 | PIO_RD_WAIT1 = 5, | |
| 102 | PIO_WR = 6, | |
| 103 | UNS_REQ = 7, | |
| 104 | UNS_REQ_WAIT1 = 8, | |
| 105 | EPR_STALL = 9, | |
| 106 | MDO_ENQ_STALL = 10, | |
| 107 | PWR_ENQ_STALL = 11; | |
| 108 | ||
| 109 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
| 110 | ||
| 111 | // -------------------------------------------------------- | |
| 112 | // Clock/Reset Signals | |
| 113 | // -------------------------------------------------------- | |
| 114 | ||
| 115 | input clk; | |
| 116 | input rst_l; | |
| 117 | ||
| 118 | // -------------------------------------------------------- | |
| 119 | // FSM Inputs | |
| 120 | // -------------------------------------------------------- | |
| 121 | ||
| 122 | input dcr_fifo_empty; | |
| 123 | input pcr_fifo_empty; | |
| 124 | input urr_fifo_empty; | |
| 125 | input dcr_grnt; | |
| 126 | input pcr_grnt; | |
| 127 | input urr_grnt; | |
| 128 | input cm2cl_rcd_full; | |
| 129 | input done_psb_op; | |
| 130 | input pcr_typ; | |
| 131 | input mdo_vld; | |
| 132 | input drd_vld; | |
| 133 | input tdr_vld; | |
| 134 | input dcr_clsts; | |
| 135 | ||
| 136 | // -------------------------------------------------------- | |
| 137 | // FSM Outputs | |
| 138 | // -------------------------------------------------------- | |
| 139 | ||
| 140 | output dcr_req; | |
| 141 | output pcr_req; | |
| 142 | output urr_req; | |
| 143 | output dcr_deq; | |
| 144 | output pcr_deq; | |
| 145 | output urr_deq; | |
| 146 | output grnt_lck; | |
| 147 | output [1:0] pkt_sel; | |
| 148 | output epr_ld; | |
| 149 | output cl2cm_rcd_enq; | |
| 150 | output crm2ctm_tag_enq; | |
| 151 | output crm2ctm_rcd_deq; | |
| 152 | output start_psb_op; | |
| 153 | output [1:0] psb_op_typ; | |
| 154 | output psb_ld; | |
| 155 | output [1:0] trn_sel; | |
| 156 | ||
| 157 | // debug port | |
| 158 | output [3:0] pktctlfsm_state; | |
| 159 | ||
| 160 | // idle checker port | |
| 161 | output pktctlfsm_idle; | |
| 162 | ||
| 163 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
| 164 | ||
| 165 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 166 | ||
| 167 | // ********** Flops ********** | |
| 168 | ||
| 169 | reg [(STATE_NUM - 1):0] cur_state; | |
| 170 | reg cl2cm_rcd_enq; | |
| 171 | reg crm2ctm_tag_enq; | |
| 172 | reg crm2ctm_rcd_deq; | |
| 173 | ||
| 174 | // ********** Non-Flops ****** | |
| 175 | ||
| 176 | reg [(STATE_NUM - 1):0] nxt_state; | |
| 177 | reg [3:0] enc_state; | |
| 178 | reg [1:0] pkt_sel; | |
| 179 | reg [1:0] trn_sel; | |
| 180 | ||
| 181 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 182 | ||
| 183 | wire drd_1stcl_vld; | |
| 184 | wire proc_tdr; | |
| 185 | wire proc_mdo; | |
| 186 | wire proc_dma_1stcl; | |
| 187 | wire proc_dma_clrmdr; | |
| 188 | wire ld_dma; | |
| 189 | wire proc_pwr; | |
| 190 | wire proc_prd; | |
| 191 | wire ld_prd; | |
| 192 | wire proc_uns; | |
| 193 | wire ld_urr; | |
| 194 | ||
| 195 | // >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
| 196 | ||
| 197 | // 0in one_hot -var cur_state | |
| 198 | ||
| 199 | /* 0in state | |
| 200 | -var cur_state | |
| 201 | -val (12'b1 << IDLE) | |
| 202 | -next (12'b1 << IDLE) | |
| 203 | (12'b1 << DMA_RD) | |
| 204 | (12'b1 << MDO_CPL) | |
| 205 | (12'b1 << PIO_RD) | |
| 206 | (12'b1 << PIO_WR) | |
| 207 | (12'b1 << UNS_REQ) | |
| 208 | -match_by_cycle | |
| 209 | */ | |
| 210 | ||
| 211 | /* 0in state | |
| 212 | -var cur_state | |
| 213 | -val (12'b1 << DMA_RD) | |
| 214 | -next (12'b1 << DMA_RD_WAIT1) | |
| 215 | -match_by_cycle | |
| 216 | */ | |
| 217 | ||
| 218 | /* 0in state | |
| 219 | -var cur_state | |
| 220 | -val (12'b1 << DMA_RD_WAIT1) | |
| 221 | -next (12'b1 << DMA_RD_WAIT1) | |
| 222 | (12'b1 << EPR_STALL) | |
| 223 | (12'b1 << MDO_ENQ_STALL) | |
| 224 | (12'b1 << PWR_ENQ_STALL) | |
| 225 | (12'b1 << IDLE) | |
| 226 | (12'b1 << DMA_RD) | |
| 227 | (12'b1 << PIO_RD) | |
| 228 | (12'b1 << UNS_REQ) | |
| 229 | -match_by_cycle | |
| 230 | */ | |
| 231 | ||
| 232 | /* 0in state | |
| 233 | -var cur_state | |
| 234 | -val (12'b1 << MDO_CPL) | |
| 235 | -next (12'b1 << IDLE) | |
| 236 | (12'b1 << DMA_RD) | |
| 237 | (12'b1 << MDO_CPL) | |
| 238 | (12'b1 << PIO_RD) | |
| 239 | (12'b1 << PIO_WR) | |
| 240 | (12'b1 << UNS_REQ) | |
| 241 | -match_by_cycle | |
| 242 | */ | |
| 243 | ||
| 244 | /* 0in state | |
| 245 | -var cur_state | |
| 246 | -val (12'b1 << PIO_RD) | |
| 247 | -next (12'b1 << PIO_RD_WAIT1) | |
| 248 | -match_by_cycle | |
| 249 | */ | |
| 250 | ||
| 251 | /* 0in state | |
| 252 | -var cur_state | |
| 253 | -val (12'b1 << PIO_RD_WAIT1) | |
| 254 | -next (12'b1 << PIO_RD_WAIT1) | |
| 255 | (12'b1 << EPR_STALL) | |
| 256 | (12'b1 << MDO_ENQ_STALL) | |
| 257 | (12'b1 << PWR_ENQ_STALL) | |
| 258 | (12'b1 << IDLE) | |
| 259 | (12'b1 << DMA_RD) | |
| 260 | (12'b1 << PIO_RD) | |
| 261 | (12'b1 << UNS_REQ) | |
| 262 | -match_by_cycle | |
| 263 | */ | |
| 264 | ||
| 265 | /* 0in state | |
| 266 | -var cur_state | |
| 267 | -val (12'b1 << PIO_WR) | |
| 268 | -next (12'b1 << IDLE) | |
| 269 | (12'b1 << DMA_RD) | |
| 270 | (12'b1 << MDO_CPL) | |
| 271 | (12'b1 << PIO_RD) | |
| 272 | (12'b1 << PIO_WR) | |
| 273 | (12'b1 << UNS_REQ) | |
| 274 | -match_by_cycle | |
| 275 | */ | |
| 276 | ||
| 277 | /* 0in state | |
| 278 | -var cur_state | |
| 279 | -val (12'b1 << UNS_REQ) | |
| 280 | -next (12'b1 << UNS_REQ_WAIT1) | |
| 281 | -match_by_cycle | |
| 282 | */ | |
| 283 | ||
| 284 | /* 0in state | |
| 285 | -var cur_state | |
| 286 | -val (12'b1 << UNS_REQ_WAIT1) | |
| 287 | -next (12'b1 << UNS_REQ_WAIT1) | |
| 288 | (12'b1 << EPR_STALL) | |
| 289 | (12'b1 << MDO_ENQ_STALL) | |
| 290 | (12'b1 << PWR_ENQ_STALL) | |
| 291 | (12'b1 << IDLE) | |
| 292 | (12'b1 << DMA_RD) | |
| 293 | (12'b1 << PIO_RD) | |
| 294 | (12'b1 << UNS_REQ) | |
| 295 | -match_by_cycle | |
| 296 | */ | |
| 297 | ||
| 298 | /* 0in state | |
| 299 | -var cur_state | |
| 300 | -val (12'b1 << EPR_STALL) | |
| 301 | -next (12'b1 << EPR_STALL) | |
| 302 | (12'b1 << MDO_ENQ_STALL) | |
| 303 | (12'b1 << PWR_ENQ_STALL) | |
| 304 | (12'b1 << IDLE) | |
| 305 | (12'b1 << DMA_RD) | |
| 306 | (12'b1 << PIO_RD) | |
| 307 | (12'b1 << UNS_REQ) | |
| 308 | -match_by_cycle | |
| 309 | */ | |
| 310 | ||
| 311 | /* 0in state | |
| 312 | -var cur_state | |
| 313 | -val (12'b1 << MDO_ENQ_STALL) | |
| 314 | -next (12'b1 << MDO_ENQ_STALL) | |
| 315 | (12'b1 << MDO_CPL) | |
| 316 | -match_by_cycle | |
| 317 | */ | |
| 318 | ||
| 319 | /* 0in state | |
| 320 | -var cur_state | |
| 321 | -val (12'b1 << PWR_ENQ_STALL) | |
| 322 | -next (12'b1 << PWR_ENQ_STALL) | |
| 323 | (12'b1 << PIO_WR) | |
| 324 | -match_by_cycle | |
| 325 | */ | |
| 326 | ||
| 327 | // 0in kndr -var cm2cl_rcd_full | |
| 328 | ||
| 329 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
| 330 | ||
| 331 | // -------------------------------------------------------- | |
| 332 | // IDLE Checker | |
| 333 | // -------------------------------------------------------- | |
| 334 | ||
| 335 | assign pktctlfsm_idle = cur_state[IDLE]; | |
| 336 | ||
| 337 | // -------------------------------------------------------- | |
| 338 | // Debug Port Logic | |
| 339 | // -------------------------------------------------------- | |
| 340 | ||
| 341 | // encode one-hot current_state vector for debug port | |
| 342 | always @(cur_state[(STATE_NUM - 1):1]) | |
| 343 | begin | |
| 344 | enc_state[0] = (cur_state[1] | cur_state[3] | cur_state[5] | | |
| 345 | cur_state[7] | cur_state[9] | cur_state[11]); | |
| 346 | ||
| 347 | enc_state[1] = (cur_state[2] | cur_state[3] | cur_state[6] | | |
| 348 | cur_state[7] | cur_state[10] | cur_state[11]); | |
| 349 | ||
| 350 | enc_state[2] = (cur_state[4] | cur_state[5] | cur_state[6] | | |
| 351 | cur_state[7]); | |
| 352 | ||
| 353 | enc_state[3] = (cur_state[8] | cur_state[9] | cur_state[10] | | |
| 354 | cur_state[11]); | |
| 355 | end | |
| 356 | ||
| 357 | // output pktctlfsm debug bus | |
| 358 | assign pktctlfsm_state = enc_state; | |
| 359 | ||
| 360 | // -------------------------------------------------------- | |
| 361 | // Control Decode | |
| 362 | // -------------------------------------------------------- | |
| 363 | ||
| 364 | // dma rd cpl for 1st_cl | |
| 365 | assign drd_1stcl_vld = drd_vld & dcr_clsts; | |
| 366 | ||
| 367 | // -------------------------------------------------------- | |
| 368 | // Arbiter Requests | |
| 369 | // -------------------------------------------------------- | |
| 370 | ||
| 371 | // tdr and non-1stcl dma_cpl do not require arb (they are dropped) | |
| 372 | assign dcr_req = ~dcr_fifo_empty & (mdo_vld | drd_1stcl_vld); | |
| 373 | assign pcr_req = ~pcr_fifo_empty; | |
| 374 | assign urr_req = ~urr_fifo_empty; | |
| 375 | ||
| 376 | // -------------------------------------------------------- | |
| 377 | // FSM Next State | |
| 378 | // -------------------------------------------------------- | |
| 379 | ||
| 380 | // next state assignment | |
| 381 | always @(cur_state or cm2cl_rcd_full or dcr_grnt or pcr_grnt or urr_grnt or | |
| 382 | drd_1stcl_vld or mdo_vld or pcr_typ or done_psb_op) | |
| 383 | begin | |
| 384 | ||
| 385 | // initialization | |
| 386 | nxt_state = {STATE_NUM{1'b0}}; | |
| 387 | ||
| 388 | case (1'b1) // synopsys parallel_case | |
| 389 | ||
| 390 | // 0in < case -full | |
| 391 | ||
| 392 | /////////////////////////////////////////////////////////////////////// | |
| 393 | ||
| 394 | // ---------- IDLE ------------------------------------------ | |
| 395 | ||
| 396 | // IDLE State | |
| 397 | cur_state[IDLE] : | |
| 398 | casez ({cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, drd_1stcl_vld, | |
| 399 | mdo_vld, pcr_typ}) | |
| 400 | ||
| 401 | // 0in < case -parallel -full | |
| 402 | ||
| 403 | 7'b1_zzz_zzz, | |
| 404 | 7'b0_000_zzz, | |
| 405 | 7'b0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 406 | 7'b0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 407 | 7'b0_100_01z : nxt_state[MDO_CPL] = 1'b1; | |
| 408 | 7'b0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 409 | 7'b0_010_zz0 : nxt_state[PIO_WR] = 1'b1; | |
| 410 | 7'b0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 411 | endcase | |
| 412 | ||
| 413 | /////////////////////////////////////////////////////////////////////// | |
| 414 | ||
| 415 | // ---------- DMA READ CPL ---------------------------------- | |
| 416 | ||
| 417 | // DMA READ State | |
| 418 | cur_state[DMA_RD] : | |
| 419 | nxt_state[DMA_RD_WAIT1] = 1'b1; | |
| 420 | ||
| 421 | // DMA READ WAIT1 State | |
| 422 | cur_state[DMA_RD_WAIT1] : | |
| 423 | casez ({done_psb_op, cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, | |
| 424 | drd_1stcl_vld, mdo_vld, pcr_typ}) | |
| 425 | ||
| 426 | // 0in < case -parallel -full | |
| 427 | ||
| 428 | // MDO_CPL/PIO_WR must wait until DMA_RD enq cycle finishes | |
| 429 | ||
| 430 | 8'b0_z_zzz_zzz : nxt_state[DMA_RD_WAIT1] = 1'b1; | |
| 431 | 8'b1_1_zzz_zzz : nxt_state[EPR_STALL] = 1'b1; | |
| 432 | 8'b1_0_100_01z : nxt_state[MDO_ENQ_STALL] = 1'b1; | |
| 433 | 8'b1_0_010_zz0 : nxt_state[PWR_ENQ_STALL] = 1'b1; | |
| 434 | 8'b1_0_000_zzz, | |
| 435 | 8'b1_0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 436 | 8'b1_0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 437 | 8'b1_0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 438 | 8'b1_0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 439 | endcase | |
| 440 | ||
| 441 | /////////////////////////////////////////////////////////////////////// | |
| 442 | ||
| 443 | // ---------- MONDO CPL ------------------------------------ | |
| 444 | ||
| 445 | // MDO COMPLETION State | |
| 446 | cur_state[MDO_CPL] : | |
| 447 | casez ({cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, drd_1stcl_vld, | |
| 448 | mdo_vld, pcr_typ}) | |
| 449 | ||
| 450 | // 0in < case -parallel -full | |
| 451 | ||
| 452 | 7'b1_zzz_zzz, | |
| 453 | 7'b0_000_zzz, | |
| 454 | 7'b0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 455 | 7'b0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 456 | 7'b0_100_01z : nxt_state[MDO_CPL] = 1'b1; | |
| 457 | 7'b0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 458 | 7'b0_010_zz0 : nxt_state[PIO_WR] = 1'b1; | |
| 459 | 7'b0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 460 | endcase | |
| 461 | ||
| 462 | /////////////////////////////////////////////////////////////////////// | |
| 463 | ||
| 464 | // ---------- PIO READ REQ ---------------------------------- | |
| 465 | ||
| 466 | // PIO READ State | |
| 467 | cur_state[PIO_RD] : | |
| 468 | nxt_state[PIO_RD_WAIT1] = 1'b1; | |
| 469 | ||
| 470 | // PIO READ WAIT1 State | |
| 471 | cur_state[PIO_RD_WAIT1] : | |
| 472 | casez ({done_psb_op, cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, | |
| 473 | drd_1stcl_vld, mdo_vld, pcr_typ}) | |
| 474 | ||
| 475 | // 0in < case -parallel -full | |
| 476 | ||
| 477 | // MDO_CPL/PIO_WR must wait until PIO_RD enq cycle finishes | |
| 478 | ||
| 479 | 8'b0_z_zzz_zzz : nxt_state[PIO_RD_WAIT1] = 1'b1; | |
| 480 | 8'b1_1_zzz_zzz : nxt_state[EPR_STALL] = 1'b1; | |
| 481 | 8'b1_0_100_01z : nxt_state[MDO_ENQ_STALL] = 1'b1; | |
| 482 | 8'b1_0_010_zz0 : nxt_state[PWR_ENQ_STALL] = 1'b1; | |
| 483 | 8'b1_0_000_zzz, | |
| 484 | 8'b1_0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 485 | 8'b1_0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 486 | 8'b1_0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 487 | 8'b1_0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 488 | endcase | |
| 489 | ||
| 490 | /////////////////////////////////////////////////////////////////////// | |
| 491 | ||
| 492 | // ---------- PIO WR REQ ------------------------------------ | |
| 493 | ||
| 494 | // PIO WRITE State | |
| 495 | cur_state[PIO_WR] : | |
| 496 | casez ({cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, drd_1stcl_vld, | |
| 497 | mdo_vld, pcr_typ}) | |
| 498 | ||
| 499 | // 0in < case -parallel -full | |
| 500 | ||
| 501 | 7'b1_zzz_zzz, | |
| 502 | 7'b0_000_zzz, | |
| 503 | 7'b0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 504 | 7'b0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 505 | 7'b0_100_01z : nxt_state[MDO_CPL] = 1'b1; | |
| 506 | 7'b0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 507 | 7'b0_010_zz0 : nxt_state[PIO_WR] = 1'b1; | |
| 508 | 7'b0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 509 | endcase | |
| 510 | ||
| 511 | /////////////////////////////////////////////////////////////////////// | |
| 512 | ||
| 513 | // ---------- UNSUPPORTED REQ ------------------------------- | |
| 514 | ||
| 515 | // UNS REQUEST State | |
| 516 | cur_state[UNS_REQ] : | |
| 517 | nxt_state[UNS_REQ_WAIT1] = 1'b1; | |
| 518 | ||
| 519 | // UNS REQUEST WAIT1 State | |
| 520 | cur_state[UNS_REQ_WAIT1] : | |
| 521 | casez ({done_psb_op, cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, | |
| 522 | drd_1stcl_vld, mdo_vld, pcr_typ}) | |
| 523 | ||
| 524 | // 0in < case -parallel -full | |
| 525 | ||
| 526 | // MDO_CPL/PIO_WR must wait until UNS_REQ enq cycle finishes | |
| 527 | ||
| 528 | 8'b0_z_zzz_zzz : nxt_state[UNS_REQ_WAIT1] = 1'b1; | |
| 529 | 8'b1_1_zzz_zzz : nxt_state[EPR_STALL] = 1'b1; | |
| 530 | 8'b1_0_100_01z : nxt_state[MDO_ENQ_STALL] = 1'b1; | |
| 531 | 8'b1_0_010_zz0 : nxt_state[PWR_ENQ_STALL] = 1'b1; | |
| 532 | 8'b1_0_000_zzz, | |
| 533 | 8'b1_0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 534 | 8'b1_0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 535 | 8'b1_0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 536 | 8'b1_0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 537 | endcase | |
| 538 | ||
| 539 | /////////////////////////////////////////////////////////////////////// | |
| 540 | ||
| 541 | // ---------- EPR PIPE STALL -------------------------------- | |
| 542 | ||
| 543 | // EPR_STALL State | |
| 544 | cur_state[EPR_STALL] : | |
| 545 | casez ({cm2cl_rcd_full, dcr_grnt, pcr_grnt, urr_grnt, drd_1stcl_vld, | |
| 546 | mdo_vld, pcr_typ}) | |
| 547 | ||
| 548 | // 0in < case -parallel -full | |
| 549 | ||
| 550 | // MDO_CPL/PIO_WR must wait until dma/piord/uns enq cycle finishes | |
| 551 | ||
| 552 | 7'b1_zzz_zzz : nxt_state[EPR_STALL] = 1'b1; | |
| 553 | 7'b0_100_01z : nxt_state[MDO_ENQ_STALL] = 1'b1; | |
| 554 | 7'b0_010_zz0 : nxt_state[PWR_ENQ_STALL] = 1'b1; | |
| 555 | 7'b0_000_zzz, | |
| 556 | 7'b0_100_00z : nxt_state[IDLE] = 1'b1; | |
| 557 | 7'b0_100_10z : nxt_state[DMA_RD] = 1'b1; | |
| 558 | 7'b0_010_zz1 : nxt_state[PIO_RD] = 1'b1; | |
| 559 | 7'b0_001_zzz : nxt_state[UNS_REQ] = 1'b1; | |
| 560 | endcase | |
| 561 | ||
| 562 | /////////////////////////////////////////////////////////////////////// | |
| 563 | ||
| 564 | // ---------- ENQ STALL ------------------------------------- | |
| 565 | ||
| 566 | // MDO_ENQ_STALL State | |
| 567 | cur_state[MDO_ENQ_STALL] : | |
| 568 | if (cm2cl_rcd_full) | |
| 569 | nxt_state[MDO_ENQ_STALL] = 1'b1; | |
| 570 | else | |
| 571 | nxt_state[MDO_CPL] = 1'b1; | |
| 572 | ||
| 573 | // PWR_ENQ_STALL State | |
| 574 | cur_state[PWR_ENQ_STALL] : | |
| 575 | if (cm2cl_rcd_full) | |
| 576 | nxt_state[PWR_ENQ_STALL] = 1'b1; | |
| 577 | else | |
| 578 | nxt_state[PIO_WR] = 1'b1; | |
| 579 | ||
| 580 | /////////////////////////////////////////////////////////////////////// | |
| 581 | ||
| 582 | endcase | |
| 583 | end | |
| 584 | ||
| 585 | // -------------------------------------------------------- | |
| 586 | // FSM Current State | |
| 587 | // -------------------------------------------------------- | |
| 588 | ||
| 589 | // summit state_vector cur_state enum cur_enum | |
| 590 | ||
| 591 | // current state assignment | |
| 592 | always @(posedge clk) | |
| 593 | if (~rst_l) | |
| 594 | begin | |
| 595 | cur_state <= {STATE_NUM{1'b0}}; | |
| 596 | cur_state[IDLE] <= 1'b1; | |
| 597 | end | |
| 598 | else | |
| 599 | cur_state <= nxt_state; | |
| 600 | ||
| 601 | // -------------------------------------------------------- | |
| 602 | // FSM Output Gen | |
| 603 | // -------------------------------------------------------- | |
| 604 | ||
| 605 | // ########################################################################## | |
| 606 | ||
| 607 | // ************************************************************************** | |
| 608 | // ***** DCR FIFO TRANSACTION PROCESSING ************************************ | |
| 609 | // ************************************************************************** | |
| 610 | ||
| 611 | // ----- process tablewalk data response ------------------- | |
| 612 | ||
| 613 | // no common resource requirement for tdr; no arbiter dependency | |
| 614 | ||
| 615 | // deq dcr_fifo, drop cpl, return credit to CTM | |
| 616 | assign proc_tdr = ~dcr_fifo_empty & tdr_vld; | |
| 617 | ||
| 618 | // ----- process mondo completion -------------------------- | |
| 619 | ||
| 620 | // deq dcr_fifo, ld epr_reg, enq epr_pkt to TCM, return credit to CTM | |
| 621 | assign proc_mdo = nxt_state[MDO_CPL]; // single-cyc type; deq for next | |
| 622 | ||
| 623 | // ----- process dma read completion ----------------------- | |
| 624 | ||
| 625 | // enq epr_pkt to TCM | |
| 626 | assign proc_dma_1stcl = (cur_state[DMA_RD_WAIT1] & | |
| 627 | ~(nxt_state[DMA_RD_WAIT1] | nxt_state[EPR_STALL])); | |
| 628 | ||
| 629 | // deq dcr_fifo, drop cpl, return credit to CTM | |
| 630 | assign proc_dma_clrmdr = ~dcr_fifo_empty & drd_vld & ~dcr_clsts; | |
| 631 | ||
| 632 | // deq dcr_fifo, ld epr_reg, return credit to CTM | |
| 633 | assign ld_dma = cur_state[DMA_RD]; | |
| 634 | ||
| 635 | // ************************************************************************** | |
| 636 | // ***** PCR FIFO TRANSACTION PROCESSING ************************************ | |
| 637 | // ************************************************************************** | |
| 638 | ||
| 639 | // ----- process pio write request ------------------------- | |
| 640 | ||
| 641 | // deq pcr_fifo, ld epr_reg, enq epr_pkt to TCM | |
| 642 | assign proc_pwr = nxt_state[PIO_WR]; // single-cyc type; deq for next | |
| 643 | ||
| 644 | // ----- process pio read request -------------------------- | |
| 645 | ||
| 646 | // enq epr_pkt to TCM | |
| 647 | assign proc_prd = (cur_state[PIO_RD_WAIT1] & | |
| 648 | ~(nxt_state[PIO_RD_WAIT1] | nxt_state[EPR_STALL])); | |
| 649 | ||
| 650 | // deq dcr_fifo, ld epr_reg | |
| 651 | assign ld_prd = cur_state[PIO_RD]; // multi-cyc type; deq in pio_rd state | |
| 652 | ||
| 653 | // ************************************************************************** | |
| 654 | // ***** URR FIFO TRANSACTION PROCESSING ************************************ | |
| 655 | // ************************************************************************** | |
| 656 | ||
| 657 | // ----- process unsupported request ----------------------- | |
| 658 | ||
| 659 | // enq epr_pkt to TCM | |
| 660 | assign proc_uns = (cur_state[UNS_REQ_WAIT1] & | |
| 661 | ~(nxt_state[UNS_REQ_WAIT1] | nxt_state[EPR_STALL])); | |
| 662 | ||
| 663 | // deq urr_fifo, ld epr_reg | |
| 664 | assign ld_urr = cur_state[UNS_REQ]; // multi-cyc type; deq in uns_req state | |
| 665 | ||
| 666 | // ########################################################################## | |
| 667 | ||
| 668 | // ----- generate fifo deqs -------------------------------- | |
| 669 | ||
| 670 | // dcr fifo deq - tdr, mdo, dma | |
| 671 | assign dcr_deq = proc_tdr | proc_dma_clrmdr | proc_mdo | ld_dma; | |
| 672 | ||
| 673 | // pcr fifo deq - pio_wr, pio_rd | |
| 674 | assign pcr_deq = proc_pwr | ld_prd; | |
| 675 | ||
| 676 | // urr fifo deq - unsupp req | |
| 677 | assign urr_deq = ld_urr; | |
| 678 | ||
| 679 | // ----- epr_reg load -------------------------------------- | |
| 680 | ||
| 681 | // generate epr_reg ld | |
| 682 | assign epr_ld = proc_mdo | ld_dma | pcr_deq | urr_deq; | |
| 683 | ||
| 684 | // generate epr_pkt select | |
| 685 | always @(proc_pwr or ld_prd or ld_urr) | |
| 686 | begin | |
| 687 | if (proc_pwr | ld_prd) | |
| 688 | pkt_sel = 2'b01; // pcr (pio_wr/pio_rd) | |
| 689 | else if (ld_urr) | |
| 690 | pkt_sel = 2'b10; // urr (unsupported) | |
| 691 | else | |
| 692 | pkt_sel = 2'b00; // dcr (dma/mdo) | |
| 693 | end | |
| 694 | ||
| 695 | // ----- psb_reg load -------------------------------------- | |
| 696 | ||
| 697 | // psb trn select | |
| 698 | always @(nxt_state[PIO_RD] or nxt_state[UNS_REQ]) | |
| 699 | if (nxt_state[PIO_RD]) | |
| 700 | trn_sel = 2'b01; | |
| 701 | else if (nxt_state[UNS_REQ]) | |
| 702 | trn_sel = 2'b10; | |
| 703 | else | |
| 704 | trn_sel = 2'b00; | |
| 705 | ||
| 706 | // psb wr_data/trn load enable | |
| 707 | assign psb_ld = nxt_state[DMA_RD] | nxt_state[PIO_RD] | nxt_state[UNS_REQ]; | |
| 708 | ||
| 709 | // ----- crm control --------------------------------------- | |
| 710 | ||
| 711 | // init psb access operation (psbctlfsm init) | |
| 712 | assign start_psb_op = (nxt_state[DMA_RD] | nxt_state[PIO_RD] | | |
| 713 | nxt_state[UNS_REQ]); | |
| 714 | ||
| 715 | // psb access type (01-piowr, 10-dmardclr) | |
| 716 | assign psb_op_typ = {(nxt_state[DMA_RD] | nxt_state[UNS_REQ]), | |
| 717 | nxt_state[PIO_RD]}; | |
| 718 | ||
| 719 | // arbiter lock to maintain state during psb ops and pipe stall | |
| 720 | assign grnt_lck = (nxt_state[DMA_RD_WAIT1] | nxt_state[PIO_RD_WAIT1] | | |
| 721 | nxt_state[UNS_REQ_WAIT1] | nxt_state[EPR_STALL] | | |
| 722 | nxt_state[MDO_ENQ_STALL] | nxt_state[PWR_ENQ_STALL] | | |
| 723 | cm2cl_rcd_full); | |
| 724 | ||
| 725 | // ----- interface control --------------------------------- | |
| 726 | ||
| 727 | // registered control outputs | |
| 728 | always @(posedge clk) | |
| 729 | if (~rst_l) | |
| 730 | begin | |
| 731 | cl2cm_rcd_enq <= 1'b0; | |
| 732 | crm2ctm_tag_enq <= 1'b0; | |
| 733 | crm2ctm_rcd_deq <= 1'b0; | |
| 734 | end | |
| 735 | else | |
| 736 | begin | |
| 737 | ||
| 738 | // ----- gen epr pkt enq ----------- | |
| 739 | if (proc_mdo | proc_dma_1stcl | proc_pwr | proc_prd | proc_uns | | |
| 740 | (cur_state[EPR_STALL] & ~nxt_state[EPR_STALL])) | |
| 741 | cl2cm_rcd_enq <= 1'b1; | |
| 742 | else | |
| 743 | cl2cm_rcd_enq <= 1'b0; | |
| 744 | ||
| 745 | // ----- tag/credit return enq ----- | |
| 746 | if (dcr_deq) | |
| 747 | crm2ctm_tag_enq <= 1'b1; | |
| 748 | else | |
| 749 | crm2ctm_tag_enq <= 1'b0; | |
| 750 | ||
| 751 | // ----- urr fifo deq -------------- | |
| 752 | if (urr_deq) | |
| 753 | crm2ctm_rcd_deq <= 1'b1; | |
| 754 | else | |
| 755 | crm2ctm_rcd_deq <= 1'b0; | |
| 756 | ||
| 757 | end | |
| 758 | ||
| 759 | endmodule // dmu_clu_crm_pktctlfsm |