[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_cmu_ctx.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_cmu_ctx.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
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// ========== Copyright Header End ============================================
module dmu_cmu_ctx (
		clk, 	
		rst_l,

     // Debug
		dbg2ctx_dbg_sel_a,	
		dbg2ctx_dbg_sel_b,	
		ctx2dbg_dbg_a, 
		ctx2dbg_dbg_b, 

     // RCM
		rcm2ctx_ctx_req,
		ctx2rcm_ctx_gnt,
		ctx2rcm_nxctx_addr,
		rcm2ctx_ctx_addr,
		rcm2ctx_ctx_rw,
		ctx2rcm_cur_ctx,
		rcm2ctx_ctx,
		rcm2ctx_seq_req,
		ctx2rcm_seq_gnt,
		ctx2rcm_nxseq_addr,
		rcm2ctx_pkseq_addr,
		rcm2ctx_pkseq_rw,
		rcm2ctx_pkseq,

     // TCM
		tcm2ctx_ctx_addr,
		tcm2ctx_ctx_rw,
		ctx2tcm_cur_ctx,
		tcm2ctx_ctx,
		tcm2ctx_pkseq_addr,
		tcm2ctx_pkseq_rw,
		ctx2tcm_cur_pkseq,
		tcm2ctx_pkseq,
		tcm2ctx_lst_req,
		ctx2tcm_lst_gnt,
		ctx2tcm_nxlst_addr,
		tcm2ctx_ctxlst_addr,
		tcm2ctx_clst_rw,
		tcm2ctx_lst,
		ctx2tcm_cur_lst,
		tcm2ctx_ret_req,
		tcm2ctx_ret_addr
		);

     
//************************************************
//				PARAMETERS
//************************************************

// parameter MM2CM_WDTH    = `FIRE_DLC_ISR_REC_WDTH,       //79
//           CM2PM_WDTH    = `FIRE_DLC_IPR_REC_WDTH,       //93
//           CL2CM_WDTH    = `FIRE_DLC_EPR_REC_WDTH,       //80
//			 CM2RM_WDTH    = `FIRE_DLC_ERR_REC_WDTH;       //70   

// parameter SRMSB       = `FIRE_DLC_ISR_MSB,              // MM2CM_SRWDTH -1
//           RRMSB       = `FIRE_DLC_ERR_MSB;              // CM2RM_RRWDTH -1
   
//   parameter IPRMSB      = `FIRE_DLC_IPR_MSB,            // CM2PM_PRWDTH -1
//			   EPRMSB      = `FIRE_DLC_EPR_MSB;            // CL2CM_PRWDTH -1


// CTX
//   parameter CTXARRAY_WDTH      = 43,           // Context CTX entry width
   parameter CTXARRAY_WDTH      = 44,           // Context CTX entry width
			 CTXARRAYMSB        = CTXARRAY_WDTH -1,
			 CTXARRAY_DEPTH     = 32,
   			 CTXARRAY_ADDR_WDTH = 5,
             CTXARRAYADDRMSB    = CTXARRAY_ADDR_WDTH -1,
             CTXADDRLSB         = 0,
			 CTXADDR_WDTH       = 5,
             CTXADDRMSB         = CTXADDRLSB + CTXADDR_WDTH -1;			 

   parameter CTXALOC_WDTH   = 5,
			 CTXALOC_DEPTH  = 32;

// PKSEQ   
   parameter PSEQARRAY_WDTH      = 5,            // Context PKSEQ entry width
			 PSEQARRAYMSB        = PSEQARRAY_WDTH -1,
			 PSEQARRAY_DEPTH     = 32,
			 PSEQARRAY_ADDR_WDTH = 5,
             PSEQARRAYADDRMSB    = PSEQARRAY_ADDR_WDTH -1,
             PSEQADDRLSB         = 0,
			 PSEQADDR_WDTH       = 5,
			 PSEQADDRMSB         = PSEQADDRLSB + PSEQADDR_WDTH -1;			 
   
   parameter PSEQALOC_WDTH  = 5,
			 PSEQALOC_DEPTH = 32;   
   
// CLST
   parameter CLSTARRAY_WDTH      = 54,            // Context CLST entry width
			 CLSTARRAYMSB        = CLSTARRAY_WDTH -1,
			 CLSTARRAY_DEPTH     = 16,
			 CLSTARRAY_ADDR_WDTH = 4,
             CLSTARRAYADDRMSB    = CLSTARRAY_ADDR_WDTH -1,
             CLSTADDRLSB         = 0,
			 CLSTADDR_WDTH       = 4,
			 CLSTADDRMSB         = CLSTADDRLSB + CLSTADDR_WDTH -1;
   
   parameter CLSTALOC_WDTH   = 4,
             CLSTALOC_DEPTH = 16;   

// RET address
   parameter RETADDRARRAY_WDTH  = 17,
			 RETADDRMSB         = RETADDRARRAY_WDTH -1;   
   
   parameter RETCLSTADDRLSB      = 0,
			 RETCLSTADDR_WDTH    = 4,
			 RETCLSTADDRMSB      = RETCLSTADDRLSB + RETCLSTADDR_WDTH -1,
			 RETCLSTLSB          = RETCLSTADDRLSB + RETCLSTADDR_WDTH,
			 RETCLST_WDTH        = 1,
			 RETCLSTMSB          = RETCLSTLSB + RETCLST_WDTH -1,
			 RETPSEQADDRLSB      = RETCLSTLSB + RETCLST_WDTH,
			 RETPSEQADDR_WDTH    = 5,
			 RETPSEQADDRMSB      = RETPSEQADDRLSB + RETPSEQADDR_WDTH -1,
			 RETPSEQLSB          = RETPSEQADDRLSB + RETPSEQADDR_WDTH,
			 RETPSEQ_WDTH        = 1,
			 RETPSEQMSB          = RETPSEQLSB + RETPSEQ_WDTH -1,
			 RETCTXADDRLSB       = RETPSEQLSB + RETPSEQ_WDTH,
			 RETCTXADDR_WDTH     = 5,
             RETCTXADDRMSB       = RETCTXADDRLSB + RETCTXADDR_WDTH -1,
			 RETCTXLSB           = RETCTXADDRLSB + RETCTXADDR_WDTH,
			 RETCTX_WDTH         = 1,
			 RETCTXMSB           = RETCTXLSB + RETCTX_WDTH -1;

   
//************************************************
//				PORTS
//************************************************

   input clk;                                      // The input clock
   input rst_l;                                    // synopsys sync_set_reset "rst_l"

// RCM
   input  rcm2ctx_ctx_req;   
   output ctx2rcm_ctx_gnt; 
   output [CTXADDRMSB :0] ctx2rcm_nxctx_addr;
   
   input  [CTXADDRMSB :0] rcm2ctx_ctx_addr;
   input  rcm2ctx_ctx_rw;
   output [CTXARRAYMSB : 0] ctx2rcm_cur_ctx;
   input  [CTXARRAYMSB : 0] rcm2ctx_ctx;
   
   input  rcm2ctx_seq_req;
   output ctx2rcm_seq_gnt;
   output [PSEQADDRMSB :0] ctx2rcm_nxseq_addr;
   input  [PSEQADDRMSB :0] rcm2ctx_pkseq_addr;
   input  rcm2ctx_pkseq_rw;
   input  [PSEQARRAYMSB :0] rcm2ctx_pkseq;

// TCM
   input  [CTXADDRMSB :0] tcm2ctx_ctx_addr;
   input  tcm2ctx_ctx_rw;
   output [CTXARRAYMSB : 0] ctx2tcm_cur_ctx;
   input  [CTXARRAYMSB : 0] tcm2ctx_ctx;

   input  [PSEQADDRMSB :0] tcm2ctx_pkseq_addr;
   input  tcm2ctx_pkseq_rw;
   output [PSEQARRAYMSB : 0] ctx2tcm_cur_pkseq;
   input  [PSEQARRAYMSB : 0] tcm2ctx_pkseq;

   input  tcm2ctx_lst_req;
   output ctx2tcm_lst_gnt;
   output [CLSTADDRMSB :0] ctx2tcm_nxlst_addr;

   input  [CLSTADDRMSB :0] tcm2ctx_ctxlst_addr;
   input  tcm2ctx_clst_rw;
   input  [CLSTARRAYMSB : 0] tcm2ctx_lst;
   output [CLSTARRAYMSB : 0] ctx2tcm_cur_lst;   

   input  tcm2ctx_ret_req;
   input  [RETADDRMSB :0] tcm2ctx_ret_addr;

// Debug
   input [`FIRE_DLC_CMU_CTX_DS_BITS] dbg2ctx_dbg_sel_a;
   input [`FIRE_DLC_CMU_CTX_DS_BITS] dbg2ctx_dbg_sel_b;
   output [`FIRE_DBG_DATA_BITS] 	ctx2dbg_dbg_a;
   output [`FIRE_DBG_DATA_BITS] 	ctx2dbg_dbg_b;   
   
//************************************************
//				Functions
//************************************************

   
//************************************************
//				SIGNALS
//************************************************


   wire ctx_valid;
   wire seq_valid;

   wire clst_mpty;

//   for use when debug gets wired up
//   wire ctx_full;
//   wire clst_full;
//   wire clst_overflow;
//   wire clst_underflow;

// to-from RCM
   wire [CTXADDRMSB :0] ctx2rcm_nxctx_addr;
   
   wire [CTXADDRMSB :0] rcm2ctx_ctx_addr;
   wire rcm2ctx_ctx_rw;
   wire [CTXARRAYMSB : 0] ctx2rcm_cur_ctx;
   wire [CTXARRAYMSB : 0] rcm2ctx_ctx;
   
   wire rcm2ctx_seq_req;
   wire ctx2rcm_seq_gnt;
   wire [PSEQADDRMSB :0] ctx2rcm_nxseq_addr;
   wire [PSEQADDRMSB :0] rcm2ctx_pkseq_addr;
   wire rcm2ctx_pkseq_rw;
   wire [PSEQARRAYMSB : 0] rcm2ctx_pkseq;

// to-from TCM
   wire [CTXADDRMSB :0] tcm2ctx_ctx_addr;
   wire tcm2ctx_ctx_rw;
   wire [CTXARRAYMSB : 0] tcm2ctx_ctx;

   wire [PSEQADDRMSB :0] tcm2ctx_pkseq_addr;
   wire tcm2ctx_pkseq_rw;
   wire [PSEQARRAYMSB : 0] ctx2tcm_cur_pkseq;
   wire [PSEQARRAYMSB : 0] tcm2ctx_pkseq;

   wire tcm2ctx_lst_req;
   wire ctx2tcm_lst_gnt;
   wire [CLSTADDRMSB :0] ctx2tcm_nxlst_addr;

   wire [CLSTADDRMSB :0] tcm2ctx_ctxlst_addr;
   wire tcm2ctx_clst_rw;
   wire [CLSTARRAYMSB : 0] tcm2ctx_lst;
   wire [CLSTARRAYMSB : 0] ctx2tcm_cur_lst;   

   wire tcm2ctx_ret_req;
   wire [RETADDRMSB :0] tcm2ctx_ret_addr;   

   wire [CTXARRAYADDRMSB :0] ctx_ret_addr;
   wire [PSEQARRAYADDRMSB :0] seq_ret_addr;
   wire [CLSTARRAYADDRMSB :0] clst_ret_addr;

   wire ctx_rel, 
        seq_rel, 
        clst_rel;

// Registers
   reg ctx_enq,
       seq_enq,
       clst_enq;

   reg next_ctx_deq, ctx_deq;
   reg next_seq_deq, seq_deq; 
   reg next_clst_deq, clst_deq;
   
   reg [1 :0] ctx_state;
   reg [1 :0] ctx_next;  

   reg [1 :0] seq_state;
   reg [1 :0] seq_next;  

   reg [1 :0] clst_state;
   reg [1 :0] clst_next;

   reg ctx_is_idle; 

// Debug
  reg  [`FIRE_DLC_CMU_RCM_DS_BITS]	dbg_sel [0:1];
  reg  [`FIRE_DBG_DATA_BITS]	dbg_bus [0:1];
  reg  [`FIRE_DBG_DATA_BITS]	nxt_dbg_bus [0:1];
  integer i, j;   
   
// *************** Local Declarations ******************************/

   parameter 
	   CTXIDLE  = 2'b00,  // NO requests
       CTXDEQ   = 2'b01;  // number available

   parameter 
	   SEQIDLE  = 2'b00,  // NO requests
       SEQDEQ   = 2'b01;  // number available

   parameter 
	   CLSTIDLE  = 2'b00,  // NO requests
       CLSTDEQ   = 2'b01;  // number available
   
   
//************************************************
// Zero In checkers
//************************************************ 
// ctx_fsm
  //0in state_transition  -var ctx_state  -val CTXIDLE  -next CTXIDLE CTXDEQ 
  //0in state_transition  -var ctx_state  -val CTXDEQ   -next CTXIDLE

// seq_fsm
  //0in state_transition  -var seq_state  -val SEQIDLE  -next SEQIDLE SEQDEQ
  //0in state_transition  -var seq_state  -val SEQDEQ   -next SEQIDLE

// clst_fsm
  //0in state_transition  -var clst_state  -val CLSTIDLE  -next CLSTIDLE CLSTDEQ
  //0in state_transition  -var clst_state  -val CLSTDEQ   -next CLSTIDLE


// *************** Procedures *************************************/

always @( ctx_rel or seq_rel or clst_rel)
  begin
	 ctx_enq = 1'b0;
     seq_enq = 1'b0;
     clst_enq = 1'b0;
	 if(ctx_rel) ctx_enq = 1'b1;
	 if(seq_rel) seq_enq = 1'b1;
	 if(clst_rel) clst_enq = 1'b1;
  end   
		  
// Context Number aloc fsm
// if ctx_valid = 1 current address can be used   
// if next sequential address is in use valid = 0 - wait
   
 always @(ctx_state or ctx_valid or rcm2ctx_ctx_req)
   begin
	  next_ctx_deq = 1'b0;
      ctx_next = ctx_state;

	   case  (ctx_state)
		 CTXIDLE :  begin        // Waiting for requests
           if (rcm2ctx_ctx_req) begin
			  if(~ctx_valid) begin
				 next_ctx_deq = 1'b0;
				 ctx_next = CTXIDLE;
			  end
			  else begin
				 next_ctx_deq = 1'b1;
				 ctx_next = CTXDEQ;
			  end
		   end			
		   else begin
			  next_ctx_deq = 1'b0;
			  ctx_next = CTXIDLE;
		   end
		 end		 
         CTXDEQ : begin          // Load winner issue gnt to requester
			   next_ctx_deq = 1'b0;
               ctx_next = CTXIDLE;
          end         
         default : begin
			  next_ctx_deq = 1'b0;
			  ctx_next = CTXIDLE;
		   end
	   endcase // case(ctx_state)
   end // always @ (ctx_state or pre_win or ctx_valid or rcm2ctx_ctx_req)   

// CTX aloc state transitions
always @(posedge clk)
  begin
	 if (rst_l == 1'b0)
	   ctx_state <= CTXIDLE;	// Synchronous Reset
	 else begin
		ctx_state <= ctx_next;
	 end
  end  

// PKSEQ Address aloc fsm
// if seq_valid = 1 current address can be used
// if next sequential address is in use valid = 0 - wait

 always @(seq_state or rcm2ctx_seq_req or seq_valid)
   begin
	  next_seq_deq = 1'b0;
      seq_next = seq_state;

	   case  (seq_state)
		 SEQIDLE :  begin        // Waiting for requests
           if (rcm2ctx_seq_req) begin
			  if(seq_valid == 1'b1 ) begin
				 next_seq_deq = 1'b1;
				 seq_next = SEQDEQ;
			  end
			  else begin
				 next_seq_deq = 1'b0;
				 seq_next = SEQIDLE;
			  end
		   end			
		   else begin
			  next_seq_deq = 1'b0;
			  seq_next = SEQIDLE;
		   end
		 end		 
         SEQDEQ : begin          // Load winner issue gnt to requester
			   next_seq_deq = 1'b0;
               seq_next = SEQIDLE;
          end         
         default : begin
			  next_seq_deq = 1'b0;
			  seq_next = SEQIDLE;
		   end
	   endcase // case(seq_state)	  
   end // always @ (seq_state or rcm2ctx_seq_req or seq_valid)   

// PSEQ aloc state transitions
always @(posedge clk)
  begin
	 if (rst_l == 1'b0)
	   seq_state <= SEQIDLE;	// Synchronous Reset
	 else begin
		seq_state <= seq_next;
	 end
  end  

// CLIST Address aloc fsm
 always @(clst_state or clst_mpty or tcm2ctx_lst_req)
   begin
	  next_clst_deq = 1'b0;
      clst_next = clst_state;

	   case  (clst_state)
		 CLSTIDLE :  begin        // Waiting for requests
           if (tcm2ctx_lst_req) begin
			  if(clst_mpty) begin
				 next_clst_deq = 1'b0;
				 clst_next = CLSTIDLE;
			  end
			  else begin
				 next_clst_deq = 1'b1;
				 clst_next = CLSTDEQ;
			  end
		   end			
		   else begin
			  next_clst_deq = 1'b0;
			  clst_next = CLSTIDLE;
		   end
		 end		 
         CLSTDEQ : begin          // Load winner issue gnt to requester
			   next_clst_deq = 1'b0;
               clst_next = CLSTIDLE;
          end         
         default : begin
			  next_clst_deq = 1'b0;
			  clst_next = CLSTIDLE;
		   end
	   endcase // case(clst_state)
   end // always @ (clst_state or clst_mpty or rcm2ctx_seq_req)   

// CLIST aloc state transitions
always @(posedge clk)
  begin
	 if (rst_l == 1'b0)
	   clst_state <= CLSTIDLE;	// Synchronous Reset
	 else begin
		clst_state <= clst_next;
	 end
  end  
    
   
//************************************************
//				MODULES
//************************************************

// Context Number Address Allocater
dmu_cmu_ctx_aloc #(CTXALOC_WDTH, CTXALOC_DEPTH) 
   cnum_aloc (
			  .clk (clk),
			  .rst_l (rst_l),
			  .enq (ctx_enq),
			  .data_in (ctx_ret_addr),
			  .deq (ctx_deq),
			  .data_out (ctx2rcm_nxctx_addr),
			  .valid (ctx_valid)
			  );

// Context Array
// both ports same size   
dmu_cmu_ctx_reg_array #(CTXARRAY_WDTH,CTXARRAY_DEPTH,CTXARRAY_ADDR_WDTH)
   ctx_array (
			  .clk(clk),
			  .rst_l(rst_l),
			  .addr0(rcm2ctx_ctx_addr),
			  .data0_in(rcm2ctx_ctx),
			  .rw0(rcm2ctx_ctx_rw),
			  .data0_out(ctx2rcm_cur_ctx),           //may not need
			  .addr1(tcm2ctx_ctx_addr),
			  .data1_in(tcm2ctx_ctx),
			  .rw1(tcm2ctx_ctx_rw),
			  .data1_out(ctx2tcm_cur_ctx)
			   );

// Context Packet Sequence Address Allocater
dmu_cmu_ctx_pkseqaloc #(PSEQALOC_WDTH,PSEQALOC_DEPTH)
   pkseq_aloc (
			   .clk (clk),
			   .rst_l (rst_l),
			   .enq (seq_enq),
			   .data_in (seq_ret_addr),
			   .deq (seq_deq),
			   .data_out (ctx2rcm_nxseq_addr),
			   .valid(seq_valid)
			    );

// Packet Sequence Array   
// both ports same size
dmu_cmu_ctx_reg_array #(PSEQARRAY_WDTH,PSEQARRAY_DEPTH,PSEQARRAY_ADDR_WDTH)
         pkseq_array (
					  .clk(clk),
					  .rst_l(rst_l),
					  .addr0(rcm2ctx_pkseq_addr),
					  .data0_in(rcm2ctx_pkseq),
					  .rw0(rcm2ctx_pkseq_rw),
					  .data0_out(),  
					  .addr1(tcm2ctx_pkseq_addr),
					  .data1_in(tcm2ctx_pkseq),
					  .rw1(tcm2ctx_pkseq_rw),
					  .data1_out(ctx2tcm_cur_pkseq)
					   );

// Context List Address Allocater
dmu_cmu_clst_aloc #(CLSTALOC_WDTH, CLSTALOC_DEPTH)
   lst_aloc (
			 .clk (clk),
			 .rst_l (rst_l),
			 .enq (clst_enq),
			 .data_in (clst_ret_addr),
			 .deq (clst_deq),
			 .data_out (ctx2tcm_nxlst_addr),
			 .full (),              //.full (clst_full),
			 .empty (clst_mpty),
             .overflow(),           //.overflow(clst_overflow),
             .underflow()           //.underflow(clst_underflow)
			 );

// Context List Array
// both ports same size      
dmu_cmu_ctx_clstreg_array #(CLSTARRAY_WDTH,
                                 CLSTARRAY_DEPTH,
                                 CLSTARRAY_ADDR_WDTH
                                 ) 
   clist_array (
				.clk(clk),
				.rst_l(rst_l),
				.addr(tcm2ctx_ctxlst_addr),
				.data_in(tcm2ctx_lst),
				.rw(tcm2ctx_clst_rw),
				.data_out(ctx2tcm_cur_lst)
				 );
   
// ********************** signal registers ************************/
always @(posedge clk)
  begin	 
    if (rst_l == 1'b0) begin
	   ctx_deq   <= 0;	   
	   seq_deq   <= 0;	   
	   clst_deq  <= 0;	   
	end
	else begin
	   ctx_deq  <= next_ctx_deq;	   
	   seq_deq  <= next_seq_deq;	   
	   clst_deq <= next_clst_deq;	   
	end
  end // always @ (posedge clk) 
   
always @(posedge clk)
  begin
    if (rst_l == 1'b0) begin
	   ctx_is_idle <= 1'b1;	   
     end
    else begin
	   ctx_is_idle <= ((rcm2ctx_ctx_req == 1'b0) && (ctx_state == CTXIDLE) && 
                       (rcm2ctx_seq_req == 1'b0) && (seq_state == SEQIDLE) &&
                       (tcm2ctx_lst_req == 1'b0)  && (clst_state == CLSTIDLE))
                      ? 1'b1 : 1'b0;
	end
  end 

// ----------------------------------------------------------------------------
// Debug
// ----------------------------------------------------------------------------
always @ (dbg2ctx_dbg_sel_a or dbg2ctx_dbg_sel_b) 
  begin
	 dbg_sel[0] = dbg2ctx_dbg_sel_a;
	 dbg_sel[1] = dbg2ctx_dbg_sel_b;
  end

always @ (dbg_sel[0] or dbg_sel[1] or 
          rcm2ctx_ctx_req or ctx_deq or ctx2rcm_nxctx_addr or
          rcm2ctx_seq_req or seq_deq or ctx2rcm_nxseq_addr or
          tcm2ctx_lst_req or clst_deq or ctx2tcm_nxlst_addr or
          ctx_rel or ctx_ret_addr or seq_rel or seq_ret_addr or
		  clst_rel or clst_ret_addr or ctx_is_idle
		  )
  begin
	 for (i = 0; i < 2; i = i + 1) begin
		case (dbg_sel[i]) // synopsys infer_mux
		  3'b000: nxt_dbg_bus[i] = {ctx_is_idle,rcm2ctx_ctx_req,ctx_deq,ctx2rcm_nxctx_addr};
		  3'b001: nxt_dbg_bus[i] = {1'b0,rcm2ctx_seq_req,seq_deq,ctx2rcm_nxseq_addr};
		  3'b010: nxt_dbg_bus[i] = {2'b00,tcm2ctx_lst_req,clst_deq,ctx2tcm_nxlst_addr};
		  3'b011: nxt_dbg_bus[i] = {2'b00,ctx_rel,ctx_ret_addr};
		  3'b100: nxt_dbg_bus[i] = {2'b00,seq_rel,seq_ret_addr};
		  3'b101: nxt_dbg_bus[i] = {3'b000,clst_rel,clst_ret_addr};
		  3'b110: nxt_dbg_bus[i] = 8'h00;
		  3'b111: nxt_dbg_bus[i] = 8'h00;
		endcase // case(dbg_sel[i])
	 end // for (i = 0; i < 2; i = i + 1)
  end // always @ (dbg_sel[0] or dbg_sel[1] or...  
   
always @ (posedge clk) begin
   if(rst_l == 1'b0) begin
    for (j = 0; j < 2; j = j + 1) begin
      dbg_bus[j] <= 8'h00;
    end
   end
   else begin
	  for (j = 0; j < 2; j = j + 1) begin
		 dbg_bus[j] <= nxt_dbg_bus[j];
	  end
   end
end // always @ (posedge clk)

	   
// ********************** Output Procedures ***********************/

   
// ***********************Assignments *****************************/
   assign ctx_rel = tcm2ctx_ret_req & tcm2ctx_ret_addr[RETCTXMSB];   
   assign ctx_ret_addr = tcm2ctx_ret_addr[RETCTXADDRMSB :RETCTXADDRLSB];

   assign seq_rel = tcm2ctx_ret_req & tcm2ctx_ret_addr[RETPSEQMSB];   
   assign seq_ret_addr = tcm2ctx_ret_addr[RETPSEQADDRMSB :RETPSEQADDRLSB];

   assign clst_rel = tcm2ctx_ret_req & tcm2ctx_ret_addr[RETCLSTMSB];   
   assign clst_ret_addr = tcm2ctx_ret_addr[RETCLSTADDRMSB :RETCLSTADDRLSB];

   assign ctx2rcm_ctx_gnt = ctx_deq;
   assign ctx2rcm_seq_gnt = seq_deq;
   assign ctx2tcm_lst_gnt = clst_deq;

// Output assignments
   
// Debug
  assign ctx2dbg_dbg_a = dbg_bus[0];
  assign ctx2dbg_dbg_b = dbg_bus[1];   

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_cmu_ctx.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_cmu_ctx (
	36	clk,
	37	rst_l,
	38
	39	// Debug
	40	dbg2ctx_dbg_sel_a,
	41	dbg2ctx_dbg_sel_b,
	42	ctx2dbg_dbg_a,
	43	ctx2dbg_dbg_b,
	44
	45	// RCM
	46	rcm2ctx_ctx_req,
	47	ctx2rcm_ctx_gnt,
	48	ctx2rcm_nxctx_addr,
	49	rcm2ctx_ctx_addr,
	50	rcm2ctx_ctx_rw,
	51	ctx2rcm_cur_ctx,
	52	rcm2ctx_ctx,
	53	rcm2ctx_seq_req,
	54	ctx2rcm_seq_gnt,
	55	ctx2rcm_nxseq_addr,
	56	rcm2ctx_pkseq_addr,
	57	rcm2ctx_pkseq_rw,
	58	rcm2ctx_pkseq,
	59
	60	// TCM
	61	tcm2ctx_ctx_addr,
	62	tcm2ctx_ctx_rw,
	63	ctx2tcm_cur_ctx,
	64	tcm2ctx_ctx,
65	tcm2ctx_pkseq_addr,
66	tcm2ctx_pkseq_rw,
67	ctx2tcm_cur_pkseq,
68	tcm2ctx_pkseq,
69	tcm2ctx_lst_req,
70	ctx2tcm_lst_gnt,
71	ctx2tcm_nxlst_addr,
72	tcm2ctx_ctxlst_addr,
73	tcm2ctx_clst_rw,
74	tcm2ctx_lst,
75	ctx2tcm_cur_lst,
76	tcm2ctx_ret_req,
77	tcm2ctx_ret_addr
78	);
79
80
81	//************************************************
82	// PARAMETERS
83	//************************************************
84
85	// parameter MM2CM_WDTH = `FIRE_DLC_ISR_REC_WDTH, //79
86	// CM2PM_WDTH = `FIRE_DLC_IPR_REC_WDTH, //93
87	// CL2CM_WDTH = `FIRE_DLC_EPR_REC_WDTH, //80
88	// CM2RM_WDTH = `FIRE_DLC_ERR_REC_WDTH; //70
89
90	// parameter SRMSB = `FIRE_DLC_ISR_MSB, // MM2CM_SRWDTH -1
91	// RRMSB = `FIRE_DLC_ERR_MSB; // CM2RM_RRWDTH -1
92
93	// parameter IPRMSB = `FIRE_DLC_IPR_MSB, // CM2PM_PRWDTH -1
94	// EPRMSB = `FIRE_DLC_EPR_MSB; // CL2CM_PRWDTH -1
95
96
97	// CTX
98	// parameter CTXARRAY_WDTH = 43, // Context CTX entry width
99	parameter CTXARRAY_WDTH = 44, // Context CTX entry width
100	CTXARRAYMSB = CTXARRAY_WDTH -1,
101	CTXARRAY_DEPTH = 32,
102	CTXARRAY_ADDR_WDTH = 5,
103	CTXARRAYADDRMSB = CTXARRAY_ADDR_WDTH -1,
104	CTXADDRLSB = 0,
105	CTXADDR_WDTH = 5,
106	CTXADDRMSB = CTXADDRLSB + CTXADDR_WDTH -1;
107
108	parameter CTXALOC_WDTH = 5,
109	CTXALOC_DEPTH = 32;
110
111	// PKSEQ
112	parameter PSEQARRAY_WDTH = 5, // Context PKSEQ entry width
113	PSEQARRAYMSB = PSEQARRAY_WDTH -1,
114	PSEQARRAY_DEPTH = 32,
115	PSEQARRAY_ADDR_WDTH = 5,
116	PSEQARRAYADDRMSB = PSEQARRAY_ADDR_WDTH -1,
117	PSEQADDRLSB = 0,
118	PSEQADDR_WDTH = 5,
119	PSEQADDRMSB = PSEQADDRLSB + PSEQADDR_WDTH -1;
120
121	parameter PSEQALOC_WDTH = 5,
122	PSEQALOC_DEPTH = 32;
123
124	// CLST
125	parameter CLSTARRAY_WDTH = 54, // Context CLST entry width
126	CLSTARRAYMSB = CLSTARRAY_WDTH -1,
127	CLSTARRAY_DEPTH = 16,
128	CLSTARRAY_ADDR_WDTH = 4,
129	CLSTARRAYADDRMSB = CLSTARRAY_ADDR_WDTH -1,
130	CLSTADDRLSB = 0,
131	CLSTADDR_WDTH = 4,
132	CLSTADDRMSB = CLSTADDRLSB + CLSTADDR_WDTH -1;
133
134	parameter CLSTALOC_WDTH = 4,
135	CLSTALOC_DEPTH = 16;
136
137	// RET address
138	parameter RETADDRARRAY_WDTH = 17,
139	RETADDRMSB = RETADDRARRAY_WDTH -1;
140
141	parameter RETCLSTADDRLSB = 0,
142	RETCLSTADDR_WDTH = 4,
143	RETCLSTADDRMSB = RETCLSTADDRLSB + RETCLSTADDR_WDTH -1,
144	RETCLSTLSB = RETCLSTADDRLSB + RETCLSTADDR_WDTH,
145	RETCLST_WDTH = 1,
146	RETCLSTMSB = RETCLSTLSB + RETCLST_WDTH -1,
147	RETPSEQADDRLSB = RETCLSTLSB + RETCLST_WDTH,
148	RETPSEQADDR_WDTH = 5,
149	RETPSEQADDRMSB = RETPSEQADDRLSB + RETPSEQADDR_WDTH -1,
150	RETPSEQLSB = RETPSEQADDRLSB + RETPSEQADDR_WDTH,
151	RETPSEQ_WDTH = 1,
152	RETPSEQMSB = RETPSEQLSB + RETPSEQ_WDTH -1,
153	RETCTXADDRLSB = RETPSEQLSB + RETPSEQ_WDTH,
154	RETCTXADDR_WDTH = 5,
155	RETCTXADDRMSB = RETCTXADDRLSB + RETCTXADDR_WDTH -1,
156	RETCTXLSB = RETCTXADDRLSB + RETCTXADDR_WDTH,
157	RETCTX_WDTH = 1,
158	RETCTXMSB = RETCTXLSB + RETCTX_WDTH -1;
159
160
161	//************************************************
162	// PORTS
163	//************************************************
164
165	input clk; // The input clock
166	input rst_l; // synopsys sync_set_reset "rst_l"
167
168	// RCM
169	input rcm2ctx_ctx_req;
170	output ctx2rcm_ctx_gnt;
171	output [CTXADDRMSB :0] ctx2rcm_nxctx_addr;
172
173	input [CTXADDRMSB :0] rcm2ctx_ctx_addr;
174	input rcm2ctx_ctx_rw;
175	output [CTXARRAYMSB : 0] ctx2rcm_cur_ctx;
176	input [CTXARRAYMSB : 0] rcm2ctx_ctx;
177
178	input rcm2ctx_seq_req;
179	output ctx2rcm_seq_gnt;
180	output [PSEQADDRMSB :0] ctx2rcm_nxseq_addr;
181	input [PSEQADDRMSB :0] rcm2ctx_pkseq_addr;
182	input rcm2ctx_pkseq_rw;
183	input [PSEQARRAYMSB :0] rcm2ctx_pkseq;
184
185	// TCM
186	input [CTXADDRMSB :0] tcm2ctx_ctx_addr;
187	input tcm2ctx_ctx_rw;
188	output [CTXARRAYMSB : 0] ctx2tcm_cur_ctx;
189	input [CTXARRAYMSB : 0] tcm2ctx_ctx;
190
191	input [PSEQADDRMSB :0] tcm2ctx_pkseq_addr;
192	input tcm2ctx_pkseq_rw;
193	output [PSEQARRAYMSB : 0] ctx2tcm_cur_pkseq;
194	input [PSEQARRAYMSB : 0] tcm2ctx_pkseq;
195
196	input tcm2ctx_lst_req;
197	output ctx2tcm_lst_gnt;
198	output [CLSTADDRMSB :0] ctx2tcm_nxlst_addr;
199
200	input [CLSTADDRMSB :0] tcm2ctx_ctxlst_addr;
201	input tcm2ctx_clst_rw;
202	input [CLSTARRAYMSB : 0] tcm2ctx_lst;
203	output [CLSTARRAYMSB : 0] ctx2tcm_cur_lst;
204
205	input tcm2ctx_ret_req;
206	input [RETADDRMSB :0] tcm2ctx_ret_addr;
207
208	// Debug
209	input [`FIRE_DLC_CMU_CTX_DS_BITS] dbg2ctx_dbg_sel_a;
210	input [`FIRE_DLC_CMU_CTX_DS_BITS] dbg2ctx_dbg_sel_b;
211	output [`FIRE_DBG_DATA_BITS] ctx2dbg_dbg_a;
212	output [`FIRE_DBG_DATA_BITS] ctx2dbg_dbg_b;
213
214	//************************************************
215	// Functions
216	//************************************************
217
218
219	//************************************************
220	// SIGNALS
221	//************************************************
222
223
224	wire ctx_valid;
225	wire seq_valid;
226
227	wire clst_mpty;
228
229	// for use when debug gets wired up
230	// wire ctx_full;
231	// wire clst_full;
232	// wire clst_overflow;
233	// wire clst_underflow;
234
235	// to-from RCM
236	wire [CTXADDRMSB :0] ctx2rcm_nxctx_addr;
237
238	wire [CTXADDRMSB :0] rcm2ctx_ctx_addr;
239	wire rcm2ctx_ctx_rw;
240	wire [CTXARRAYMSB : 0] ctx2rcm_cur_ctx;
241	wire [CTXARRAYMSB : 0] rcm2ctx_ctx;
242
243	wire rcm2ctx_seq_req;
244	wire ctx2rcm_seq_gnt;
245	wire [PSEQADDRMSB :0] ctx2rcm_nxseq_addr;
246	wire [PSEQADDRMSB :0] rcm2ctx_pkseq_addr;
247	wire rcm2ctx_pkseq_rw;
248	wire [PSEQARRAYMSB : 0] rcm2ctx_pkseq;
249
250	// to-from TCM
251	wire [CTXADDRMSB :0] tcm2ctx_ctx_addr;
252	wire tcm2ctx_ctx_rw;
253	wire [CTXARRAYMSB : 0] tcm2ctx_ctx;
254
255	wire [PSEQADDRMSB :0] tcm2ctx_pkseq_addr;
256	wire tcm2ctx_pkseq_rw;
257	wire [PSEQARRAYMSB : 0] ctx2tcm_cur_pkseq;
258	wire [PSEQARRAYMSB : 0] tcm2ctx_pkseq;
259
260	wire tcm2ctx_lst_req;
261	wire ctx2tcm_lst_gnt;
262	wire [CLSTADDRMSB :0] ctx2tcm_nxlst_addr;
263
264	wire [CLSTADDRMSB :0] tcm2ctx_ctxlst_addr;
265	wire tcm2ctx_clst_rw;
266	wire [CLSTARRAYMSB : 0] tcm2ctx_lst;
267	wire [CLSTARRAYMSB : 0] ctx2tcm_cur_lst;
268
269	wire tcm2ctx_ret_req;
270	wire [RETADDRMSB :0] tcm2ctx_ret_addr;
271
272	wire [CTXARRAYADDRMSB :0] ctx_ret_addr;
273	wire [PSEQARRAYADDRMSB :0] seq_ret_addr;
274	wire [CLSTARRAYADDRMSB :0] clst_ret_addr;
275
276	wire ctx_rel,
277	seq_rel,
278	clst_rel;
279
280	// Registers
281	reg ctx_enq,
282	seq_enq,
283	clst_enq;
284
285	reg next_ctx_deq, ctx_deq;
286	reg next_seq_deq, seq_deq;
287	reg next_clst_deq, clst_deq;
288
289	reg [1 :0] ctx_state;
290	reg [1 :0] ctx_next;
291
292	reg [1 :0] seq_state;
293	reg [1 :0] seq_next;
294
295	reg [1 :0] clst_state;
296	reg [1 :0] clst_next;
297
298	reg ctx_is_idle;
299
300	// Debug
301	reg [`FIRE_DLC_CMU_RCM_DS_BITS] dbg_sel [0:1];
302	reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1];
303	reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1];
304	integer i, j;
305
306	// ************* Local Declarations ****************************/
307
308	parameter
309	CTXIDLE = 2'b00, // NO requests
310	CTXDEQ = 2'b01; // number available
311
312	parameter
313	SEQIDLE = 2'b00, // NO requests
314	SEQDEQ = 2'b01; // number available
315
316	parameter
317	CLSTIDLE = 2'b00, // NO requests
318	CLSTDEQ = 2'b01; // number available
319
320
321	//************************************************
322	// Zero In checkers
323	//************************************************
324	// ctx_fsm
325	//0in state_transition -var ctx_state -val CTXIDLE -next CTXIDLE CTXDEQ
326	//0in state_transition -var ctx_state -val CTXDEQ -next CTXIDLE
327
328	// seq_fsm
329	//0in state_transition -var seq_state -val SEQIDLE -next SEQIDLE SEQDEQ
330	//0in state_transition -var seq_state -val SEQDEQ -next SEQIDLE
331
332	// clst_fsm
333	//0in state_transition -var clst_state -val CLSTIDLE -next CLSTIDLE CLSTDEQ
334	//0in state_transition -var clst_state -val CLSTDEQ -next CLSTIDLE
335
336
337	// ************* Procedures ***********************************/
338
339	always @( ctx_rel or seq_rel or clst_rel)
340	begin
341	ctx_enq = 1'b0;
342	seq_enq = 1'b0;
343	clst_enq = 1'b0;
344	if(ctx_rel) ctx_enq = 1'b1;
345	if(seq_rel) seq_enq = 1'b1;
346	if(clst_rel) clst_enq = 1'b1;
347	end
348
349	// Context Number aloc fsm
350	// if ctx_valid = 1 current address can be used
351	// if next sequential address is in use valid = 0 - wait
352
353	always @(ctx_state or ctx_valid or rcm2ctx_ctx_req)
354	begin
355	next_ctx_deq = 1'b0;
356	ctx_next = ctx_state;
357
358	case (ctx_state)
359	CTXIDLE : begin // Waiting for requests
360	if (rcm2ctx_ctx_req) begin
361	if(~ctx_valid) begin
362	next_ctx_deq = 1'b0;
363	ctx_next = CTXIDLE;
364	end
365	else begin
366	next_ctx_deq = 1'b1;
367	ctx_next = CTXDEQ;
368	end
369	end
370	else begin
371	next_ctx_deq = 1'b0;
372	ctx_next = CTXIDLE;
373	end
374	end
375	CTXDEQ : begin // Load winner issue gnt to requester
376	next_ctx_deq = 1'b0;
377	ctx_next = CTXIDLE;
378	end
379	default : begin
380	next_ctx_deq = 1'b0;
381	ctx_next = CTXIDLE;
382	end
383	endcase // case(ctx_state)
384	end // always @ (ctx_state or pre_win or ctx_valid or rcm2ctx_ctx_req)
385
386	// CTX aloc state transitions
387	always @(posedge clk)
388	begin
389	if (rst_l == 1'b0)
390	ctx_state <= CTXIDLE; // Synchronous Reset
391	else begin
392	ctx_state <= ctx_next;
393	end
394	end
395
396	// PKSEQ Address aloc fsm
397	// if seq_valid = 1 current address can be used
398	// if next sequential address is in use valid = 0 - wait
399
400	always @(seq_state or rcm2ctx_seq_req or seq_valid)
401	begin
402	next_seq_deq = 1'b0;
403	seq_next = seq_state;
404
405	case (seq_state)
406	SEQIDLE : begin // Waiting for requests
407	if (rcm2ctx_seq_req) begin
408	if(seq_valid == 1'b1 ) begin
409	next_seq_deq = 1'b1;
410	seq_next = SEQDEQ;
411	end
412	else begin
413	next_seq_deq = 1'b0;
414	seq_next = SEQIDLE;
415	end
416	end
417	else begin
418	next_seq_deq = 1'b0;
419	seq_next = SEQIDLE;
420	end
421	end
422	SEQDEQ : begin // Load winner issue gnt to requester
423	next_seq_deq = 1'b0;
424	seq_next = SEQIDLE;
425	end
426	default : begin
427	next_seq_deq = 1'b0;
428	seq_next = SEQIDLE;
429	end
430	endcase // case(seq_state)
431	end // always @ (seq_state or rcm2ctx_seq_req or seq_valid)
432
433	// PSEQ aloc state transitions
434	always @(posedge clk)
435	begin
436	if (rst_l == 1'b0)
437	seq_state <= SEQIDLE; // Synchronous Reset
438	else begin
439	seq_state <= seq_next;
440	end
441	end
442
443	// CLIST Address aloc fsm
444	always @(clst_state or clst_mpty or tcm2ctx_lst_req)
445	begin
446	next_clst_deq = 1'b0;
447	clst_next = clst_state;
448
449	case (clst_state)
450	CLSTIDLE : begin // Waiting for requests
451	if (tcm2ctx_lst_req) begin
452	if(clst_mpty) begin
453	next_clst_deq = 1'b0;
454	clst_next = CLSTIDLE;
455	end
456	else begin
457	next_clst_deq = 1'b1;
458	clst_next = CLSTDEQ;
459	end
460	end
461	else begin
462	next_clst_deq = 1'b0;
463	clst_next = CLSTIDLE;
464	end
465	end
466	CLSTDEQ : begin // Load winner issue gnt to requester
467	next_clst_deq = 1'b0;
468	clst_next = CLSTIDLE;
469	end
470	default : begin
471	next_clst_deq = 1'b0;
472	clst_next = CLSTIDLE;
473	end
474	endcase // case(clst_state)
475	end // always @ (clst_state or clst_mpty or rcm2ctx_seq_req)
476
477	// CLIST aloc state transitions
478	always @(posedge clk)
479	begin
480	if (rst_l == 1'b0)
481	clst_state <= CLSTIDLE; // Synchronous Reset
482	else begin
483	clst_state <= clst_next;
484	end
485	end
486
487
488	//************************************************
489	// MODULES
490	//************************************************
491
492	// Context Number Address Allocater
493	dmu_cmu_ctx_aloc #(CTXALOC_WDTH, CTXALOC_DEPTH)
494	cnum_aloc (
495	.clk (clk),
496	.rst_l (rst_l),
497	.enq (ctx_enq),
498	.data_in (ctx_ret_addr),
499	.deq (ctx_deq),
500	.data_out (ctx2rcm_nxctx_addr),
501	.valid (ctx_valid)
502	);
503
504	// Context Array
505	// both ports same size
506	dmu_cmu_ctx_reg_array #(CTXARRAY_WDTH,CTXARRAY_DEPTH,CTXARRAY_ADDR_WDTH)
507	ctx_array (
508	.clk(clk),
509	.rst_l(rst_l),
510	.addr0(rcm2ctx_ctx_addr),
511	.data0_in(rcm2ctx_ctx),
512	.rw0(rcm2ctx_ctx_rw),
513	.data0_out(ctx2rcm_cur_ctx), //may not need
514	.addr1(tcm2ctx_ctx_addr),
515	.data1_in(tcm2ctx_ctx),
516	.rw1(tcm2ctx_ctx_rw),
517	.data1_out(ctx2tcm_cur_ctx)
518	);
519
520	// Context Packet Sequence Address Allocater
521	dmu_cmu_ctx_pkseqaloc #(PSEQALOC_WDTH,PSEQALOC_DEPTH)
522	pkseq_aloc (
523	.clk (clk),
524	.rst_l (rst_l),
525	.enq (seq_enq),
526	.data_in (seq_ret_addr),
527	.deq (seq_deq),
528	.data_out (ctx2rcm_nxseq_addr),
529	.valid(seq_valid)
530	);
531
532	// Packet Sequence Array
533	// both ports same size
534	dmu_cmu_ctx_reg_array #(PSEQARRAY_WDTH,PSEQARRAY_DEPTH,PSEQARRAY_ADDR_WDTH)
535	pkseq_array (
536	.clk(clk),
537	.rst_l(rst_l),
538	.addr0(rcm2ctx_pkseq_addr),
539	.data0_in(rcm2ctx_pkseq),
540	.rw0(rcm2ctx_pkseq_rw),
541	.data0_out(),
542	.addr1(tcm2ctx_pkseq_addr),
543	.data1_in(tcm2ctx_pkseq),
544	.rw1(tcm2ctx_pkseq_rw),
545	.data1_out(ctx2tcm_cur_pkseq)
546	);
547
548	// Context List Address Allocater
549	dmu_cmu_clst_aloc #(CLSTALOC_WDTH, CLSTALOC_DEPTH)
550	lst_aloc (
551	.clk (clk),
552	.rst_l (rst_l),
553	.enq (clst_enq),
554	.data_in (clst_ret_addr),
555	.deq (clst_deq),
556	.data_out (ctx2tcm_nxlst_addr),
557	.full (), //.full (clst_full),
558	.empty (clst_mpty),
559	.overflow(), //.overflow(clst_overflow),
560	.underflow() //.underflow(clst_underflow)
561	);
562
563	// Context List Array
564	// both ports same size
565	dmu_cmu_ctx_clstreg_array #(CLSTARRAY_WDTH,
566	CLSTARRAY_DEPTH,
567	CLSTARRAY_ADDR_WDTH
568	)
569	clist_array (
570	.clk(clk),
571	.rst_l(rst_l),
572	.addr(tcm2ctx_ctxlst_addr),
573	.data_in(tcm2ctx_lst),
574	.rw(tcm2ctx_clst_rw),
575	.data_out(ctx2tcm_cur_lst)
576	);
577
578	// ******************** signal registers **********************/
579	always @(posedge clk)
580	begin
581	if (rst_l == 1'b0) begin
582	ctx_deq <= 0;
583	seq_deq <= 0;
584	clst_deq <= 0;
585	end
586	else begin
587	ctx_deq <= next_ctx_deq;
588	seq_deq <= next_seq_deq;
589	clst_deq <= next_clst_deq;
590	end
591	end // always @ (posedge clk)
592
593	always @(posedge clk)
594	begin
595	if (rst_l == 1'b0) begin
596	ctx_is_idle <= 1'b1;
597	end
598	else begin
599	ctx_is_idle <= ((rcm2ctx_ctx_req == 1'b0) && (ctx_state == CTXIDLE) &&
600	(rcm2ctx_seq_req == 1'b0) && (seq_state == SEQIDLE) &&
601	(tcm2ctx_lst_req == 1'b0) && (clst_state == CLSTIDLE))
602	? 1'b1 : 1'b0;
603	end
604	end
605
606	// ----------------------------------------------------------------------------
607	// Debug
608	// ----------------------------------------------------------------------------
609	always @ (dbg2ctx_dbg_sel_a or dbg2ctx_dbg_sel_b)
610	begin
611	dbg_sel[0] = dbg2ctx_dbg_sel_a;
612	dbg_sel[1] = dbg2ctx_dbg_sel_b;
613	end
614
615	always @ (dbg_sel[0] or dbg_sel[1] or
616	rcm2ctx_ctx_req or ctx_deq or ctx2rcm_nxctx_addr or
617	rcm2ctx_seq_req or seq_deq or ctx2rcm_nxseq_addr or
618	tcm2ctx_lst_req or clst_deq or ctx2tcm_nxlst_addr or
619	ctx_rel or ctx_ret_addr or seq_rel or seq_ret_addr or
620	clst_rel or clst_ret_addr or ctx_is_idle
621	)
622	begin
623	for (i = 0; i < 2; i = i + 1) begin
624	case (dbg_sel[i]) // synopsys infer_mux
625	3'b000: nxt_dbg_bus[i] = {ctx_is_idle,rcm2ctx_ctx_req,ctx_deq,ctx2rcm_nxctx_addr};
626	3'b001: nxt_dbg_bus[i] = {1'b0,rcm2ctx_seq_req,seq_deq,ctx2rcm_nxseq_addr};
627	3'b010: nxt_dbg_bus[i] = {2'b00,tcm2ctx_lst_req,clst_deq,ctx2tcm_nxlst_addr};
628	3'b011: nxt_dbg_bus[i] = {2'b00,ctx_rel,ctx_ret_addr};
629	3'b100: nxt_dbg_bus[i] = {2'b00,seq_rel,seq_ret_addr};
630	3'b101: nxt_dbg_bus[i] = {3'b000,clst_rel,clst_ret_addr};
631	3'b110: nxt_dbg_bus[i] = 8'h00;
632	3'b111: nxt_dbg_bus[i] = 8'h00;
633	endcase // case(dbg_sel[i])
634	end // for (i = 0; i < 2; i = i + 1)
635	end // always @ (dbg_sel[0] or dbg_sel[1] or...
636
637	always @ (posedge clk) begin
638	if(rst_l == 1'b0) begin
639	for (j = 0; j < 2; j = j + 1) begin
640	dbg_bus[j] <= 8'h00;
641	end
642	end
643	else begin
644	for (j = 0; j < 2; j = j + 1) begin
645	dbg_bus[j] <= nxt_dbg_bus[j];
646	end
647	end
648	end // always @ (posedge clk)
649
650
651	// ******************** Output Procedures *********************/
652
653
654
655
656	// *********************Assignments ***************************/
657	assign ctx_rel = tcm2ctx_ret_req & tcm2ctx_ret_addr[RETCTXMSB];
658	assign ctx_ret_addr = tcm2ctx_ret_addr[RETCTXADDRMSB :RETCTXADDRLSB];
659
660	assign seq_rel = tcm2ctx_ret_req & tcm2ctx_ret_addr[RETPSEQMSB];
661	assign seq_ret_addr = tcm2ctx_ret_addr[RETPSEQADDRMSB :RETPSEQADDRLSB];
662
663	assign clst_rel = tcm2ctx_ret_req & tcm2ctx_ret_addr[RETCLSTMSB];
664	assign clst_ret_addr = tcm2ctx_ret_addr[RETCLSTADDRMSB :RETCLSTADDRLSB];
665
666	assign ctx2rcm_ctx_gnt = ctx_deq;
667	assign ctx2rcm_seq_gnt = seq_deq;
668	assign ctx2tcm_lst_gnt = clst_deq;
669
670	// Output assignments
671
672	// Debug
673	assign ctx2dbg_dbg_a = dbg_bus[0];
674	assign ctx2dbg_dbg_b = dbg_bus[1];
675
676	endmodule