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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_cmu_ctx_reg_array.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_cmu_ctx_reg_array ( | |
36 | clk, | |
37 | rst_l, | |
38 | addr0, | |
39 | data0_in, | |
40 | rw0, | |
41 | data0_out, | |
42 | addr1, | |
43 | data1_in, | |
44 | rw1, | |
45 | data1_out | |
46 | ); | |
47 | ||
48 | //************************************************ | |
49 | // PARAMETERS | |
50 | //************************************************ | |
51 | ||
52 | parameter WIDTH = 5, | |
53 | DEPTH = 8, | |
54 | ADDR_WDTH = 3; | |
55 | ||
56 | //************************************************ | |
57 | // PORTS | |
58 | //************************************************ | |
59 | ||
60 | input clk; // input clock | |
61 | input rst_l; // synopsys sync_set_reset "rst_l" | |
62 | ||
63 | input [ADDR_WDTH -1 :0] addr0; | |
64 | input [WIDTH -1 :0] data0_in; // input data | |
65 | input rw0; // syncronous write strobe | |
66 | output [WIDTH - 1:0] data0_out; // output data | |
67 | ||
68 | input [ADDR_WDTH -1 :0] addr1; | |
69 | input [WIDTH -1 :0] data1_in; // input data | |
70 | input rw1; // syncronous write strobe | |
71 | output [WIDTH -1 :0] data1_out; // output data | |
72 | ||
73 | ||
74 | // Flop Array | |
75 | ||
76 | reg [WIDTH -1 :0] reg_array[0 :DEPTH -1]; // The fifo storge arrary | |
77 | ||
78 | integer i; | |
79 | ||
80 | ||
81 | //************************************************ | |
82 | // SIGNALS | |
83 | //************************************************ | |
84 | ||
85 | ||
86 | //************************************************ | |
87 | // Zero In checkers | |
88 | //************************************************ | |
89 | ||
90 | // *************** Procedures *************************************/ | |
91 | // Write access, put the data on the input bus into | |
92 | // the location referenced by the write pointer. | |
93 | // Write contention is guaranteed not to happen | |
94 | // because accessing agents never access same address | |
95 | ||
96 | always @(posedge clk) | |
97 | if(~rst_l) begin : reg_array_rst | |
98 | integer j; | |
99 | for(j=0; j < DEPTH; j=j+1) | |
100 | begin | |
101 | reg_array[j] <= {WIDTH{1'b0}}; | |
102 | end | |
103 | end | |
104 | else begin | |
105 | case({rw0,rw1}) // synopsys parallel_case | |
106 | 2'b00 : begin | |
107 | for(i=0; i < DEPTH; i=i+1) | |
108 | reg_array[i] <= reg_array[i]; | |
109 | end | |
110 | 2'b10 : reg_array[addr0] <= data0_in; | |
111 | 2'b01 : reg_array[addr1] <= data1_in; | |
112 | 2'b11 : begin | |
113 | reg_array[addr0] <= data0_in; | |
114 | reg_array[addr1] <= data1_in; | |
115 | end | |
116 | endcase // case({rw0,rw1}) | |
117 | end // always @ (posedge clk) | |
118 | ||
119 | // ***********************Assignments *****************************/ | |
120 | ||
121 | ||
122 | //*********************************************** | |
123 | // A read returns data referenced by the read pointer | |
124 | //************************************************ | |
125 | ||
126 | assign data0_out = reg_array[addr0]; | |
127 | assign data1_out = reg_array[addr1]; | |
128 | ||
129 | endmodule // dmu_cmu_ctx_reg_array |