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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_cmu_rcm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_cmu_rcm ( | |
36 | clk, | |
37 | rst_l, | |
38 | ||
39 | // Debug | |
40 | dbg2rcm_dbg_sel_a, | |
41 | dbg2rcm_dbg_sel_b, | |
42 | rcm2dbg_dbg_a, | |
43 | rcm2dbg_dbg_b, | |
44 | ||
45 | // MMU | |
46 | mm2cm_rcd_enq, | |
47 | mm2cm_rcd, | |
48 | cm2mm_rcd_full, | |
49 | ||
50 | // PMU | |
51 | cm2pm_rcd_enq, | |
52 | cm2pm_rcd, | |
53 | pm2cm_rcd_full, | |
54 | ||
55 | // CTX | |
56 | rcm2ctx_ctx_req, | |
57 | ctx2rcm_ctx_gnt, | |
58 | ctx2rcm_nxctx_addr, | |
59 | rcm2ctx_ctx_addr, | |
60 | rcm2ctx_ctx_rw, | |
61 | ctx2rcm_cur_ctx, | |
62 | rcm2ctx_ctx, | |
63 | rcm2ctx_seq_req, | |
64 | ctx2rcm_seq_gnt, | |
65 | ctx2rcm_nxseq_addr, | |
66 | rcm2ctx_pkseq_addr, | |
67 | rcm2ctx_pkseq_rw, | |
68 | rcm2ctx_pkseq, | |
69 | ||
70 | // ILU | |
71 | y2k_mps | |
72 | ); | |
73 | ||
74 | //************************************************ | |
75 | // PARAMETERS | |
76 | //************************************************ | |
77 | ||
78 | // Ingress Schedule Record Fields | |
79 | // parameter MM2CM_WDTH = `FIRE_DLC_ISR_REC_WDTH; //79 | |
80 | parameter ISRMSB = `FIRE_DLC_ISR_MSB; // MM2CM_WDTH -1 | |
81 | ||
82 | parameter SRTYP_WDTH = `FIRE_DLC_ISR_TYP_WDTH, // 7 | |
83 | SRLEN_WDTH = `FIRE_DLC_ISR_LEN_WDTH, //10 | |
84 | SRDWBE_WDTH = `FIRE_DLC_ISR_DWBE_WDTH, // 8 | |
85 | SRADDR_WDTH = `FIRE_DLC_ISR_ADDR_WDTH, //41 | |
86 | SRDPTR_WDTH = `FIRE_DLC_ISR_DPTR_WDTH, // 7 | |
87 | SRSBDTAG_WDTH = `FIRE_DLC_ISR_SBDTAG_WDTH; // 5 | |
88 | ||
89 | parameter SRTYPMSB = SRTYP_WDTH -1, | |
90 | SRLENMSB = SRLEN_WDTH -1, | |
91 | SRDWBEMSB = SRDWBE_WDTH -1, | |
92 | SRADDRMSB = SRADDR_WDTH -1, | |
93 | SRDPTRMSB = SRDPTR_WDTH -1, | |
94 | SRSBDTAGMSB = SRSBDTAG_WDTH -1; | |
95 | ||
96 | parameter EXPLENMSB = SRLENMSB +1; | |
97 | ||
98 | ||
99 | // Ingress Packet Record Fields | |
100 | // parameter CM2PM_WDTH = `FIRE_DLC_IPR_REC_WDTH; //93 | |
101 | parameter IPRMSB = `FIRE_DLC_IPR_MSB; // CM2PM_WDTH -1 | |
102 | ||
103 | ||
104 | parameter PRTYP_WDTH = `FIRE_DLC_IPR_TYP_WDTH, // 7 | |
105 | PRLEN_WDTH = `FIRE_DLC_IPR_LEN_WDTH, //10 | |
106 | PRBYTCNT_WDTH = `FIRE_DLC_IPR_BYTCNT_WDTH, //12 | |
107 | PRCNTXTNUM_WDTH = `FIRE_DLC_IPR_CNTXTNUM_WDTH, // 5 | |
108 | PRSEQNUM_WDTH = `FIRE_DLC_IPR_PKSEQNUM_WDTH, // 5 | |
109 | PRADDR_WDTH = `FIRE_DLC_IPR_ADDR_WDTH, //41 | |
110 | PRDPTR_WDTH = `FIRE_DLC_IPR_DPTR_WDTH, // 7 | |
111 | PRSBDTAG_WDTH = `FIRE_DLC_IPR_SBDTAG_WDTH; // 5 | |
112 | ||
113 | parameter PRTYPMSB = PRTYP_WDTH -1, | |
114 | PRLENMSB = PRLEN_WDTH -1, | |
115 | PRBYTCNTMSB = PRBYTCNT_WDTH -1, | |
116 | PRCNTXTNUMMSB = PRCNTXTNUM_WDTH -1, | |
117 | PRSEQNUMMSB = PRSEQNUM_WDTH -1, | |
118 | PRADDRMSB = PRADDR_WDTH -1, | |
119 | PRDPTRMSB = PRDPTR_WDTH -1, | |
120 | PRSBDTAGMSB = PRSBDTAG_WDTH -1; | |
121 | ||
122 | // ILU | |
123 | parameter MPS_WDTH = `FIRE_DLC_MPS; | |
124 | parameter MPSMSB = MPS_WDTH - 1; | |
125 | ||
126 | // CTX | |
127 | // parameter CTXARRAY_WDTH = 43, // Context CTX entry width | |
128 | parameter CTXARRAY_WDTH = 44, // Context CTX entry width | |
129 | CTXARRAYMSB = CTXARRAY_WDTH -1, | |
130 | CTXADDRLSB = 0, | |
131 | CTXADDR_WDTH = 5, | |
132 | CTXADDRMSB = CTXADDRLSB + CTXADDR_WDTH -1; | |
133 | ||
134 | // PKSEQ | |
135 | parameter PSEQARRAY_WDTH = 5, // Context PKSEQ entry width | |
136 | PSEQARRAYMSB = PSEQARRAY_WDTH -1, | |
137 | PSEQADDRLSB = 0, | |
138 | PSEQADDR_WDTH = 5, | |
139 | PSEQADDRMSB = PSEQADDRLSB + PSEQADDR_WDTH -1; | |
140 | ||
141 | parameter CLSTADDRLSB = 0, | |
142 | CLSTADDR_WDTH = 4, | |
143 | CLSTADDRMSB = CLSTADDRLSB + CLSTADDR_WDTH -1; | |
144 | ||
145 | //MISC | |
146 | // parameter CLTOT_WDTH = 5; | |
147 | parameter CLTOT_WDTH = 6; | |
148 | ||
149 | parameter CLTOTMSB = CLTOT_WDTH -1; | |
150 | ||
151 | parameter ORDERBITLSB = 0, //0 | |
152 | ORDERBIT_WDTH = 32, | |
153 | ORDERBITMSB = ORDERBITLSB + ORDERBIT_WDTH -1; //63 | |
154 | ||
155 | //************************************************ | |
156 | // PORTS | |
157 | //************************************************ | |
158 | ||
159 | input clk; // The input clock | |
160 | input rst_l; // synopsys sync_set_reset "rst_l" | |
161 | ||
162 | // RCM | |
163 | input mm2cm_rcd_enq; | |
164 | input [ISRMSB : 0] mm2cm_rcd; | |
165 | output cm2mm_rcd_full; | |
166 | ||
167 | output cm2pm_rcd_enq; | |
168 | output [IPRMSB : 0] cm2pm_rcd; | |
169 | input pm2cm_rcd_full; | |
170 | ||
171 | output rcm2ctx_ctx_req; | |
172 | input ctx2rcm_ctx_gnt; | |
173 | input [CTXADDRMSB :0] ctx2rcm_nxctx_addr; | |
174 | output [CTXADDRMSB :0] rcm2ctx_ctx_addr; | |
175 | output rcm2ctx_ctx_rw; | |
176 | input [CTXARRAYMSB : 0] ctx2rcm_cur_ctx; | |
177 | output [CTXARRAYMSB : 0] rcm2ctx_ctx; | |
178 | output rcm2ctx_seq_req; | |
179 | input ctx2rcm_seq_gnt; | |
180 | input [PSEQADDRMSB :0] ctx2rcm_nxseq_addr; | |
181 | output [PSEQADDRMSB :0] rcm2ctx_pkseq_addr; | |
182 | output rcm2ctx_pkseq_rw; | |
183 | output [PSEQARRAYMSB : 0] rcm2ctx_pkseq; | |
184 | ||
185 | // ILU | |
186 | input [MPSMSB :0] y2k_mps; | |
187 | ||
188 | // Debug | |
189 | input [`FIRE_DLC_CMU_RCM_DS_BITS] dbg2rcm_dbg_sel_a; | |
190 | input [`FIRE_DLC_CMU_RCM_DS_BITS] dbg2rcm_dbg_sel_b; | |
191 | output [`FIRE_DBG_DATA_BITS] rcm2dbg_dbg_a; | |
192 | output [`FIRE_DBG_DATA_BITS] rcm2dbg_dbg_b; | |
193 | ||
194 | //************************************************ | |
195 | // Functions | |
196 | //************************************************ | |
197 | ||
198 | function [EXPLENMSB :0] get_rem_payld; | |
199 | input [EXPLENMSB :0] length; | |
200 | input [MPSMSB :0] payload; | |
201 | reg [EXPLENMSB :0] return; | |
202 | ||
203 | begin | |
204 | case(payload) // synopsys parallel_case | |
205 | 3'b000 : return = {6'h00,5'h1f} & length; // 128 | |
206 | 3'b001 : return = {5'h00,6'h3f} & length; // 256 | |
207 | 3'b010 : return = {4'h0 ,7'h7f} & length; // 512 | |
208 | default : return = 11'h001; // payloads > 512 are not supported | |
209 | endcase // case(maxpayload) | |
210 | ||
211 | get_rem_payld = return; | |
212 | ||
213 | end | |
214 | endfunction // get_rem_payld | |
215 | ||
216 | function [EXPLENMSB :0] get_payld_offset; | |
217 | input [EXPLENMSB :0] length; | |
218 | input [MPSMSB :0] maxpayload; | |
219 | reg [EXPLENMSB :0] return; | |
220 | ||
221 | begin | |
222 | case(maxpayload) // synopsys parallel_case | |
223 | 3'b000 : return = length >> 5; // 128 | |
224 | 3'b001 : return = length >> 6; // 256 | |
225 | 3'b010 : return = length >> 7; // 512 | |
226 | default : return = 11'h001; // payloads > 512 are not supported | |
227 | endcase // case(maxpayload) | |
228 | ||
229 | get_payld_offset = return; | |
230 | ||
231 | end | |
232 | endfunction // get_payld_offset | |
233 | ||
234 | ||
235 | function [CLTOTMSB :0] num_paylds; // added muxes to make vlint happy | |
236 | input [EXPLENMSB :0] length; | |
237 | input [MPSMSB :0] maxpayload; | |
238 | reg [EXPLENMSB :0] result; | |
239 | reg [CLTOTMSB :0] return; | |
240 | ||
241 | begin | |
242 | result = get_rem_payld(length, maxpayload); | |
243 | ||
244 | if (result == 0) begin | |
245 | case(maxpayload) // synopsys parallel_case | |
246 | 3'b000 : return = {length[EXPLENMSB :5]}; // 128 | |
247 | 3'b001 : return = {1'h0,length[EXPLENMSB :6]}; // 256 | |
248 | 3'b010 : return = {2'h0,length[EXPLENMSB :7]}; // 512 | |
249 | default : return = 6'h01; // payloads > 512 are not supported | |
250 | endcase // case(maxpayload) | |
251 | end | |
252 | else begin | |
253 | case(maxpayload) // synopsys parallel_case | |
254 | 3'b000 : return = {length[EXPLENMSB :5]} + 6'h01; // 128 | |
255 | 3'b001 : return = {1'h0,length[EXPLENMSB :6]} + 6'h01; // 256 | |
256 | 3'b010 : return = {2'h0,length[EXPLENMSB :7]} + 6'h01; // 512 | |
257 | default : return = 6'h01; // payloads > 512 are not supported | |
258 | endcase // case(maxpayload) | |
259 | end | |
260 | ||
261 | num_paylds = return[CLTOTMSB :0]; | |
262 | ||
263 | end | |
264 | endfunction // num_paylds | |
265 | ||
266 | function [PRBYTCNTMSB :0] byt_cnt; | |
267 | input [EXPLENMSB :0] length; | |
268 | input [SRDWBEMSB :0] dwbe; | |
269 | ||
270 | reg [2:0] frst_dw_bytcnt; | |
271 | reg [2:0] last_dw_bytcnt; | |
272 | reg [2:0] one_dw_bytcnt; | |
273 | reg is_one_dw; | |
274 | reg [3:0] fst_dwbe; | |
275 | reg [3:0] lst_dwbe; | |
276 | reg [1:0] minus_fst; | |
277 | reg [1:0] minus_lst; | |
278 | reg [2:0] minus_all; | |
279 | reg [PRBYTCNTMSB :0] raw_bytcnt; | |
280 | reg [PRBYTCNTMSB :0] final_bytcnt; | |
281 | ||
282 | begin | |
283 | fst_dwbe = dwbe[3:0]; | |
284 | lst_dwbe = dwbe[7:4]; | |
285 | is_one_dw = ~|length[EXPLENMSB-1:1] & length[0]; | |
286 | ||
287 | casez (fst_dwbe) | |
288 | 4'b0000 : frst_dw_bytcnt = 3'h0; | |
289 | 4'b1000 : frst_dw_bytcnt = 3'h1; | |
290 | 4'b0100 : frst_dw_bytcnt = 3'h1; | |
291 | 4'b0010 : frst_dw_bytcnt = 3'h1; | |
292 | 4'b0001 : frst_dw_bytcnt = 3'h1; | |
293 | 4'b1100 : frst_dw_bytcnt = 3'h2; | |
294 | 4'b0110 : frst_dw_bytcnt = 3'h2; | |
295 | 4'b0011 : frst_dw_bytcnt = 3'h2; | |
296 | 4'b1z10 : frst_dw_bytcnt = 3'h3; | |
297 | 4'b01z1 : frst_dw_bytcnt = 3'h3; | |
298 | 4'b1zz1 : frst_dw_bytcnt = 3'h4; | |
299 | endcase // casez(fst_dwbe) | |
300 | ||
301 | casez (lst_dwbe) | |
302 | 4'b0000 : last_dw_bytcnt = 3'h0; | |
303 | 4'b1000 : last_dw_bytcnt = 3'h1; | |
304 | 4'b0100 : last_dw_bytcnt = 3'h1; | |
305 | 4'b0010 : last_dw_bytcnt = 3'h1; | |
306 | 4'b0001 : last_dw_bytcnt = 3'h1; | |
307 | 4'b1100 : last_dw_bytcnt = 3'h2; | |
308 | 4'b0110 : last_dw_bytcnt = 3'h2; | |
309 | 4'b0011 : last_dw_bytcnt = 3'h2; | |
310 | 4'b1z10 : last_dw_bytcnt = 3'h3; | |
311 | 4'b01z1 : last_dw_bytcnt = 3'h3; | |
312 | 4'b1zz1 : last_dw_bytcnt = 3'h4; | |
313 | endcase // casez(last_dwbe) | |
314 | ||
315 | ||
316 | if (dwbe[0]) minus_fst = 2'b00; | |
317 | else if (dwbe[1]) minus_fst = 2'b01; | |
318 | else if (dwbe[2]) minus_fst = 2'b10; | |
319 | else if (dwbe[3]) minus_fst = 2'b11; | |
320 | else minus_fst = 2'b00; | |
321 | ||
322 | if (dwbe[7]) minus_lst = 2'b00; | |
323 | else if (dwbe[6]) minus_lst = 2'b01; | |
324 | else if (dwbe[5]) minus_lst = 2'b10; | |
325 | else if (dwbe[4]) minus_lst = 2'b11; | |
326 | else minus_lst = 2'b00; | |
327 | ||
328 | minus_all = {1'b0,minus_fst} + {1'b0,minus_lst}; | |
329 | one_dw_bytcnt = frst_dw_bytcnt + last_dw_bytcnt; | |
330 | raw_bytcnt = {1'b0, length << 2}; | |
331 | final_bytcnt = raw_bytcnt - {9'h000,minus_all}; | |
332 | ||
333 | byt_cnt = is_one_dw ? (((fst_dwbe == 4'h0) && (lst_dwbe == 4'h0)) | |
334 | ? {9'h000, 3'h1} : {9'h000,one_dw_bytcnt}) | |
335 | : final_bytcnt; | |
336 | ||
337 | end | |
338 | endfunction // byt_cnt | |
339 | ||
340 | ||
341 | //************************************************ | |
342 | // SIGNALS | |
343 | //************************************************ | |
344 | ||
345 | wire clk; | |
346 | wire rst_l; | |
347 | ||
348 | wire [EXPLENMSB : 0] cacheline; | |
349 | ||
350 | // Schedule Record queue signals | |
351 | wire srmpty; | |
352 | ||
353 | // Schedule Record field assignments to RCM signals | |
354 | wire [SRTYPMSB :0] srtyp; | |
355 | wire [SRLENMSB :0] srlen; | |
356 | wire [SRDWBEMSB :0] srdwbe; | |
357 | wire [SRADDRMSB :0] sraddr; | |
358 | wire sraddrerr; | |
359 | wire [SRDPTRMSB :0] srdptr; | |
360 | wire [SRSBDTAGMSB :0] srtr_tag; | |
361 | ||
362 | wire [EXPLENMSB :0] part_len; | |
363 | wire [EXPLENMSB :0] sel_payld_len; | |
364 | wire [EXPLENMSB :0] first_len; | |
365 | wire [EXPLENMSB :0] restof_len; | |
366 | ||
367 | wire fourk_bit; | |
368 | wire [EXPLENMSB :0] explen; | |
369 | ||
370 | //RCM - CTX | |
371 | reg rcm2ctx_ctx_req; | |
372 | reg [CTXADDRMSB :0] rcm2ctx_ctx_addr; | |
373 | reg rcm2ctx_ctx_rw; | |
374 | ||
375 | reg [ORDERBITMSB :0] new_order_bits; | |
376 | ||
377 | reg [CLTOTMSB +1 :0] j; // indicies for setting order_bits | |
378 | reg [CTXARRAYMSB : 0] cur_ctx; | |
379 | reg [EXPLENMSB :0] maxpyld; | |
380 | ||
381 | wire ctx2rcm_ctx_gnt; | |
382 | wire [CTXADDRMSB :0] ctx2rcm_nxctx_addr; | |
383 | wire [CTXARRAYMSB : 0] ctx2rcm_cur_ctx; | |
384 | reg [CTXARRAYMSB : 0] rcm2ctx_ctx; | |
385 | ||
386 | reg rcm2ctx_seq_req; | |
387 | wire ctx2rcm_seq_gnt; | |
388 | wire [PSEQADDRMSB :0] ctx2rcm_nxseq_addr; | |
389 | reg [PSEQADDRMSB :0] rcm2ctx_pkseq_addr; | |
390 | reg rcm2ctx_pkseq_rw; | |
391 | wire [PSEQARRAYMSB : 0] rcm2ctx_pkseq; | |
392 | ||
393 | reg first_ctx_gnt; | |
394 | ||
395 | // Multicycle signals | |
396 | wire [9 :0] lo_addr; | |
397 | wire [9 :0] payld_lo_addr; | |
398 | wire pipe_mpty; | |
399 | ||
400 | reg xfr_strt; | |
401 | ||
402 | // Registers | |
403 | reg [PRTYPMSB :0] pkt_typ; | |
404 | reg [PRLENMSB :0] pkt_len; | |
405 | reg [PRBYTCNTMSB :0] pkt_byt_cnt; | |
406 | reg [PRCNTXTNUMMSB :0] pkt_cntxt_num; | |
407 | reg [PRSEQNUMMSB :0] pkt_seq_num; | |
408 | reg [PRADDRMSB :0] pkt_addr; | |
409 | reg pkt_addr_err; | |
410 | reg [PRDPTRMSB :0] pkt_dptr; | |
411 | reg [PRSBDTAGMSB :0] pkt_tr_tag; | |
412 | ||
413 | reg [EXPLENMSB :0] next_pktlen; | |
414 | reg [PRBYTCNTMSB :0] next_pktbyt_cnt; | |
415 | reg [PRCNTXTNUMMSB :0] next_pktcntxt_num; | |
416 | reg [PRSEQNUMMSB :0] next_pktseq_num; | |
417 | reg [PRADDRMSB :0] next_pktaddr; | |
418 | reg [PRDPTRMSB :0] next_pktdptr; | |
419 | reg [PRSBDTAGMSB :0] next_pkttr_tag; | |
420 | ||
421 | reg [SRTYPMSB :0] pipe_typ; | |
422 | reg [EXPLENMSB :0] pipe_len; | |
423 | reg [EXPLENMSB :0] pipe_srlen; | |
424 | ||
425 | reg [PRBYTCNTMSB :0] pipe_bytcnt; | |
426 | reg [PRCNTXTNUMMSB :0] pipe_cntxtnum; | |
427 | reg [PRSEQNUMMSB :0] pipe_seqnum; | |
428 | reg [PRADDRMSB :0] pipe_addr; | |
429 | reg [PRADDRMSB :10] pipe_addr_hi; | |
430 | reg pipe_addrerr; | |
431 | reg [SRDWBEMSB :0] pipe_dwbe; | |
432 | reg [PRDPTRMSB :0] pipe_dptr; | |
433 | reg [SRSBDTAGMSB :0] pipe_trtag; | |
434 | reg [CLTOTMSB :0] pipe_cycles; | |
435 | reg pipe_mcycle; | |
436 | ||
437 | wire [EXPLENMSB :0] temp_len; | |
438 | wire [EXPLENMSB :0] temp_payld_len; | |
439 | reg [EXPLENMSB :0] adj_len; | |
440 | reg [EXPLENMSB :0] adj_payld_len; | |
441 | wire [EXPLENMSB : 0] payld_offset; | |
442 | reg [EXPLENMSB :0] rem_payld_len; | |
443 | ||
444 | reg [PRTYPMSB :0] cyc_typ; | |
445 | reg [EXPLENMSB :0] cyc_len; | |
446 | reg [PRBYTCNTMSB :0] cyc_bytcnt; | |
447 | reg [PRCNTXTNUMMSB :0] cyc_cntxtnum; | |
448 | reg [PRSEQNUMMSB :0] cyc_seqnum; | |
449 | reg [SRADDRMSB :0] cyc_addr; | |
450 | reg cyc_addrerr; | |
451 | reg [SRSBDTAGMSB :0] cyc_trtag; | |
452 | reg [SRDPTRMSB :0] cyc_dptr; | |
453 | ||
454 | reg [SRDWBEMSB :0] new_payld_dwbe; | |
455 | reg [3 :0] pipe_lastdwbe; | |
456 | reg [3 :0] lastdwbe; | |
457 | ||
458 | reg [CLTOTMSB :0] num_cmd; | |
459 | reg [CLTOTMSB :0] cycles; | |
460 | reg [CLTOTMSB :0] next_cycles; | |
461 | ||
462 | reg next_multicycle; | |
463 | ||
464 | reg next_deq_sr; | |
465 | reg next_gen_pkt; | |
466 | reg next_pkseq_req; | |
467 | reg next_rcd_enq; | |
468 | reg cm2pm_rcd_enq; | |
469 | reg next_gen_ctx; | |
470 | reg next_ctx_req; | |
471 | ||
472 | reg [1:0] deq_state; | |
473 | reg [1:0] deq_next; | |
474 | ||
475 | reg [1:0] ctx_state; | |
476 | reg [1:0] ctx_next; | |
477 | ||
478 | reg [1:0] seq_state; | |
479 | reg [1:0] seq_next; | |
480 | ||
481 | reg [2:0] bld_state; | |
482 | reg [2:0] bld_next; | |
483 | ||
484 | ||
485 | reg [2 :0] next_clastyp; | |
486 | reg [2 :0] pipe_clastyp; | |
487 | reg [2 :0] clastyp; | |
488 | ||
489 | reg multicycle; | |
490 | reg ld_ptr; | |
491 | reg pipe_full; | |
492 | reg next_deq_pipe; | |
493 | reg deq_pipe; | |
494 | reg ld_pipe; | |
495 | ||
496 | reg rcm_is_idle; | |
497 | ||
498 | // Debug | |
499 | reg [`FIRE_DLC_CMU_RCM_DS_BITS] dbg_sel [0:1]; | |
500 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; | |
501 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1]; | |
502 | integer i, k; | |
503 | ||
504 | // Schedule queue signals | |
505 | ||
506 | // wire overflow; //for debug use | |
507 | // wire underflow; //for debug use | |
508 | ||
509 | // *************** Local Declarations ************************************* | |
510 | ||
511 | parameter DEQIDLE = 2'b00, // no work to do | |
512 | DEQPIPE = 2'b01, // load pipeline with current packet | |
513 | DEQ = 2'b10; // dequeue next packet | |
514 | ||
515 | parameter CTXIDLE = 2'b00, // Context Number Request Idle | |
516 | CTXGNT = 2'b01; // Context number Request granted | |
517 | ||
518 | parameter SEQIDLE = 2'b00, // Packet Sequence Address Request Idle | |
519 | SEQGNT = 2'b01, // Packet Sequence Address Request granted | |
520 | SEQWAIT = 2'b10; // wait for pipeline to unstall | |
521 | ||
522 | parameter BLDIDLE = 3'b000, // Build Context Idle | |
523 | BLDCNTX = 3'b010, // Context ops in progress | |
524 | BLDBPAS = 3'b011; // NO context ops needed | |
525 | ||
526 | parameter CLASWR = 3'b001, // Schedule record is a Write | |
527 | CLASRD = 3'b010, // Schedule record is a Read | |
528 | CLASPIO = 3'b011, // Schedule record is a PIO | |
529 | CLASMSI = 3'b100, // Schedule record is a MSI | |
530 | CLASMSC = 3'b101, // Schedule record is a Misc | |
531 | CLASMDO = 3'b110; // Schedule record is a Mondo | |
532 | ||
533 | //************************************************ | |
534 | // Zero In checkers | |
535 | //************************************************ | |
536 | ||
537 | // Request Grant check for ctx number | |
538 | // 0in req_ack -req rcm2ctx_ctx_req -ack ctx2rcm_ctx_gnt -req_until_ack | |
539 | ||
540 | // Request Grant check for pkseq number | |
541 | // 0in req_ack -req rcm2ctx_seq_req -ack ctx2rcm_seq_gnt -req_until_ack | |
542 | ||
543 | // deq_fsm | |
544 | //0in state_transition -var deq_state -val DEQIDLE -next DEQIDLE DEQPIPE | |
545 | //0in state_transition -var deq_state -val DEQPIPE -next DEQPIPE DEQ | |
546 | //0in state_transition -var deq_state -val DEQ -next DEQIDLE | |
547 | ||
548 | // ctx_fsm | |
549 | //0in state_transition -var ctx_state -val CTXIDLE -next CTXIDLE CTXGNT | |
550 | //0in state_transition -var ctx_state -val CTXGNT -next CTXGNT CTXIDLE | |
551 | ||
552 | // seq_fsm | |
553 | //0in state_transition -var seq_state -val SEQIDLE -next SEQIDLE SEQGNT | |
554 | //0in state_transition -var seq_state -val SEQGNT -next SEQGNT SEQIDLE SEQWAIT | |
555 | //0in state_transition -var seq_state -val SEQWAIT -next SEQWAIT SEQIDLE | |
556 | ||
557 | // build_crcd (pipeline staging and command record build) | |
558 | //0in state_transition -var bld_state -val BLDIDLE -next BLDIDLE BLDCNTX BLDBPAS | |
559 | //0in state_transition -var bld_state -val BLDCNTX -next BLDCNTX BLDIDLE | |
560 | //0in state_transition -var bld_state -val BLDBPAS -next BLDBPAS BLDIDLE | |
561 | ||
562 | // *************** Procedures ************************************* | |
563 | ||
564 | // Transaction Type Decode - context ops encoding | |
565 | always @(srtyp) | |
566 | begin | |
567 | case (srtyp) // synopsys parallel_case | |
568 | 7'b0000000 : next_clastyp = CLASRD; // DMAMR | |
569 | 7'b0100000 : next_clastyp = CLASRD; // DMAMR | |
570 | 7'b0000001 : next_clastyp = CLASMSC; // DMAMRDLK | |
571 | 7'b0100001 : next_clastyp = CLASMSC; // DMARDLK_alt | |
572 | 7'b0001001 : next_clastyp = CLASMSC; // UNSUP | |
573 | 7'b1000000 : next_clastyp = CLASWR; // DMAMWR | |
574 | 7'b1100000 : next_clastyp = CLASWR; // DMAMWR | |
575 | 7'b1111000 : next_clastyp = CLASMSI; // MSIEQWR | |
576 | 7'b1011000 : next_clastyp = CLASMSI; // MSIEQWR | |
577 | 7'b1010000 : next_clastyp = CLASMSI; // MSGEQWR | |
578 | 7'b1110000 : next_clastyp = CLASMSI; // MSGEQWR | |
579 | 7'b1111100 : next_clastyp = CLASMSC; // NULL | |
580 | 7'b1111010 : next_clastyp = CLASMDO; // MDO | |
581 | 7'b0001010 : next_clastyp = CLASPIO; // PIOCP | |
582 | 7'b1001010 : next_clastyp = CLASPIO; // PIOCPLD | |
583 | default : next_clastyp = 3'b111; // to satisfy vlint | |
584 | endcase // case(srtyp) | |
585 | end // always @ (srtyp) | |
586 | ||
587 | // Parse Schedule Record to issue Packet Records | |
588 | // lengths are represented in DW's | |
589 | ||
590 | always @(next_clastyp or sraddr or cacheline or part_len or first_len | |
591 | or srlen or srdwbe or srdptr or srtr_tag or sraddrerr or maxpyld | |
592 | or y2k_mps or explen or restof_len) | |
593 | begin | |
594 | next_pktlen[EXPLENMSB :0] = 0; | |
595 | next_pktbyt_cnt[PRBYTCNTMSB :0] = 0; | |
596 | next_pktcntxt_num[PRCNTXTNUMMSB :0] = 0; | |
597 | next_pktseq_num[PRSEQNUMMSB :0] = 0; | |
598 | next_pktaddr[PRADDRMSB :0] = 0; | |
599 | next_pktdptr[PRDPTRMSB :0] = 0; | |
600 | next_pkttr_tag[PRSBDTAGMSB :0] = 0; | |
601 | next_multicycle = 1'b0; | |
602 | next_cycles = 6'h01; | |
603 | ||
604 | case (next_clastyp) // synopsys full_case parallel_case | |
605 | CLASWR: begin // DMA Wr | |
606 | if (explen <= cacheline) begin //(length LE 16) | |
607 | next_pktcntxt_num = 0; | |
608 | next_pktseq_num = 0; | |
609 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
610 | ||
611 | if (sraddr[3:0] == 4'h0) begin | |
612 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
613 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
614 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
615 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
616 | next_multicycle = 1'b0; | |
617 | next_cycles = 6'h01; | |
618 | end | |
619 | else begin // (sraddr[3:0] != 4'h0) | |
620 | if (explen > part_len) begin | |
621 | next_pktlen = part_len[EXPLENMSB :0]; // DW's | |
622 | next_pktbyt_cnt = {4'h0,4'hf,srdwbe[3 :0]}; | |
623 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
624 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
625 | next_multicycle = 1'b1; | |
626 | next_cycles = 6'h02; | |
627 | end | |
628 | else begin | |
629 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
630 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
631 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
632 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
633 | next_multicycle = 1'b0; | |
634 | next_cycles = 6'h01; | |
635 | end // else: !if(explen > part_len) | |
636 | end // else: !if(sraddr[3:0] == 4'h0) | |
637 | end // if ((srlen <= cacheline) begin... | |
638 | ||
639 | if (explen > cacheline) begin //(length GT 16) | |
640 | next_pktcntxt_num = 0; | |
641 | next_pktseq_num = 0; | |
642 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
643 | ||
644 | if (sraddr[3:0] == 4'h0) begin | |
645 | if (srdwbe[7:0] == 8'hff) begin | |
646 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
647 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
648 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
649 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
650 | next_multicycle = 1'b0; | |
651 | next_cycles = 6'h01; | |
652 | end | |
653 | else begin | |
654 | next_pktlen = part_len[EXPLENMSB :0]; | |
655 | next_pktbyt_cnt = {4'h0,4'hf,srdwbe[3 :0]}; | |
656 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
657 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
658 | next_multicycle = 1'b1; | |
659 | next_cycles = 6'h02; | |
660 | end // else: !if(srdwbe[7:0] == 8'hff) | |
661 | end // if (sraddr[3:0] == 4'h0) | |
662 | else begin // sraddr[3:0] != 4'h0 | |
663 | next_pktlen = part_len[EXPLENMSB :0]; | |
664 | next_pktbyt_cnt = {4'h0,4'hf,srdwbe[3 :0]}; | |
665 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
666 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
667 | next_multicycle = 1'b1; | |
668 | next_cycles = 6'h02; | |
669 | end // else: !if(sraddr[3:0] == 4'h0) | |
670 | end // if (srlen > cacheline) | |
671 | end // case: CLASWR | |
672 | ||
673 | CLASRD : begin // DMA Rd | |
674 | if (explen <= cacheline) begin //(length LE 16) | |
675 | if ( srlen == 10'h001) next_pktbyt_cnt = {4'h0, 4'h0, srdwbe[3 :0]}; | |
676 | else next_pktbyt_cnt = {4'h0 , srdwbe[SRDWBEMSB :0]}; | |
677 | next_pktcntxt_num = 0; | |
678 | next_pktseq_num = 0; | |
679 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
680 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
681 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
682 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
683 | next_multicycle = 1'b0; | |
684 | next_cycles = 6'h01; | |
685 | end // if (explen <= cacheline) | |
686 | ||
687 | if (explen > cacheline) begin //(length GT 16) | |
688 | next_pktcntxt_num = 0; | |
689 | next_pktseq_num = 0; | |
690 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
691 | ||
692 | if (sraddr[3:0] == 4'h0) begin // aligned | |
693 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
694 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
695 | ||
696 | if (sraddrerr) begin | |
697 | next_pktlen = explen[EXPLENMSB :0]; | |
698 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
699 | next_multicycle = 1'b0; | |
700 | next_cycles = 6'h01; | |
701 | end | |
702 | else begin | |
703 | if(explen <= maxpyld) begin | |
704 | next_pktlen = explen[EXPLENMSB :0]; | |
705 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
706 | next_multicycle = 1'b0; | |
707 | next_cycles = 6'h01; | |
708 | end | |
709 | else begin | |
710 | next_pktlen = maxpyld; | |
711 | if (srdwbe[3:0] == 4'hf) next_pktbyt_cnt = {4'h0,8'hff}; | |
712 | else next_pktbyt_cnt = {4'h0,4'hf,srdwbe[3 :0]}; | |
713 | next_multicycle = 1'b1; | |
714 | next_cycles = (num_paylds(explen, y2k_mps)); | |
715 | end | |
716 | end // else: !if(sraddrerr) | |
717 | end // if (sraddr[3:0] == 4'h0) | |
718 | else begin // un-aligned | |
719 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
720 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
721 | ||
722 | if (sraddrerr) begin | |
723 | next_pktlen = explen[EXPLENMSB :0]; | |
724 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
725 | next_multicycle = 1'b0; | |
726 | next_cycles = 6'h01; | |
727 | end | |
728 | else begin | |
729 | if(explen <= maxpyld) begin | |
730 | next_pktlen = explen[EXPLENMSB :0]; | |
731 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
732 | next_multicycle = 1'b0; | |
733 | next_cycles = 6'h01; | |
734 | end | |
735 | else begin | |
736 | next_pktlen = first_len[EXPLENMSB :0]; | |
737 | if (srdwbe[3:0] == 4'hf) next_pktbyt_cnt = {4'h0,8'hff}; | |
738 | else next_pktbyt_cnt = {4'h0,4'hf,srdwbe[3 :0]}; | |
739 | next_multicycle = 1'b1; | |
740 | next_cycles = 6'h01 + (num_paylds(restof_len, y2k_mps)); | |
741 | end | |
742 | end // else: !if(sraddrerr) | |
743 | end // else: !if(sraddr[3:0] == 4'h0) | |
744 | end // if (explen > cacheline) | |
745 | end // case: CLASRD | |
746 | ||
747 | CLASPIO : begin // PIO CplD | |
748 | next_pktcntxt_num = {1'b0,srdwbe[3 :0]}; | |
749 | next_pktseq_num = 0; | |
750 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
751 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
752 | next_pktbyt_cnt = 0; | |
753 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
754 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
755 | next_multicycle = 1'b0; | |
756 | next_cycles = 6'h01; | |
757 | end | |
758 | ||
759 | CLASMDO : begin //Mondo Wr | |
760 | next_pktcntxt_num = 0; | |
761 | next_pktseq_num = 0; | |
762 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
763 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
764 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
765 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
766 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
767 | next_multicycle = 1'b0; | |
768 | next_cycles = 6'h01; | |
769 | end | |
770 | ||
771 | CLASMSI : begin //MSI,MSG Wr | |
772 | next_pktcntxt_num = 0; | |
773 | next_pktseq_num = 0; | |
774 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
775 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
776 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
777 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
778 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
779 | next_multicycle = 1'b0; | |
780 | next_cycles = 6'h01; | |
781 | end | |
782 | CLASMSC : begin // Unsup req | |
783 | next_pktcntxt_num = 0; | |
784 | next_pktseq_num = 0; | |
785 | next_pkttr_tag = srtr_tag[SRSBDTAGMSB :0]; | |
786 | next_pktlen = explen[EXPLENMSB :0]; // DW's | |
787 | next_pktbyt_cnt = {4'h0,srdwbe[SRDWBEMSB :0]}; | |
788 | next_pktaddr = sraddr[SRADDRMSB :0]; | |
789 | next_pktdptr = srdptr[SRDPTRMSB :0]; | |
790 | next_multicycle = 1'b0; | |
791 | next_cycles = 6'h01; | |
792 | end | |
793 | ||
794 | default begin | |
795 | next_pktcntxt_num = 0; | |
796 | next_pktseq_num = 0; | |
797 | next_pkttr_tag = 0; | |
798 | next_pktlen = 0; // DW's | |
799 | next_pktbyt_cnt = 0; | |
800 | next_pktaddr = 0; | |
801 | next_pktdptr = 0; | |
802 | next_multicycle = 0; | |
803 | next_cycles = 0; | |
804 | end | |
805 | endcase // case(next_clastyp) | |
806 | end // always @ (next_clastyp or sraddrerr or srlen or sraddr or byt_cnt... | |
807 | ||
808 | // Maxpayload decoder | |
809 | always @(posedge clk) | |
810 | begin | |
811 | if (rst_l == 1'b0) begin | |
812 | maxpyld <= 0; | |
813 | end | |
814 | else begin | |
815 | case (y2k_mps) // synopsys parallel_case | |
816 | 3'b000 : maxpyld <= 11'h020; | |
817 | 3'b001 : maxpyld <= 11'h040; | |
818 | 3'b010 : maxpyld <= 11'h080; | |
819 | default : maxpyld <= 11'h010; // payloads > 512 are not supported | |
820 | endcase // case(y2k_mps) // RCM will force length = 10DW | |
821 | end // else: !if(!rst_l == 1'b1) | |
822 | end // always @ (posedge clk) | |
823 | ||
824 | // Multicycle Parse Schedule Record to issue Packet Records | |
825 | // lengths are represented in DW's | |
826 | ||
827 | // Order Bit updates | |
828 | // work around code re-write to make 0-in happy | |
829 | // Zero-In cannot unroll for loops well enough to | |
830 | // understand just bit wiring, but it does understand | |
831 | // muxes | |
832 | ||
833 | always @(cycles) | |
834 | begin | |
835 | for( j = 7'b0; j < 7'd32; j = j + 1'b1) | |
836 | new_order_bits[j[CLTOTMSB -1 :0]] = (j < {1'b0,cycles}) ? 1'b1 : 1'b0; | |
837 | end | |
838 | ||
839 | // Pipelined staging for Packet record processing | |
840 | always @(posedge clk) | |
841 | if(~rst_l) begin | |
842 | pipe_clastyp <= 3'b0; | |
843 | pipe_typ <= {SRTYP_WDTH{1'b0}}; | |
844 | pipe_len <= {(SRLEN_WDTH +1){1'b0}}; | |
845 | pipe_srlen <= {(SRLEN_WDTH +1){1'b0}}; | |
846 | pipe_bytcnt <= {PRBYTCNT_WDTH{1'b0}}; | |
847 | pipe_cntxtnum <= {PRCNTXTNUM_WDTH{1'b0}}; | |
848 | pipe_seqnum <= {PRSEQNUM_WDTH{1'b0}}; | |
849 | pipe_addr <= {PRADDR_WDTH{1'b0}}; | |
850 | pipe_addr_hi <= {PRADDR_WDTH - 10{1'b0}}; | |
851 | pipe_addrerr <= {{1'b0}}; | |
852 | pipe_lastdwbe <= {4{1'b0}}; | |
853 | pipe_dwbe <= {SRDWBE_WDTH{1'b0}}; | |
854 | pipe_dptr <= {PRDPTR_WDTH{1'b0}}; | |
855 | pipe_trtag <= {SRSBDTAG_WDTH{1'b0}}; | |
856 | pipe_cycles <= {CLTOT_WDTH{1'b0}}; | |
857 | pipe_mcycle <= {{1'b0}}; | |
858 | end | |
859 | else begin | |
860 | pipe_clastyp <= ld_pipe ? next_clastyp : pipe_clastyp; | |
861 | pipe_typ <= ld_pipe ? srtyp : pipe_typ; | |
862 | pipe_len <= ld_pipe ? next_pktlen : pipe_len; | |
863 | pipe_srlen <= ld_pipe ? explen : pipe_srlen; | |
864 | pipe_bytcnt <= ld_pipe ? next_pktbyt_cnt : pipe_bytcnt; | |
865 | pipe_cntxtnum <= ld_pipe ? next_pktcntxt_num : pipe_cntxtnum; | |
866 | pipe_seqnum <= ld_pipe ? next_pktseq_num : pipe_seqnum; | |
867 | pipe_addr <= ld_pipe ? next_pktaddr : pipe_addr; | |
868 | pipe_addr_hi <= ld_pipe ? next_pktaddr[PRADDRMSB :10] : pipe_addr_hi; | |
869 | pipe_addrerr <= ld_pipe ? sraddrerr : pipe_addrerr; | |
870 | pipe_lastdwbe <= ld_pipe ? srdwbe[7:4] : pipe_lastdwbe; | |
871 | ||
872 | case(next_clastyp) // synopsys parallel_case | |
873 | CLASRD : begin | |
874 | pipe_dwbe <= ld_pipe ? next_pktbyt_cnt[SRDWBEMSB :0] : pipe_dwbe; | |
875 | end | |
876 | ||
877 | CLASWR, | |
878 | CLASPIO, | |
879 | CLASMSI, | |
880 | CLASMSC, | |
881 | CLASMDO : begin | |
882 | pipe_dwbe <= ld_pipe ? srdwbe : pipe_dwbe; | |
883 | end | |
884 | ||
885 | default : begin | |
886 | pipe_dwbe <= ld_pipe ? srdwbe : pipe_dwbe; | |
887 | end | |
888 | endcase // case(next_clastyp) | |
889 | ||
890 | pipe_dptr <= ld_pipe ? next_pktdptr : pipe_dptr; | |
891 | pipe_trtag <= ld_pipe ? next_pkttr_tag : pipe_trtag; | |
892 | pipe_cycles <= ld_pipe ? next_cycles : pipe_cycles; | |
893 | pipe_mcycle <= ld_pipe ? next_multicycle : pipe_mcycle; | |
894 | end // always @ (posedge clk) | |
895 | ||
896 | always @(posedge clk) | |
897 | begin | |
898 | if (rst_l == 1'b0) begin | |
899 | multicycle <= 0; | |
900 | cycles <= 6'h01; | |
901 | adj_len <= 0; | |
902 | adj_payld_len <= 0; | |
903 | new_payld_dwbe <= 0; | |
904 | rem_payld_len <= 0; | |
905 | lastdwbe <= 0; | |
906 | end | |
907 | else begin | |
908 | case (bld_state) // synopsys parallel_case | |
909 | BLDIDLE : begin | |
910 | multicycle <= pipe_mcycle; | |
911 | cycles <= pipe_cycles; | |
912 | adj_len <= pipe_srlen; | |
913 | adj_payld_len <= pipe_srlen; | |
914 | new_payld_dwbe <= pipe_dwbe; | |
915 | rem_payld_len <= 0; | |
916 | lastdwbe <= pipe_lastdwbe; | |
917 | end | |
918 | BLDBPAS : begin | |
919 | multicycle <= multicycle; | |
920 | cycles <= cycles; | |
921 | adj_len <= ld_ptr ? (adj_len - cyc_len) : adj_len; | |
922 | adj_payld_len <= (multicycle & xfr_strt) | |
923 | ? (adj_payld_len - cyc_len) | |
924 | : adj_payld_len; | |
925 | new_payld_dwbe <= (payld_offset != 0) | |
926 | ? 8'hff | |
927 | : {pipe_dwbe[7:4], 4'hf}; | |
928 | rem_payld_len <= get_rem_payld(temp_payld_len,y2k_mps); | |
929 | lastdwbe <= lastdwbe; | |
930 | ||
931 | end | |
932 | BLDCNTX : begin | |
933 | multicycle <= multicycle; | |
934 | cycles <= cycles; | |
935 | adj_len <= ld_ptr ? (adj_len - cyc_len) : adj_len; | |
936 | adj_payld_len <= (multicycle & next_rcd_enq) | |
937 | ? (adj_payld_len - cyc_len) | |
938 | : adj_payld_len; | |
939 | new_payld_dwbe <= (multicycle & next_rcd_enq) | |
940 | ? ((payld_offset != 0) ? 8'hff | |
941 | : {lastdwbe, 4'hf}) | |
942 | : new_payld_dwbe; | |
943 | ||
944 | rem_payld_len <= get_rem_payld(temp_payld_len,y2k_mps); | |
945 | lastdwbe <= lastdwbe; | |
946 | end | |
947 | default : begin | |
948 | multicycle <= 0; | |
949 | cycles <= 6'h01; | |
950 | adj_len <= 0; | |
951 | adj_payld_len <= 0; | |
952 | new_payld_dwbe <= 0; | |
953 | rem_payld_len <= 0; | |
954 | lastdwbe <= 0; | |
955 | end | |
956 | endcase // case(bld_state) | |
957 | end // else: !if(rst_l == 1'b0) | |
958 | end // always @ (posedge clk) | |
959 | ||
960 | always @(posedge clk) | |
961 | begin | |
962 | if (rst_l == 1'b0) begin | |
963 | clastyp <= 0; | |
964 | end | |
965 | else begin | |
966 | case (next_deq_pipe) // synopsys parallel_case | |
967 | 1'b1 : clastyp <= pipe_clastyp; | |
968 | 1'b0 : clastyp <= clastyp; | |
969 | endcase // case(next_deq_pipe) | |
970 | end | |
971 | end // always @ (posedge clk) | |
972 | ||
973 | // Pipelined computed values for the next multi-command | |
974 | // build for a given schedule record. | |
975 | ||
976 | always @(posedge clk) | |
977 | begin | |
978 | if (rst_l == 1'b0) begin | |
979 | cyc_typ <= 0; | |
980 | cyc_len <= 0; | |
981 | cyc_bytcnt <= 0; | |
982 | cyc_addr <= 0; | |
983 | cyc_addrerr <= 0; | |
984 | cyc_dptr <= 0; | |
985 | cyc_cntxtnum <= 0; | |
986 | cyc_seqnum <= 0; | |
987 | cyc_trtag <= 0; | |
988 | end // if (rst_l == 1'b0) | |
989 | else begin | |
990 | case (next_deq_pipe) // synopsys full_case parallel_case | |
991 | 1'b1 : begin | |
992 | case (pipe_clastyp) // synopsys parallel_case | |
993 | CLASWR: begin // DMA Wr | |
994 | cyc_typ <= pipe_typ; | |
995 | cyc_len <= pipe_len; | |
996 | cyc_bytcnt <= pipe_bytcnt; | |
997 | cyc_addr <= pipe_addr; | |
998 | cyc_addrerr <= pipe_addrerr; | |
999 | cyc_dptr <= pipe_dptr; | |
1000 | cyc_cntxtnum <= pipe_cntxtnum; | |
1001 | cyc_seqnum <= pipe_seqnum; | |
1002 | cyc_trtag <= pipe_trtag; | |
1003 | end // case: CLASWR | |
1004 | ||
1005 | CLASRD: begin // DMA Rd | |
1006 | cyc_typ <= pipe_typ; | |
1007 | cyc_len <= pipe_len; | |
1008 | cyc_addr <= pipe_addr; | |
1009 | cyc_addrerr <= pipe_addrerr; | |
1010 | cyc_dptr <= pipe_dptr; | |
1011 | cyc_bytcnt <= byt_cnt(pipe_len, pipe_dwbe); | |
1012 | cyc_cntxtnum <= ctx2rcm_nxctx_addr; | |
1013 | cyc_seqnum <= pipe_seqnum; | |
1014 | cyc_trtag <= pipe_trtag; | |
1015 | end // case: CLASRD | |
1016 | ||
1017 | default: begin | |
1018 | cyc_typ <= pipe_typ; | |
1019 | cyc_len <= pipe_len; | |
1020 | cyc_bytcnt <= pipe_bytcnt; | |
1021 | cyc_addr <= pipe_addr; | |
1022 | cyc_addrerr <= pipe_addrerr; | |
1023 | cyc_dptr <= pipe_dptr; | |
1024 | cyc_cntxtnum <= pipe_cntxtnum; | |
1025 | cyc_seqnum <= pipe_seqnum; | |
1026 | cyc_trtag <= pipe_trtag; | |
1027 | end // case: default | |
1028 | endcase // case(clastyp) | |
1029 | end // case: 1'b1 | |
1030 | 1'b0 : begin | |
1031 | case (clastyp) // synopsys parallel_case | |
1032 | CLASWR: begin // DMA Wr | |
1033 | cyc_typ <= cyc_typ; | |
1034 | cyc_len <= ld_ptr ? temp_len : cyc_len; | |
1035 | cyc_bytcnt <= (multicycle & next_rcd_enq) | |
1036 | ? ({4'h0,lastdwbe,4'hf}) | |
1037 | : cyc_bytcnt; | |
1038 | cyc_addr <= (ld_ptr ? {cyc_addr[SRADDRMSB :10],lo_addr} | |
1039 | : cyc_addr); | |
1040 | cyc_addrerr <= cyc_addrerr; | |
1041 | cyc_dptr <= cyc_dptr; | |
1042 | cyc_cntxtnum <= cyc_cntxtnum; | |
1043 | cyc_seqnum <= (ld_ptr ? (cyc_seqnum + 1'b1) : cyc_seqnum); | |
1044 | cyc_trtag <= next_deq_pipe ? pipe_trtag : cyc_trtag; | |
1045 | end // case: CLASWR | |
1046 | ||
1047 | CLASRD: begin // DMA Rd | |
1048 | cyc_typ <= cyc_typ; | |
1049 | cyc_len <= ((multicycle & next_rcd_enq) ? sel_payld_len | |
1050 | : cyc_len); | |
1051 | cyc_addr <= ((multicycle & next_rcd_enq) | |
1052 | ? {cyc_addr[SRADDRMSB :10],payld_lo_addr} | |
1053 | : cyc_addr); | |
1054 | cyc_addrerr <= cyc_addrerr; | |
1055 | cyc_dptr <= cyc_dptr; | |
1056 | cyc_bytcnt <= cyc_bytcnt; | |
1057 | ||
1058 | cyc_cntxtnum <= cyc_cntxtnum; | |
1059 | cyc_seqnum <= (cm2pm_rcd_enq ? (cyc_seqnum + 1'b1) : cyc_seqnum); | |
1060 | cyc_trtag <= cyc_trtag; | |
1061 | end // case: CLASRD | |
1062 | ||
1063 | default: begin | |
1064 | cyc_typ <= cyc_typ; | |
1065 | cyc_len <= cyc_len; | |
1066 | cyc_bytcnt <= cyc_bytcnt; | |
1067 | cyc_addr <= cyc_addr; | |
1068 | cyc_addrerr <= cyc_addrerr; | |
1069 | cyc_dptr <= cyc_dptr; | |
1070 | cyc_cntxtnum <= cyc_cntxtnum; | |
1071 | cyc_seqnum <= cyc_seqnum; | |
1072 | cyc_trtag <= cyc_trtag; | |
1073 | end // case: default | |
1074 | endcase // case(clastyp) | |
1075 | end // case: 1'b0 | |
1076 | ||
1077 | default: begin | |
1078 | cyc_typ <= cyc_typ; | |
1079 | cyc_len <= cyc_len; | |
1080 | cyc_bytcnt <= cyc_bytcnt; | |
1081 | cyc_addr <= cyc_addr; | |
1082 | cyc_addrerr <= cyc_addrerr; | |
1083 | cyc_dptr <= cyc_dptr; | |
1084 | cyc_cntxtnum <= cyc_cntxtnum; | |
1085 | cyc_seqnum <= cyc_seqnum; | |
1086 | cyc_trtag <= cyc_trtag; | |
1087 | end // case: default | |
1088 | endcase // case(next_deq_pipe) | |
1089 | end // else: !if(rst_l == 1'b0) | |
1090 | end // always @ (posedge clk) | |
1091 | ||
1092 | // number of packet commands (cycles) issued in multicycle cases | |
1093 | always @(posedge clk) | |
1094 | begin | |
1095 | if (rst_l == 1'b0) begin | |
1096 | num_cmd <= 6'b000001; // command counter | |
1097 | end | |
1098 | else begin | |
1099 | num_cmd <= next_deq_pipe ? pipe_cycles : (ld_ptr ? (num_cmd - 6'b000001) : num_cmd); | |
1100 | end // else: !if(rst_l == 1'b0) | |
1101 | end // always @ (posedge clk) | |
1102 | ||
1103 | // DEQ next state | |
1104 | always @(deq_state or srmpty or pipe_full or pm2cm_rcd_full) | |
1105 | begin | |
1106 | case (deq_state) // synopsys parallel_case | |
1107 | DEQIDLE : begin | |
1108 | case(srmpty) // synopsys full_case parallel_case | |
1109 | 1'b1: deq_next = DEQIDLE; | |
1110 | 1'b0: deq_next = DEQPIPE; | |
1111 | endcase // case(pkmpty) | |
1112 | end // case: DEQIDLE | |
1113 | ||
1114 | DEQPIPE : begin | |
1115 | case (pipe_full | pm2cm_rcd_full) // synopsys full_case parallel_case | |
1116 | 1'b1 : deq_next = DEQPIPE; | |
1117 | 1'b0 : deq_next = DEQ; | |
1118 | endcase // case(pipe_full | pm2cm_rcd_full) | |
1119 | end | |
1120 | ||
1121 | DEQ : begin | |
1122 | deq_next = DEQIDLE; | |
1123 | end // case: DEQ | |
1124 | ||
1125 | default : deq_next = DEQIDLE; | |
1126 | ||
1127 | endcase // case(deq_state) | |
1128 | end // always @ (deq_state or srmpty or pipe_full) | |
1129 | ||
1130 | // DEQ state machine outputs | |
1131 | always @(deq_state or srmpty or pipe_full or pm2cm_rcd_full) | |
1132 | begin | |
1133 | case (deq_state) // synopsys parallel_case | |
1134 | DEQIDLE : begin | |
1135 | ld_pipe = 1'b0; | |
1136 | next_deq_sr = 1'b0; | |
1137 | end // case: DEQIDLE | |
1138 | ||
1139 | DEQPIPE : begin | |
1140 | next_deq_sr = 1'b0; | |
1141 | case (pipe_full | pm2cm_rcd_full) // synopsys full_case parallel_case | |
1142 | 1'b1 : ld_pipe = 1'b0; | |
1143 | 1'b0 : ld_pipe = 1'b1; | |
1144 | endcase // case(pipe_full | pm2cm_rcd_full) | |
1145 | end | |
1146 | ||
1147 | DEQ : begin | |
1148 | ld_pipe = 1'b0; | |
1149 | case (srmpty) // synopsys full_case parallel_case | |
1150 | 1'b1 : next_deq_sr = 1'b0; | |
1151 | 1'b0 : next_deq_sr = 1'b1; | |
1152 | endcase // case(srmpty) | |
1153 | end | |
1154 | ||
1155 | default : begin | |
1156 | ld_pipe = 1'b0; | |
1157 | next_deq_sr = 1'b0; | |
1158 | end | |
1159 | endcase // case(deq_state) | |
1160 | end // always @ (deq_state or srmpty or pipe_full) | |
1161 | ||
1162 | // DEQ state transitions | |
1163 | always @(posedge clk) | |
1164 | begin | |
1165 | if (rst_l == 1'b0) | |
1166 | deq_state <= DEQIDLE; // Synchronous Reset | |
1167 | else begin | |
1168 | deq_state <= deq_next; | |
1169 | end | |
1170 | end | |
1171 | ||
1172 | // *************** Build Context Procedures (build_cntx)*********/ | |
1173 | ||
1174 | // Context Number Request State machine | |
1175 | always @(ctx_state or ctx2rcm_ctx_gnt or next_gen_ctx) | |
1176 | begin | |
1177 | next_ctx_req = 1'b0; | |
1178 | ctx_next = ctx_state; | |
1179 | ||
1180 | case (ctx_state) // synopsys parallel_case | |
1181 | CTXIDLE : begin | |
1182 | case (next_gen_ctx) // synopsys full_case parallel_case | |
1183 | 1'b0: begin | |
1184 | next_ctx_req = 1'b0; | |
1185 | ctx_next = CTXIDLE; | |
1186 | end | |
1187 | 1'b1: begin | |
1188 | next_ctx_req = 1'b1; | |
1189 | ctx_next = CTXGNT; | |
1190 | end | |
1191 | endcase // case(next_gen_ctx) | |
1192 | end // case: CTXIDLE | |
1193 | ||
1194 | CTXGNT : begin | |
1195 | case (ctx2rcm_ctx_gnt) // synopsys full_case parallel_case | |
1196 | 1'b0: begin | |
1197 | next_ctx_req = 1'b1; | |
1198 | ctx_next = CTXGNT; | |
1199 | end | |
1200 | 1'b1: begin | |
1201 | next_ctx_req = 1'b0; | |
1202 | ctx_next = CTXIDLE; | |
1203 | end | |
1204 | endcase // case(ctx2rcm_ctx_gnt) | |
1205 | end // case: CTXGNT | |
1206 | ||
1207 | default : begin // to satisfy vlint | |
1208 | next_ctx_req = 1'b0; | |
1209 | ctx_next = CTXIDLE; | |
1210 | end | |
1211 | endcase // case(ctx_state) | |
1212 | end // always @ (ctx_state or ctx2rcm_ctx_gnt or next_gen_ctx) | |
1213 | ||
1214 | ||
1215 | // CTX state transitions | |
1216 | always @(posedge clk) | |
1217 | begin | |
1218 | if (rst_l == 1'b0) | |
1219 | ctx_state <= CTXIDLE; // Synchronous Reset | |
1220 | else begin | |
1221 | ctx_state <= ctx_next; | |
1222 | end | |
1223 | end | |
1224 | ||
1225 | ||
1226 | // Packet Sequence Address Request State machine | |
1227 | // SEQ next state | |
1228 | always @(seq_state or ctx2rcm_seq_gnt or next_gen_pkt or pm2cm_rcd_full) | |
1229 | begin | |
1230 | seq_next = seq_state; | |
1231 | ||
1232 | case (seq_state) // synopsys parallel_case | |
1233 | SEQIDLE : begin | |
1234 | case (next_gen_pkt) // synopsys full_case parallel_case | |
1235 | 1'b0: seq_next = SEQIDLE; | |
1236 | 1'b1: seq_next = SEQGNT; | |
1237 | endcase // case(next_gen_pkt) | |
1238 | end // case: SEQIDLE | |
1239 | ||
1240 | SEQGNT : begin | |
1241 | case ({ctx2rcm_seq_gnt, pm2cm_rcd_full}) // synopsys parallel_case | |
1242 | 2'b00, | |
1243 | 2'b01: seq_next = SEQGNT; | |
1244 | 2'b11: seq_next = SEQWAIT; | |
1245 | 2'b10: seq_next = SEQIDLE; | |
1246 | endcase // case({ctx2rcm_seq_gnt, next_gen_pkt}) | |
1247 | end // case: SEQGNT | |
1248 | ||
1249 | SEQWAIT : begin | |
1250 | case(pm2cm_rcd_full) // synopsys parallel_case | |
1251 | 1'b0: seq_next = SEQIDLE; | |
1252 | 1'b1: seq_next = SEQWAIT; | |
1253 | endcase // case(next_gen_pkt) | |
1254 | end | |
1255 | ||
1256 | default : begin // to satisfy vlint | |
1257 | seq_next = SEQIDLE; | |
1258 | end | |
1259 | endcase // case(seq_state) | |
1260 | end // always @ (seq_state or ctx2rcm_seq_gnt or next_gen_pkt) | |
1261 | ||
1262 | // SEQ outputs | |
1263 | always @(seq_state or ctx2rcm_seq_gnt or next_gen_pkt or pm2cm_rcd_full) | |
1264 | begin | |
1265 | xfr_strt = 1'b0; | |
1266 | next_pkseq_req = 1'b0; | |
1267 | ||
1268 | case (seq_state) // synopsys parallel_case | |
1269 | SEQIDLE : begin | |
1270 | case (next_gen_pkt) // synopsys full_case parallel_case | |
1271 | 1'b0: begin | |
1272 | xfr_strt = 1'b0; | |
1273 | next_pkseq_req = 1'b0; | |
1274 | end | |
1275 | 1'b1: begin | |
1276 | xfr_strt = 1'b0; | |
1277 | next_pkseq_req = 1'b1; | |
1278 | end | |
1279 | endcase // case(next_gen_pkt) | |
1280 | end // case: SEQIDLE | |
1281 | ||
1282 | SEQGNT : begin | |
1283 | case ({ctx2rcm_seq_gnt, pm2cm_rcd_full}) // synopsys parallel_case | |
1284 | 2'b00, | |
1285 | 2'b01: begin | |
1286 | xfr_strt = 1'b0; | |
1287 | next_pkseq_req = 1'b1; | |
1288 | end | |
1289 | 2'b11: begin | |
1290 | xfr_strt = 1'b0; | |
1291 | next_pkseq_req = 1'b0; | |
1292 | end | |
1293 | 2'b10 : begin | |
1294 | xfr_strt = 1'b1; | |
1295 | next_pkseq_req = 1'b0; | |
1296 | end | |
1297 | endcase // case({ctx2rcm_seq_gnt, next_gen_pkt}) | |
1298 | end // case: SEQGNT | |
1299 | ||
1300 | SEQWAIT : begin | |
1301 | case(pm2cm_rcd_full) | |
1302 | 1'b0: begin | |
1303 | xfr_strt = 1'b1; | |
1304 | next_pkseq_req = 1'b0; | |
1305 | end | |
1306 | ||
1307 | 1'b1: begin | |
1308 | xfr_strt = 1'b0; | |
1309 | next_pkseq_req = 1'b0; | |
1310 | end | |
1311 | endcase // case(next_gen_pkt) | |
1312 | end | |
1313 | ||
1314 | default : begin // to satisfy vlint | |
1315 | xfr_strt = 1'b0; | |
1316 | next_pkseq_req = 1'b0; | |
1317 | end | |
1318 | endcase // case(seq_state) | |
1319 | end // always @ (seq_state or ctx2rcm_seq_gnt or next_gen_pkt) | |
1320 | ||
1321 | ||
1322 | // SEQ state transitions | |
1323 | always @(posedge clk) | |
1324 | begin | |
1325 | if (rst_l == 1'b0) | |
1326 | seq_state <= SEQIDLE; // Synchronous Reset | |
1327 | else begin | |
1328 | seq_state <= seq_next; | |
1329 | end | |
1330 | end | |
1331 | ||
1332 | // Save inital PSEQ address to post in Context | |
1333 | always @(posedge clk) | |
1334 | begin | |
1335 | if (rst_l == 1'b0) begin | |
1336 | first_ctx_gnt <= 0; | |
1337 | end | |
1338 | else begin | |
1339 | first_ctx_gnt <= ctx2rcm_ctx_gnt | |
1340 | ? 1'b1 : (~rcm2ctx_ctx_rw & first_ctx_gnt); | |
1341 | end | |
1342 | end // always @ (posedge clk) | |
1343 | ||
1344 | ||
1345 | // Schedule Record dequeue and Transfer State machine | |
1346 | // BLD next state | |
1347 | always @(bld_state or pipe_mpty or pm2cm_rcd_full or clastyp or multicycle | |
1348 | or pipe_clastyp or num_cmd or xfr_strt) | |
1349 | begin | |
1350 | case (bld_state) // synopsys parallel_case | |
1351 | BLDIDLE : begin | |
1352 | case (pipe_mpty) // synopsys parallel_case | |
1353 | 1'b1 : bld_next = BLDIDLE; | |
1354 | 1'b0 : begin | |
1355 | case (pipe_clastyp) // synopsys parallel_case | |
1356 | CLASRD : bld_next = BLDCNTX; | |
1357 | CLASWR, | |
1358 | CLASPIO, | |
1359 | CLASMSI, | |
1360 | CLASMSC, | |
1361 | CLASMDO : bld_next = BLDBPAS; | |
1362 | default : bld_next = BLDIDLE; | |
1363 | endcase // case(pipe_clastyp) | |
1364 | end | |
1365 | endcase // case(pipe_mpty) | |
1366 | end // case: BLDDEQ | |
1367 | ||
1368 | BLDCNTX : begin | |
1369 | case(pm2cm_rcd_full) // synopsys full_case parallel_case | |
1370 | 1'b0 : begin | |
1371 | case ({multicycle,xfr_strt}) // synopsys full_case parallel_case | |
1372 | 2'b00 : bld_next = BLDCNTX; | |
1373 | 2'b01 : bld_next = BLDIDLE; | |
1374 | 2'b10 : bld_next = BLDCNTX; | |
1375 | 2'b11 : begin | |
1376 | if(num_cmd == 6'h01) bld_next = BLDIDLE; | |
1377 | else bld_next = BLDCNTX; | |
1378 | end | |
1379 | endcase // case({multicycle,xfr_strt}) | |
1380 | end // case: 1'b0 | |
1381 | ||
1382 | 1'b1 : bld_next = BLDCNTX; | |
1383 | endcase // case(pm2cm_rcd_full) | |
1384 | end // case: BLDCNTX | |
1385 | ||
1386 | BLDBPAS : begin | |
1387 | case(pm2cm_rcd_full) // synopsys full_case parallel_case | |
1388 | 1'b1 : bld_next = BLDBPAS; | |
1389 | 1'b0 : begin | |
1390 | case({multicycle, clastyp}) // synopsys parallel_case | |
1391 | {1'b1,CLASWR} : begin | |
1392 | if (num_cmd == 6'h01) bld_next = BLDIDLE; | |
1393 | else bld_next = BLDBPAS; | |
1394 | end | |
1395 | {1'b1,CLASRD}, | |
1396 | {1'b1,CLASMSI}, | |
1397 | {1'b1,CLASMDO}, | |
1398 | {1'b1,CLASMSC} : bld_next = BLDIDLE; | |
1399 | ||
1400 | {1'b0,CLASWR}, | |
1401 | {1'b0,CLASPIO}, | |
1402 | {1'b0,CLASMSI}, | |
1403 | {1'b0,CLASMDO}, | |
1404 | {1'b0,CLASMSC} : bld_next = BLDIDLE; | |
1405 | ||
1406 | default : bld_next = BLDIDLE; | |
1407 | endcase // case({multicycle, clastyp}) | |
1408 | end // case: 1'b0 | |
1409 | endcase // case(pm2cm_rcd_full) | |
1410 | end // case: BLDBPAS | |
1411 | ||
1412 | default: bld_next = BLDIDLE; | |
1413 | ||
1414 | endcase // case(bld_state) | |
1415 | end // always @ (bld_state or pipe_mpty or pm2cm_rcd_full or clastyp or multicycle... | |
1416 | ||
1417 | ||
1418 | // BLD state machine outputs | |
1419 | always @(bld_state or pipe_mpty or pm2cm_rcd_full or clastyp or multicycle | |
1420 | or pipe_clastyp or num_cmd or xfr_strt) | |
1421 | begin | |
1422 | ||
1423 | // next_deq_pipe = signal to dequeue next packet from pipeline | |
1424 | // next_rcd_enq = signal to enqueue packet record to output queue | |
1425 | // next_gen_ctx = signal to strt context operations | |
1426 | // next_gen_pkt = signal to enqueue packet to output queue | |
1427 | // ld_ptr = signal loads new packet values for multicycles | |
1428 | ||
1429 | case (bld_state) // synopsys parallel_case | |
1430 | BLDIDLE : begin | |
1431 | next_rcd_enq = 1'b0; | |
1432 | ld_ptr = 1'b0; | |
1433 | case (pipe_mpty) // synopsys full_case parallel_case | |
1434 | 1'b1 : begin | |
1435 | next_deq_pipe = 1'b0; | |
1436 | next_gen_ctx = 1'b0; | |
1437 | next_gen_pkt = 1'b0; | |
1438 | end | |
1439 | 1'b0 : begin | |
1440 | case (pipe_clastyp) // synopsys parallel_case | |
1441 | CLASRD : begin | |
1442 | next_deq_pipe = 1'b1; | |
1443 | next_gen_ctx = 1'b1; | |
1444 | next_gen_pkt = 1'b1; | |
1445 | end | |
1446 | ||
1447 | CLASWR, | |
1448 | CLASPIO, | |
1449 | CLASMSI, | |
1450 | CLASMSC, | |
1451 | CLASMDO : begin | |
1452 | next_deq_pipe = 1'b1; | |
1453 | next_gen_ctx = 1'b0; | |
1454 | next_gen_pkt = 1'b0; | |
1455 | end // case: CLASWR,... | |
1456 | ||
1457 | default : begin | |
1458 | next_deq_pipe = 1'b0; | |
1459 | next_gen_ctx = 1'b0; | |
1460 | next_gen_pkt = 1'b0; | |
1461 | end | |
1462 | endcase // case(pipe_clastyp) | |
1463 | end // case: 1'b0 | |
1464 | endcase // case(pipe_mpty) | |
1465 | end // case: BLDDEQ | |
1466 | ||
1467 | BLDCNTX : begin | |
1468 | next_deq_pipe = 1'b0; | |
1469 | next_gen_ctx = 1'b0; | |
1470 | ||
1471 | case(pm2cm_rcd_full) // synopsys full_case parallel_case | |
1472 | 1'b0 : begin | |
1473 | case ({multicycle,xfr_strt}) // synopsys full_case parallel_case | |
1474 | 2'b00 : begin | |
1475 | next_rcd_enq = 1'b0; | |
1476 | next_gen_pkt = 1'b0; | |
1477 | ld_ptr = 1'b0; | |
1478 | end | |
1479 | 2'b01 : begin | |
1480 | next_rcd_enq = 1'b1; | |
1481 | next_gen_pkt = 1'b0; | |
1482 | ld_ptr = 1'b0; | |
1483 | end | |
1484 | 2'b10 : begin | |
1485 | next_rcd_enq = 1'b0; | |
1486 | next_gen_pkt = 1'b1; | |
1487 | ld_ptr = 1'b0; | |
1488 | end | |
1489 | 2'b11 : begin | |
1490 | if(num_cmd == 6'h01) begin | |
1491 | next_rcd_enq = 1'b1; | |
1492 | next_gen_pkt = 1'b0; | |
1493 | ld_ptr = 1'b1; | |
1494 | end | |
1495 | else begin | |
1496 | next_rcd_enq = 1'b1; | |
1497 | next_gen_pkt = 1'b1; | |
1498 | ld_ptr = 1'b1; | |
1499 | end // else: !if(num_cmd == 5'h01) | |
1500 | end // case: 2'b11 | |
1501 | endcase // case({multicycle,xfr_strt}) | |
1502 | end // case: 1'b0 | |
1503 | ||
1504 | 1'b1 : begin | |
1505 | next_rcd_enq = 1'b0; | |
1506 | next_gen_pkt = 1'b0; | |
1507 | ld_ptr = 1'b0; | |
1508 | end // case: 1'b1 | |
1509 | endcase // case(pm2cm_rcd_full) | |
1510 | end // case: BLDCNTX | |
1511 | ||
1512 | BLDBPAS : begin | |
1513 | next_deq_pipe = 1'b0; | |
1514 | next_gen_ctx = 1'b0; | |
1515 | next_gen_pkt = 1'b0; | |
1516 | case(pm2cm_rcd_full) // synopsys full_case parallel_case | |
1517 | 1'b0 : begin | |
1518 | case({multicycle, clastyp}) // synopsys parallel_case | |
1519 | {1'b1,CLASWR} : begin | |
1520 | next_rcd_enq = 1'b1; | |
1521 | ld_ptr = 1'b1; | |
1522 | end | |
1523 | ||
1524 | {1'b1,CLASRD}, | |
1525 | {1'b1,CLASMSI}, | |
1526 | {1'b1,CLASMDO}, | |
1527 | {1'b1,CLASMSC} : begin | |
1528 | next_rcd_enq = 1'b0; | |
1529 | ld_ptr = 1'b0; | |
1530 | end // case: {1'b1,CLASRD},... | |
1531 | ||
1532 | ||
1533 | {1'b0,CLASWR}, | |
1534 | {1'b0,CLASMSI}, | |
1535 | {1'b0,CLASMDO}, | |
1536 | {1'b0,CLASMSC} : begin | |
1537 | next_rcd_enq = 1'b1; | |
1538 | ld_ptr = 1'b0; | |
1539 | end // case: {1'b0,CLASWR},... | |
1540 | ||
1541 | default : begin | |
1542 | next_rcd_enq = 1'b1; | |
1543 | ld_ptr = 1'b1; | |
1544 | end | |
1545 | endcase // case({multicycle, clastyp}) | |
1546 | end // case: 1'b0 | |
1547 | ||
1548 | 1'b1 : begin | |
1549 | next_rcd_enq = 1'b0; | |
1550 | ld_ptr = 1'b0; | |
1551 | ||
1552 | end // case: 1'b1 | |
1553 | endcase // case(pm2cm_rcd_full) | |
1554 | end // case: BLDBPAS | |
1555 | ||
1556 | default: begin | |
1557 | next_deq_pipe = 1'b0; | |
1558 | next_rcd_enq = 1'b0; | |
1559 | next_gen_ctx = 1'b0; | |
1560 | next_gen_pkt = 1'b0; | |
1561 | ld_ptr = 1'b0; | |
1562 | end | |
1563 | ||
1564 | endcase // case(bld_state) | |
1565 | end // always @ (bld_state or pipe_mpty or pm2cm_rcd_full or clastyp or multicycle... | |
1566 | ||
1567 | // BLD state transitions | |
1568 | always @(posedge clk) | |
1569 | begin | |
1570 | if (rst_l == 1'b0) | |
1571 | bld_state <= BLDIDLE; // Synchronous Reset | |
1572 | else begin | |
1573 | bld_state <= bld_next; | |
1574 | end | |
1575 | end | |
1576 | ||
1577 | ||
1578 | //************************************************ | |
1579 | // MODULES | |
1580 | //************************************************ | |
1581 | ||
1582 | dmu_cmu_rcm_schrcd_q rcm_queue ( | |
1583 | .clk (clk), | |
1584 | .rst_l (rst_l), | |
1585 | .enq (mm2cm_rcd_enq), | |
1586 | .rcd_in (mm2cm_rcd), | |
1587 | .deq (next_deq_sr), | |
1588 | .typ (srtyp), | |
1589 | .len(srlen), | |
1590 | .dwbe (srdwbe), | |
1591 | .addr(sraddr), | |
1592 | .addr_err(sraddrerr), | |
1593 | .dptr(srdptr), | |
1594 | .sbd_tag(srtr_tag), | |
1595 | .full (cm2mm_rcd_full), | |
1596 | .empty (srmpty), | |
1597 | .overflow(), // .overflow(overflow), //for debug use | |
1598 | .underflow() // .underflow(underflow) //for debug use | |
1599 | ); | |
1600 | ||
1601 | // ********************** signal registers *************************/ | |
1602 | ||
1603 | always @(posedge clk) | |
1604 | begin | |
1605 | if (rst_l == 1'b0) begin | |
1606 | deq_pipe <= 0; | |
1607 | cm2pm_rcd_enq <= 0; | |
1608 | ||
1609 | rcm2ctx_ctx_req <= 0; | |
1610 | rcm2ctx_ctx_addr <= 0; | |
1611 | rcm2ctx_ctx_rw <= 0; | |
1612 | ||
1613 | rcm2ctx_seq_req <= 0; | |
1614 | rcm2ctx_pkseq_addr <= 0; | |
1615 | rcm2ctx_pkseq_rw <= 0; | |
1616 | ||
1617 | cur_ctx <= 0; | |
1618 | rcm2ctx_ctx <= 0; | |
1619 | ||
1620 | pipe_full <= 0; | |
1621 | ||
1622 | end | |
1623 | else begin | |
1624 | deq_pipe <= next_deq_pipe; | |
1625 | ||
1626 | cm2pm_rcd_enq <= next_rcd_enq; | |
1627 | ||
1628 | rcm2ctx_ctx_req <= next_ctx_req; | |
1629 | rcm2ctx_ctx_addr <= ctx2rcm_ctx_gnt ? ctx2rcm_nxctx_addr : rcm2ctx_ctx_addr; | |
1630 | rcm2ctx_ctx_rw <= ((clastyp == CLASRD) && first_ctx_gnt) | |
1631 | ? cm2pm_rcd_enq : 1'b0; | |
1632 | rcm2ctx_seq_req <= next_pkseq_req; | |
1633 | rcm2ctx_pkseq_addr <= ctx2rcm_seq_gnt ? ctx2rcm_nxseq_addr | |
1634 | : rcm2ctx_pkseq_addr; | |
1635 | rcm2ctx_pkseq_rw <= (clastyp == CLASRD) ? next_rcd_enq : 1'b0; | |
1636 | ||
1637 | cur_ctx <= ctx2rcm_ctx_gnt ? ctx2rcm_cur_ctx : cur_ctx; | |
1638 | ||
1639 | rcm2ctx_ctx <= (first_ctx_gnt & cm2pm_rcd_enq) | |
1640 | ? ({ // Context entry | |
1641 | cycles[CLTOTMSB :0], | |
1642 | rcm2ctx_pkseq_addr[PSEQADDRMSB :0], | |
1643 | pkt_addr_err, | |
1644 | new_order_bits[ORDERBITMSB :0] | |
1645 | }) | |
1646 | : {(CTXARRAYMSB + 1){1'b0}}; | |
1647 | ||
1648 | pipe_full <= ld_pipe ? 1'b1 : (~deq_pipe & pipe_full); | |
1649 | ||
1650 | end // else: !if(rst_l == 1'b0) | |
1651 | end // always @ (posedge clk) | |
1652 | ||
1653 | // ---------------------------------------------------------------------------- | |
1654 | // Debug | |
1655 | // ---------------------------------------------------------------------------- | |
1656 | ||
1657 | always @ (dbg2rcm_dbg_sel_a or dbg2rcm_dbg_sel_b) | |
1658 | begin | |
1659 | dbg_sel[0] = dbg2rcm_dbg_sel_a; | |
1660 | dbg_sel[1] = dbg2rcm_dbg_sel_b; | |
1661 | end | |
1662 | ||
1663 | always @ (dbg_sel[0] or dbg_sel[1] or next_cycles or next_clastyp or | |
1664 | pipe_cycles or pipe_clastyp or xfr_strt or pipe_mcycle or | |
1665 | clastyp or bld_state or srmpty or next_deq_sr or ld_pipe or | |
1666 | pipe_full or deq_state or ld_ptr or pipe_mpty or next_deq_pipe or | |
1667 | next_gen_ctx or next_gen_pkt or pm2cm_rcd_full or multicycle or | |
1668 | ctx2rcm_ctx_gnt or next_ctx_req or rcm_is_idle or | |
1669 | y2k_mps or ctx_state or next_pkseq_req or | |
1670 | ctx2rcm_seq_gnt or seq_state | |
1671 | ) | |
1672 | begin | |
1673 | for (i = 0; i < 2; i = i + 1) begin | |
1674 | case (dbg_sel[i]) // synopsys infer_mux | |
1675 | 3'b000: nxt_dbg_bus[i] = {next_cycles[CLTOTMSB -1 :0],next_clastyp}; | |
1676 | 3'b001: nxt_dbg_bus[i] = {pipe_cycles[CLTOTMSB -1 :0],pipe_clastyp}; | |
1677 | 3'b010: nxt_dbg_bus[i] = {xfr_strt,pipe_mcycle,clastyp,bld_state}; | |
1678 | 3'b011: nxt_dbg_bus[i] = {1'b0,rcm_is_idle,srmpty,next_deq_sr,ld_pipe,pipe_full,deq_state}; | |
1679 | 3'b100: nxt_dbg_bus[i] = {ld_ptr,pipe_mpty,next_deq_pipe,next_gen_ctx,next_gen_pkt,pipe_clastyp}; | |
1680 | 3'b101: nxt_dbg_bus[i] = {pm2cm_rcd_full,multicycle,clastyp,bld_state}; | |
1681 | 3'b110: nxt_dbg_bus[i] = {xfr_strt,ctx2rcm_ctx_gnt,next_ctx_req,y2k_mps,ctx_state}; | |
1682 | 3'b111: nxt_dbg_bus[i] = {3'b000,next_gen_pkt,next_pkseq_req,ctx2rcm_seq_gnt,seq_state}; | |
1683 | endcase // case(dbg_sel[i]) | |
1684 | end // for (i = 0; i < 2; i = i + 1) | |
1685 | end // always @ (dbg_sel[0] or dbg_sel[1] or... | |
1686 | ||
1687 | // ********************** Output Procedures ***********************/ | |
1688 | ||
1689 | // Debug | |
1690 | always @ (posedge clk) begin | |
1691 | if(rst_l == 1'b0) begin | |
1692 | for (k = 0; k < 2; k = k + 1) begin | |
1693 | dbg_bus[k] <= 8'h00; | |
1694 | end | |
1695 | end | |
1696 | else begin | |
1697 | for (k = 0; k < 2; k = k + 1) begin | |
1698 | dbg_bus[k] <= nxt_dbg_bus[k]; | |
1699 | end | |
1700 | end | |
1701 | end // always @ (posedge clk) | |
1702 | ||
1703 | ||
1704 | //Pipeline final output stage for next packet record sequence | |
1705 | ||
1706 | always @(posedge clk) | |
1707 | if(rst_l == 1'b0) begin | |
1708 | pkt_typ <= {PRTYP_WDTH{1'b0}}; | |
1709 | pkt_len <= {PRLEN_WDTH{1'b0}}; | |
1710 | pkt_byt_cnt <= {PRBYTCNT_WDTH{1'b0}}; | |
1711 | pkt_cntxt_num <= {PRCNTXTNUM_WDTH{1'b0}}; | |
1712 | pkt_seq_num <= {PRSEQNUM_WDTH{1'b0}}; | |
1713 | pkt_addr <= {PRADDR_WDTH{1'b0}}; | |
1714 | pkt_addr_err <= {{1'b0}}; | |
1715 | pkt_tr_tag <= {PRSBDTAG_WDTH{1'b0}}; | |
1716 | pkt_dptr <= {PRDPTR_WDTH{1'b0}}; | |
1717 | end | |
1718 | else begin | |
1719 | case ({bld_state,multicycle}) // synopsys parallel_case | |
1720 | ||
1721 | // Single cycle pipeline stage | |
1722 | 4'b0100 : begin // BLDCNTX modify | |
1723 | pkt_typ <= next_rcd_enq ? cyc_typ : pkt_typ; | |
1724 | pkt_len <= next_rcd_enq ? cyc_len[SRLENMSB :0] : pkt_len; | |
1725 | pkt_byt_cnt <= next_rcd_enq ? cyc_bytcnt : pkt_byt_cnt; | |
1726 | pkt_cntxt_num <= next_rcd_enq ? cyc_cntxtnum : pkt_cntxt_num; | |
1727 | pkt_seq_num <= next_rcd_enq ? cyc_seqnum : pkt_seq_num; | |
1728 | pkt_addr <= next_rcd_enq ? cyc_addr : pkt_addr; | |
1729 | pkt_addr_err <= next_rcd_enq ? cyc_addrerr :pkt_addr_err ; | |
1730 | pkt_tr_tag <= next_rcd_enq ? cyc_trtag : pkt_tr_tag; | |
1731 | pkt_dptr <= next_rcd_enq ? cyc_dptr : pkt_dptr; | |
1732 | end // case: 4'b0100 | |
1733 | ||
1734 | 4'b0110 : begin // BLDBPAS | |
1735 | pkt_typ <= next_rcd_enq ? cyc_typ : pkt_typ; | |
1736 | pkt_len <= next_rcd_enq ? cyc_len[SRLENMSB :0] : pkt_len; | |
1737 | pkt_byt_cnt <= next_rcd_enq ? cyc_bytcnt : pkt_byt_cnt; | |
1738 | pkt_cntxt_num <= next_rcd_enq ? cyc_cntxtnum : pkt_cntxt_num; | |
1739 | pkt_seq_num <= next_rcd_enq ? cyc_seqnum : pkt_seq_num; | |
1740 | pkt_addr <= next_rcd_enq ? cyc_addr : pkt_addr; | |
1741 | pkt_addr_err <= next_rcd_enq ? cyc_addrerr :pkt_addr_err ; | |
1742 | pkt_tr_tag <= next_rcd_enq ? cyc_trtag : pkt_tr_tag; | |
1743 | pkt_dptr <= next_rcd_enq ? cyc_dptr : pkt_dptr; | |
1744 | end // case: 4'b0110 | |
1745 | ||
1746 | // multicycle pipeline stages | |
1747 | 4'b0101 : begin // BLDCNTX modify | |
1748 | pkt_typ <= next_rcd_enq ? cyc_typ : pkt_typ; | |
1749 | pkt_len <= next_rcd_enq ? cyc_len[SRLENMSB :0] : pkt_len; | |
1750 | pkt_byt_cnt <= next_rcd_enq ? (num_cmd == 6'h01) | |
1751 | ? ((cyc_len == 11'h001) ? byt_cnt(cyc_len, {lastdwbe, 4'h0}) | |
1752 | : byt_cnt(cyc_len, {lastdwbe,new_payld_dwbe[3:0]})) | |
1753 | : byt_cnt(cyc_len, new_payld_dwbe) | |
1754 | : pkt_byt_cnt; | |
1755 | ||
1756 | pkt_cntxt_num <= next_rcd_enq ? cyc_cntxtnum : pkt_cntxt_num; | |
1757 | pkt_seq_num <= next_rcd_enq ? cyc_seqnum : pkt_seq_num; | |
1758 | pkt_addr <= next_rcd_enq ? cyc_addr : pkt_addr; | |
1759 | pkt_addr_err <= next_rcd_enq ? cyc_addrerr :pkt_addr_err ; | |
1760 | pkt_tr_tag <= next_rcd_enq ? cyc_trtag : pkt_tr_tag; | |
1761 | pkt_dptr <= next_rcd_enq ? cyc_dptr : pkt_dptr; | |
1762 | end // case: 4'b0101 | |
1763 | ||
1764 | 4'b0111 : begin // BLDBPAS modify | |
1765 | pkt_typ <= next_rcd_enq ? cyc_typ : pkt_typ; | |
1766 | pkt_len <= next_rcd_enq ? cyc_len[SRLENMSB :0] : pkt_len; | |
1767 | pkt_byt_cnt <= next_rcd_enq ? cyc_bytcnt : pkt_byt_cnt; | |
1768 | pkt_cntxt_num <= next_rcd_enq ? cyc_cntxtnum : pkt_cntxt_num; | |
1769 | pkt_seq_num <= next_rcd_enq ? cyc_seqnum : pkt_seq_num; | |
1770 | pkt_addr <= next_rcd_enq ? cyc_addr : pkt_addr; | |
1771 | pkt_addr_err <= next_rcd_enq ? cyc_addrerr :pkt_addr_err ; | |
1772 | pkt_tr_tag <= next_rcd_enq ? cyc_trtag : pkt_tr_tag; | |
1773 | pkt_dptr <= next_rcd_enq ? cyc_dptr : pkt_dptr; | |
1774 | end // case: 4'b0111 | |
1775 | ||
1776 | default : begin | |
1777 | pkt_typ <= pkt_typ; | |
1778 | pkt_len <= pkt_len; | |
1779 | pkt_byt_cnt <= pkt_byt_cnt; | |
1780 | pkt_cntxt_num <= pkt_cntxt_num; | |
1781 | pkt_seq_num <= pkt_seq_num; | |
1782 | pkt_addr <= pkt_addr; | |
1783 | pkt_addr_err <= pkt_addr_err; | |
1784 | pkt_tr_tag <= pkt_tr_tag; | |
1785 | pkt_dptr <= pkt_dptr; | |
1786 | end // case: default | |
1787 | endcase // case({bld_state,multicycle}) | |
1788 | end // always @ (posedge clk) | |
1789 | ||
1790 | always @(posedge clk) | |
1791 | begin | |
1792 | if (rst_l == 1'b0) begin | |
1793 | rcm_is_idle <= 1'b1; | |
1794 | end | |
1795 | else begin | |
1796 | rcm_is_idle <= ((srmpty == 1'b1) && (deq_state == DEQIDLE) && | |
1797 | (ctx_state == CTXIDLE) && (seq_state == SEQIDLE) && | |
1798 | (pipe_mpty == 1'b1) && (bld_state == BLDIDLE)) | |
1799 | ? 1'b1 : 1'b0; | |
1800 | end | |
1801 | end | |
1802 | ||
1803 | // ***********************Assignments *****************************/ | |
1804 | ||
1805 | // Signal assignments | |
1806 | assign pipe_mpty = ~pipe_full; | |
1807 | ||
1808 | assign cacheline = 11'h010; | |
1809 | ||
1810 | assign part_len = cacheline - {7'h00, sraddr[3:0]}; //make vlint happy | |
1811 | ||
1812 | assign fourk_bit = ~|srlen[SRLENMSB :0]; | |
1813 | ||
1814 | assign explen = {fourk_bit,srlen[SRLENMSB :0]}; | |
1815 | ||
1816 | assign restof_len = explen - first_len; | |
1817 | ||
1818 | ||
1819 | //DMA Wr's | |
1820 | ||
1821 | assign lo_addr = (cyc_addr[9:0] + cyc_len[SRLENMSB :0]); | |
1822 | ||
1823 | assign temp_len = next_deq_pipe ? (cacheline - {7'h00, pipe_addr[3:0]}) | |
1824 | : (adj_len - cyc_len); | |
1825 | ||
1826 | // DMA Rd's | |
1827 | // allign to bigest payload < maxpayload | |
1828 | ||
1829 | assign first_len = (maxpyld - {7'h00,sraddr[3:0]}); | |
1830 | ||
1831 | assign sel_payld_len = (temp_payld_len > maxpyld) | |
1832 | ? maxpyld | |
1833 | : ((payld_offset == 0) ? rem_payld_len | |
1834 | : {temp_payld_len[10:4], 4'h0}); | |
1835 | assign payld_lo_addr = (cyc_addr[9:0] + cyc_len[9:0]); | |
1836 | ||
1837 | // new temp payload length based on first_len | |
1838 | assign temp_payld_len = next_deq_pipe ? first_len | |
1839 | : (adj_payld_len - cyc_len); | |
1840 | ||
1841 | assign payld_offset = get_payld_offset(temp_payld_len, y2k_mps); | |
1842 | ||
1843 | // Output assignments | |
1844 | ||
1845 | assign rcm2ctx_pkseq = { // PKSEQ entry | |
1846 | 1'b0, | |
1847 | {CLSTADDRMSB +1{1'b0}} //make vlint happy | |
1848 | }; | |
1849 | ||
1850 | assign cm2pm_rcd [IPRMSB :0] = { // Egress Retire Record | |
1851 | pkt_typ[PRTYPMSB :0], | |
1852 | pkt_len[PRLENMSB :0], | |
1853 | pkt_byt_cnt[PRBYTCNTMSB :0], | |
1854 | pkt_cntxt_num[PRCNTXTNUMMSB :0], | |
1855 | pkt_seq_num[PRSEQNUMMSB :0], | |
1856 | pkt_addr[PRADDRMSB :0], | |
1857 | pkt_addr_err, | |
1858 | pkt_dptr[PRDPTRMSB :0], | |
1859 | pkt_tr_tag[PRSBDTAGMSB :0] | |
1860 | }; | |
1861 | // Debug | |
1862 | assign rcm2dbg_dbg_a = dbg_bus[0]; | |
1863 | assign rcm2dbg_dbg_b = dbg_bus[1]; | |
1864 | ||
1865 | endmodule |