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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_cru_addr_decode.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_cru_addr_decode | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | daemon_csrbus_valid, | |
40 | daemon_csrbus_addr, | |
41 | csrbus_src_bus, | |
42 | daemon_csrbus_wr, | |
43 | daemon_csrbus_wr_out, | |
44 | daemon_csrbus_wr_data, | |
45 | daemon_csrbus_wr_data_out, | |
46 | daemon_csrbus_mapped, | |
47 | csrbus_acc_vio, | |
48 | daemon_transaction_in_progress, | |
49 | instance_id, | |
50 | daemon_csrbus_done, | |
51 | dmc_dbg_sel_a_reg_select_pulse, | |
52 | dmc_dbg_sel_b_reg_select_pulse, | |
53 | dmc_pcie_cfg_select_pulse | |
54 | ); | |
55 | ||
56 | //==================================================================== | |
57 | // Polarity declarations | |
58 | //==================================================================== | |
59 | input clk; // Clock signal | |
60 | input rst_l; // Reset | |
61 | input daemon_csrbus_valid; // Daemon_Valid | |
62 | input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
63 | input [1:0] csrbus_src_bus; // Source bus | |
64 | input daemon_csrbus_wr; // Read/Write signal | |
65 | output daemon_csrbus_wr_out; // Read/Write signal | |
66 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
67 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
68 | output daemon_csrbus_mapped; // mapped | |
69 | output csrbus_acc_vio; // acc_vio | |
70 | input daemon_transaction_in_progress; // daemon_transaction_in_progress | |
71 | input instance_id; // Instance ID | |
72 | output daemon_csrbus_done; // Operation is done | |
73 | output dmc_dbg_sel_a_reg_select_pulse; // select signal | |
74 | output dmc_dbg_sel_b_reg_select_pulse; // select signal | |
75 | output dmc_pcie_cfg_select_pulse; // select signal | |
76 | ||
77 | //==================================================================== | |
78 | // Type declarations | |
79 | //==================================================================== | |
80 | wire clk; // Clock signal | |
81 | wire rst_l; // Reset | |
82 | wire daemon_csrbus_valid; // Daemon_Valid | |
83 | wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
84 | wire [1:0] csrbus_src_bus; // Source bus | |
85 | wire daemon_csrbus_wr; // Read/Write signal | |
86 | reg daemon_csrbus_wr_out; // Read/Write signal | |
87 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
88 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
89 | wire daemon_csrbus_mapped; // mapped | |
90 | wire csrbus_acc_vio; // acc_vio | |
91 | wire daemon_transaction_in_progress; // daemon_transaction_in_progress | |
92 | wire instance_id; // Instance ID | |
93 | wire daemon_csrbus_done; // Operation is done | |
94 | reg dmc_dbg_sel_a_reg_select_pulse; // select signal | |
95 | reg dmc_dbg_sel_b_reg_select_pulse; // select signal | |
96 | reg dmc_pcie_cfg_select_pulse; // select signal | |
97 | ||
98 | ||
99 | //==================================================================== | |
100 | // Clocked valid | |
101 | //==================================================================== | |
102 | reg clocked_valid; | |
103 | reg clocked_valid_pulse; | |
104 | always @(posedge clk) | |
105 | begin | |
106 | if(~rst_l) | |
107 | begin | |
108 | clocked_valid <= 1'b0; | |
109 | clocked_valid_pulse <= 1'b0; | |
110 | end | |
111 | else | |
112 | begin | |
113 | clocked_valid <= daemon_csrbus_valid; | |
114 | clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid; | |
115 | end | |
116 | end | |
117 | ||
118 | //==================================================================== | |
119 | // Address Decode | |
120 | //==================================================================== | |
121 | reg dmc_dbg_sel_a_reg_addr_decoded; | |
122 | reg dmc_dbg_sel_b_reg_addr_decoded; | |
123 | reg dmc_pcie_cfg_addr_decoded; | |
124 | ||
125 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) | |
126 | begin | |
127 | if (~daemon_csrbus_valid) | |
128 | begin | |
129 | dmc_dbg_sel_a_reg_addr_decoded = 1'b0; | |
130 | dmc_dbg_sel_b_reg_addr_decoded = 1'b0; | |
131 | dmc_pcie_cfg_addr_decoded = 1'b0; | |
132 | end | |
133 | else | |
134 | case (instance_id) | |
135 | ||
136 | `FIRE_DLC_CRU_INSTANCE_ID_VALUE_A: | |
137 | begin | |
138 | dmc_dbg_sel_a_reg_addr_decoded = | |
139 | daemon_csrbus_addr[26:0] == `FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_HW_ADDR; | |
140 | dmc_dbg_sel_b_reg_addr_decoded = | |
141 | daemon_csrbus_addr[26:0] == `FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_HW_ADDR; | |
142 | dmc_pcie_cfg_addr_decoded = | |
143 | daemon_csrbus_addr[26:0] == `FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_HW_ADDR; | |
144 | end | |
145 | ||
146 | `FIRE_DLC_CRU_INSTANCE_ID_VALUE_B: | |
147 | begin | |
148 | dmc_dbg_sel_a_reg_addr_decoded = | |
149 | daemon_csrbus_addr[26:0] == `FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_A_REG_HW_ADDR; | |
150 | dmc_dbg_sel_b_reg_addr_decoded = | |
151 | daemon_csrbus_addr[26:0] == `FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_B_REG_HW_ADDR; | |
152 | dmc_pcie_cfg_addr_decoded = | |
153 | daemon_csrbus_addr[26:0] == `FIRE_DLC_CRU_CSR_B_DMC_PCIE_CFG_HW_ADDR; | |
154 | end | |
155 | ||
156 | default: | |
157 | begin | |
158 | dmc_dbg_sel_a_reg_addr_decoded = 1'b0; | |
159 | dmc_dbg_sel_b_reg_addr_decoded = 1'b0; | |
160 | dmc_pcie_cfg_addr_decoded = 1'b0; | |
161 | // vlint flag_system_call off | |
162 | // synopsys translate_off | |
163 | if(daemon_csrbus_valid) | |
164 | begin // axis tbcall_region | |
165 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_cru_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_cru_csr is bad"); `endif | |
166 | end // end of tbcall_region | |
167 | // synopsys translate_on | |
168 | // vlint flag_system_call on | |
169 | end | |
170 | endcase | |
171 | end | |
172 | ||
173 | //==================================================================== | |
174 | // Register violations | |
175 | //==================================================================== | |
176 | //----- reg_acc_vio: dmc_dbg_sel_a_reg | |
177 | reg dmc_dbg_sel_a_reg_acc_vio; | |
178 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
179 | dmc_dbg_sel_a_reg_addr_decoded or | |
180 | daemon_transaction_in_progress) | |
181 | begin | |
182 | if (daemon_transaction_in_progress | ~dmc_dbg_sel_a_reg_addr_decoded) | |
183 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
184 | else | |
185 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
186 | // reads | |
187 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
188 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
189 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
190 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
191 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
192 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
193 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
194 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
195 | // writes | |
196 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
197 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
198 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
199 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
200 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
201 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
202 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
203 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
204 | ||
205 | default: | |
206 | begin | |
207 | dmc_dbg_sel_a_reg_acc_vio = 1'b0; | |
208 | begin // axis tbcall_region | |
209 | // vlint flag_system_call off | |
210 | // synopsys translate_off | |
211 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_cru_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_cru_csr_a_dmc_dbg_sel_a_reg"); `endif | |
212 | // synopsys translate_on | |
213 | // vlint flag_system_call on | |
214 | end // end of tbcall_region | |
215 | end | |
216 | endcase | |
217 | end | |
218 | //----- reg_acc_vio: dmc_dbg_sel_b_reg | |
219 | reg dmc_dbg_sel_b_reg_acc_vio; | |
220 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
221 | dmc_dbg_sel_b_reg_addr_decoded or | |
222 | daemon_transaction_in_progress) | |
223 | begin | |
224 | if (daemon_transaction_in_progress | ~dmc_dbg_sel_b_reg_addr_decoded) | |
225 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
226 | else | |
227 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
228 | // reads | |
229 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
230 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
231 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
232 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
233 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
234 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
235 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
236 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
237 | // writes | |
238 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
239 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
240 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
241 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
242 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
243 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
244 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
245 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
246 | ||
247 | default: | |
248 | begin | |
249 | dmc_dbg_sel_b_reg_acc_vio = 1'b0; | |
250 | begin // axis tbcall_region | |
251 | // vlint flag_system_call off | |
252 | // synopsys translate_off | |
253 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_cru_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_cru_csr_a_dmc_dbg_sel_b_reg"); `endif | |
254 | // synopsys translate_on | |
255 | // vlint flag_system_call on | |
256 | end // end of tbcall_region | |
257 | end | |
258 | endcase | |
259 | end | |
260 | //----- reg_acc_vio: dmc_pcie_cfg | |
261 | reg dmc_pcie_cfg_acc_vio; | |
262 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
263 | dmc_pcie_cfg_addr_decoded or | |
264 | daemon_transaction_in_progress) | |
265 | begin | |
266 | if (daemon_transaction_in_progress | ~dmc_pcie_cfg_addr_decoded) | |
267 | dmc_pcie_cfg_acc_vio = 1'b0; | |
268 | else | |
269 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
270 | // reads | |
271 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
272 | dmc_pcie_cfg_acc_vio = 1'b0; | |
273 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
274 | dmc_pcie_cfg_acc_vio = 1'b0; | |
275 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
276 | dmc_pcie_cfg_acc_vio = 1'b0; | |
277 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
278 | dmc_pcie_cfg_acc_vio = 1'b0; | |
279 | // writes | |
280 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
281 | dmc_pcie_cfg_acc_vio = 1'b0; | |
282 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
283 | dmc_pcie_cfg_acc_vio = 1'b0; | |
284 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
285 | dmc_pcie_cfg_acc_vio = 1'b0; | |
286 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
287 | dmc_pcie_cfg_acc_vio = 1'b0; | |
288 | ||
289 | default: | |
290 | begin | |
291 | dmc_pcie_cfg_acc_vio = 1'b0; | |
292 | begin // axis tbcall_region | |
293 | // vlint flag_system_call off | |
294 | // synopsys translate_off | |
295 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_cru_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_cru_csr_a_dmc_pcie_cfg"); `endif | |
296 | // synopsys translate_on | |
297 | // vlint flag_system_call on | |
298 | end // end of tbcall_region | |
299 | end | |
300 | endcase | |
301 | end | |
302 | ||
303 | //==================================================================== | |
304 | // Status: daemon_csrbus_mapped / csrbus_acc_vio | |
305 | //==================================================================== | |
306 | //----- OUTPUT: daemon_csrbus_mapped | |
307 | assign daemon_csrbus_mapped = clocked_valid_pulse & | |
308 | ( | |
309 | dmc_dbg_sel_a_reg_addr_decoded | | |
310 | dmc_dbg_sel_b_reg_addr_decoded | | |
311 | dmc_pcie_cfg_addr_decoded | |
312 | ); | |
313 | ||
314 | ||
315 | // daemon_csrbus_mapped gets asserted after fixed number of cycles | |
316 | // after daemon_csrbus_valid become high | |
317 | /* 0in assert_together -name mapped_after_valid | |
318 | -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1)) | |
319 | -follower $0in_rising_edge(daemon_csrbus_mapped) | |
320 | -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid") | |
321 | -module dmu_cru_addr_decode | |
322 | -clock clk | |
323 | -active $0in_rising_edge(daemon_csrbus_mapped) | |
324 | */ | |
325 | ||
326 | // daemon_csrbus_mapped is a pulse | |
327 | /* 0in assert_timer -name daemon_csrbus_mapped_pulse | |
328 | -var daemon_csrbus_mapped -max 1 | |
329 | -message "daemon_csrbus_mapped pulse length is not 1" | |
330 | -module dmu_cru_addr_decode | |
331 | -clock clk | |
332 | */ | |
333 | //----- OUTPUT: csrbus_acc_vio | |
334 | assign csrbus_acc_vio = clocked_valid_pulse & | |
335 | dmc_dbg_sel_a_reg_acc_vio | | |
336 | dmc_dbg_sel_b_reg_acc_vio | | |
337 | dmc_pcie_cfg_acc_vio; | |
338 | ||
339 | //==================================================================== | |
340 | // Select | |
341 | //==================================================================== | |
342 | always @(posedge clk) | |
343 | begin | |
344 | if(~rst_l) | |
345 | begin | |
346 | dmc_dbg_sel_a_reg_select_pulse <= 1'b0; | |
347 | dmc_dbg_sel_b_reg_select_pulse <= 1'b0; | |
348 | dmc_pcie_cfg_select_pulse <= 1'b0; | |
349 | end | |
350 | else | |
351 | begin | |
352 | dmc_dbg_sel_a_reg_select_pulse <= | |
353 | ~dmc_dbg_sel_a_reg_acc_vio & | |
354 | clocked_valid_pulse & | |
355 | dmc_dbg_sel_a_reg_addr_decoded; | |
356 | ||
357 | dmc_dbg_sel_b_reg_select_pulse <= | |
358 | ~dmc_dbg_sel_b_reg_acc_vio & | |
359 | clocked_valid_pulse & | |
360 | dmc_dbg_sel_b_reg_addr_decoded; | |
361 | ||
362 | dmc_pcie_cfg_select_pulse <= | |
363 | ~dmc_pcie_cfg_acc_vio & | |
364 | clocked_valid_pulse & | |
365 | dmc_pcie_cfg_addr_decoded; | |
366 | ||
367 | end | |
368 | end | |
369 | ||
370 | //==================================================================== | |
371 | // daemon_csrbus_wr / daemon_csrbus_wr_data | |
372 | //==================================================================== | |
373 | always @(posedge clk) | |
374 | begin | |
375 | if(~rst_l) | |
376 | begin | |
377 | daemon_csrbus_wr_out <= 1'b0; | |
378 | daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0; | |
379 | end | |
380 | else | |
381 | begin | |
382 | daemon_csrbus_wr_out <= daemon_csrbus_wr; | |
383 | daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data; | |
384 | end | |
385 | end | |
386 | ||
387 | //==================================================================== | |
388 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming | |
389 | //==================================================================== | |
390 | ||
391 | //==================================================================== | |
392 | // OUTPUT: daemon_csrbus_done (pipelining) | |
393 | //==================================================================== | |
394 | //----- DONE for internal/extern registers | |
395 | reg stage_1_daemon_csrbus_done_internal_0; | |
396 | reg stage_2_daemon_csrbus_done_internal_0; | |
397 | ||
398 | always @(posedge clk) | |
399 | begin | |
400 | if(~rst_l) | |
401 | begin | |
402 | stage_1_daemon_csrbus_done_internal_0 <= 1'b0; | |
403 | end | |
404 | else | |
405 | begin | |
406 | stage_1_daemon_csrbus_done_internal_0 <= | |
407 | dmc_dbg_sel_a_reg_select_pulse | | |
408 | dmc_dbg_sel_b_reg_select_pulse | | |
409 | dmc_pcie_cfg_select_pulse; | |
410 | end | |
411 | if(~rst_l) | |
412 | begin | |
413 | stage_2_daemon_csrbus_done_internal_0 <= 1'b0; | |
414 | end | |
415 | else | |
416 | begin | |
417 | stage_2_daemon_csrbus_done_internal_0 <= | |
418 | stage_1_daemon_csrbus_done_internal_0; | |
419 | end | |
420 | end | |
421 | ||
422 | //----- OUTPUT: daemon_csrbus_done | |
423 | assign daemon_csrbus_done = daemon_csrbus_valid & | |
424 | ( | |
425 | stage_2_daemon_csrbus_done_internal_0 | |
426 | ); | |
427 | ||
428 | // daemon_csrbus_done gets asserted only when csrbus_valid is high | |
429 | /* 0in assert -name daemon_csrbus_done_high | |
430 | -var daemon_csrbus_valid -active daemon_csrbus_done | |
431 | -message "csrbus_done got asserted while csrbus_valid is low" | |
432 | -module dmu_cru_addr_decode | |
433 | -clock clk | |
434 | */ | |
435 | ||
436 | // daemon_csrbus_done is a pulse | |
437 | /* 0in assert_timer -name daemon_csrbus_done_pulse | |
438 | -var daemon_csrbus_done -max 1 | |
439 | -message "csrbus_done pulse length is not 1" | |
440 | -module dmu_cru_addr_decode | |
441 | -clock clk | |
442 | */ | |
443 | ||
444 | endmodule // dmu_cru_addr_decode |