[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_cru_csr_dmc_pcie_cfg_entry.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_cru_csr_dmc_pcie_cfg_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
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// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
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// ========== Copyright Header End ============================================
module dmu_cru_csr_dmc_pcie_cfg_entry 
	(
	// synopsys translate_off
	  omni_ld,
	  omni_data,
	// synopsys translate_on
	clk,
	rst_l,
	w_ld,
	csrbus_wr_data,
	dmc_pcie_cfg_csrbus_read_data
	);

//====================================================================
//     Polarity declarations
//====================================================================
// synopsys translate_off
  input  omni_ld;  // Omni load
// vlint flag_input_port_not_connected off
  input  [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH - 1:0] omni_data;  // Omni write
                                                                  // data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input  clk;  // Clock signal
input  rst_l;  // Reset signal
input  w_ld;  // SW load
// vlint flag_input_port_not_connected off
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH-1:0] dmc_pcie_cfg_csrbus_read_data;
    // SW read data

//====================================================================
//     Type declarations
//====================================================================
// synopsys translate_off
  wire omni_ld;  // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
  wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH - 1:0] omni_data;  // Omni write
                                                                // data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk;  // Clock signal
wire rst_l;  // Reset signal
wire w_ld;  // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH-1:0] dmc_pcie_cfg_csrbus_read_data;
    // SW read data

//====================================================================
//     Logic     
//====================================================================

//----- Reset values
// verilint 531 off
wire [7:0] reset_bus_num = 8'h0;
wire [15:0] reset_req_id = 16'h0;
// verilint 531 on

//----- Active high reset wires 
wire rst_l_active_high = ~rst_l;

//====================================================
//     Instantiation of flops
//====================================================

// bit 0
csr_sw csr_sw_0
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[0]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[0]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[0])
	);

// bit 1
csr_sw csr_sw_1
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[1]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[1]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[1])
	);

// bit 2
csr_sw csr_sw_2
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[2]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[2]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[2])
	);

// bit 3
csr_sw csr_sw_3
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[3]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[3]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[3])
	);

// bit 4
csr_sw csr_sw_4
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[4]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[4]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[4])
	);

// bit 5
csr_sw csr_sw_5
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[5]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[5]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[5])
	);

// bit 6
csr_sw csr_sw_6
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[6]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[6]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[6]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[6])
	);

// bit 7
csr_sw csr_sw_7
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[7]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[7]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[7]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[7])
	);

// bit 8
csr_sw csr_sw_8
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[8]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[8]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[8]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[8])
	);

// bit 9
csr_sw csr_sw_9
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[9]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[9]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[9]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[9])
	);

// bit 10
csr_sw csr_sw_10
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[10]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[10]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[10]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[10])
	);

// bit 11
csr_sw csr_sw_11
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[11]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[11]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[11]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[11])
	);

// bit 12
csr_sw csr_sw_12
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[12]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[12]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[12]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[12])
	);

// bit 13
csr_sw csr_sw_13
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[13]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[13]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[13]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[13])
	);

// bit 14
csr_sw csr_sw_14
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[14]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[14]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[14]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[14])
	);

// bit 15
csr_sw csr_sw_15
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[15]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_req_id[15]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[15]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[15])
	);

assign  dmc_pcie_cfg_csrbus_read_data[16] = 1'b0;  // bit 16
assign  dmc_pcie_cfg_csrbus_read_data[17] = 1'b0;  // bit 17
assign  dmc_pcie_cfg_csrbus_read_data[18] = 1'b0;  // bit 18
assign  dmc_pcie_cfg_csrbus_read_data[19] = 1'b0;  // bit 19
assign  dmc_pcie_cfg_csrbus_read_data[20] = 1'b0;  // bit 20
assign  dmc_pcie_cfg_csrbus_read_data[21] = 1'b0;  // bit 21
assign  dmc_pcie_cfg_csrbus_read_data[22] = 1'b0;  // bit 22
assign  dmc_pcie_cfg_csrbus_read_data[23] = 1'b0;  // bit 23
// bit 24
csr_sw csr_sw_24
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[24]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[24]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[24])
	);

// bit 25
csr_sw csr_sw_25
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[25]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[25]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[25])
	);

// bit 26
csr_sw csr_sw_26
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[26]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[26]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[26])
	);

// bit 27
csr_sw csr_sw_27
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[27]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[27]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[27])
	);

// bit 28
csr_sw csr_sw_28
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[28]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[28]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[28])
	);

// bit 29
csr_sw csr_sw_29
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[29]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[29]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[29])
	);

// bit 30
csr_sw csr_sw_30
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[30]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[6]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[30]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[30])
	);

// bit 31
csr_sw csr_sw_31
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[31]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_bus_num[7]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[31]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (dmc_pcie_cfg_csrbus_read_data[31])
	);

assign  dmc_pcie_cfg_csrbus_read_data[32] = 1'b0;  // bit 32
assign  dmc_pcie_cfg_csrbus_read_data[33] = 1'b0;  // bit 33
assign  dmc_pcie_cfg_csrbus_read_data[34] = 1'b0;  // bit 34
assign  dmc_pcie_cfg_csrbus_read_data[35] = 1'b0;  // bit 35
assign  dmc_pcie_cfg_csrbus_read_data[36] = 1'b0;  // bit 36
assign  dmc_pcie_cfg_csrbus_read_data[37] = 1'b0;  // bit 37
assign  dmc_pcie_cfg_csrbus_read_data[38] = 1'b0;  // bit 38
assign  dmc_pcie_cfg_csrbus_read_data[39] = 1'b0;  // bit 39
assign  dmc_pcie_cfg_csrbus_read_data[40] = 1'b0;  // bit 40
assign  dmc_pcie_cfg_csrbus_read_data[41] = 1'b0;  // bit 41
assign  dmc_pcie_cfg_csrbus_read_data[42] = 1'b0;  // bit 42
assign  dmc_pcie_cfg_csrbus_read_data[43] = 1'b0;  // bit 43
assign  dmc_pcie_cfg_csrbus_read_data[44] = 1'b0;  // bit 44
assign  dmc_pcie_cfg_csrbus_read_data[45] = 1'b0;  // bit 45
assign  dmc_pcie_cfg_csrbus_read_data[46] = 1'b0;  // bit 46
assign  dmc_pcie_cfg_csrbus_read_data[47] = 1'b0;  // bit 47
assign  dmc_pcie_cfg_csrbus_read_data[48] = 1'b0;  // bit 48
assign  dmc_pcie_cfg_csrbus_read_data[49] = 1'b0;  // bit 49
assign  dmc_pcie_cfg_csrbus_read_data[50] = 1'b0;  // bit 50
assign  dmc_pcie_cfg_csrbus_read_data[51] = 1'b0;  // bit 51
assign  dmc_pcie_cfg_csrbus_read_data[52] = 1'b0;  // bit 52
assign  dmc_pcie_cfg_csrbus_read_data[53] = 1'b0;  // bit 53
assign  dmc_pcie_cfg_csrbus_read_data[54] = 1'b0;  // bit 54
assign  dmc_pcie_cfg_csrbus_read_data[55] = 1'b0;  // bit 55
assign  dmc_pcie_cfg_csrbus_read_data[56] = 1'b0;  // bit 56
assign  dmc_pcie_cfg_csrbus_read_data[57] = 1'b0;  // bit 57
assign  dmc_pcie_cfg_csrbus_read_data[58] = 1'b0;  // bit 58
assign  dmc_pcie_cfg_csrbus_read_data[59] = 1'b0;  // bit 59
assign  dmc_pcie_cfg_csrbus_read_data[60] = 1'b0;  // bit 60
assign  dmc_pcie_cfg_csrbus_read_data[61] = 1'b0;  // bit 61
assign  dmc_pcie_cfg_csrbus_read_data[62] = 1'b0;  // bit 62
assign  dmc_pcie_cfg_csrbus_read_data[63] = 1'b0;  // bit 63

endmodule // dmu_cru_csr_dmc_pcie_cfg_entry
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_cru_csr_dmc_pcie_cfg_entry.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_cru_csr_dmc_pcie_cfg_entry
	36	(
	37	// synopsys translate_off
	38	omni_ld,
	39	omni_data,
	40	// synopsys translate_on
	41	clk,
	42	rst_l,
	43	w_ld,
	44	csrbus_wr_data,
	45	dmc_pcie_cfg_csrbus_read_data
	46	);
	47
	48	//====================================================================
	49	// Polarity declarations
	50	//====================================================================
	51	// synopsys translate_off
	52	input omni_ld; // Omni load
	53	// vlint flag_input_port_not_connected off
	54	input [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH - 1:0] omni_data; // Omni write
	55	// data
	56	// synopsys translate_on
	57	// vlint flag_input_port_not_connected on
	58	input clk; // Clock signal
	59	input rst_l; // Reset signal
	60	input w_ld; // SW load
	61	// vlint flag_input_port_not_connected off
	62	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
	63	// vlint flag_input_port_not_connected on
	64	output [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH-1:0] dmc_pcie_cfg_csrbus_read_data;
65	// SW read data
66
67	//====================================================================
68	// Type declarations
69	//====================================================================
70	// synopsys translate_off
71	wire omni_ld; // Omni load
72	// vlint flag_dangling_net_within_module off
73	// vlint flag_net_has_no_load off
74	wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH - 1:0] omni_data; // Omni write
75	// data
76	// synopsys translate_on
77	// vlint flag_dangling_net_within_module on
78	// vlint flag_net_has_no_load on
79	wire clk; // Clock signal
80	wire rst_l; // Reset signal
81	wire w_ld; // SW load
82	// vlint flag_dangling_net_within_module off
83	// vlint flag_net_has_no_load off
84	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
85	// vlint flag_dangling_net_within_module on
86	// vlint flag_net_has_no_load on
87	wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH-1:0] dmc_pcie_cfg_csrbus_read_data;
88	// SW read data
89
90	//====================================================================
91	// Logic
92	//====================================================================
93
94	//----- Reset values
95	// verilint 531 off
96	wire [7:0] reset_bus_num = 8'h0;
97	wire [15:0] reset_req_id = 16'h0;
98	// verilint 531 on
99
100	//----- Active high reset wires
101	wire rst_l_active_high = ~rst_l;
102
103	//====================================================
104	// Instantiation of flops
105	//====================================================
106
107	// bit 0
108	csr_sw csr_sw_0
109	(
110	// synopsys translate_off
111	.omni_ld (omni_ld),
112	.omni_data (omni_data[0]),
113	.omni_rw_alias (1'b1),
114	.omni_rw1c_alias (1'b0),
115	.omni_rw1s_alias (1'b0),
116	// synopsys translate_on
117	.rst (rst_l_active_high),
118	.rst_val (reset_req_id[0]),
119	.csr_ld (w_ld),
120	.csr_data (csrbus_wr_data[0]),
121	.rw_alias (1'b1),
122	.rw1c_alias (1'b0),
123	.rw1s_alias (1'b0),
124	.hw_ld (1'b0),
125	.hw_data (1'b0),
126	.cp (clk),
127	.q (dmc_pcie_cfg_csrbus_read_data[0])
128	);
129
130	// bit 1
131	csr_sw csr_sw_1
132	(
133	// synopsys translate_off
134	.omni_ld (omni_ld),
135	.omni_data (omni_data[1]),
136	.omni_rw_alias (1'b1),
137	.omni_rw1c_alias (1'b0),
138	.omni_rw1s_alias (1'b0),
139	// synopsys translate_on
140	.rst (rst_l_active_high),
141	.rst_val (reset_req_id[1]),
142	.csr_ld (w_ld),
143	.csr_data (csrbus_wr_data[1]),
144	.rw_alias (1'b1),
145	.rw1c_alias (1'b0),
146	.rw1s_alias (1'b0),
147	.hw_ld (1'b0),
148	.hw_data (1'b0),
149	.cp (clk),
150	.q (dmc_pcie_cfg_csrbus_read_data[1])
151	);
152
153	// bit 2
154	csr_sw csr_sw_2
155	(
156	// synopsys translate_off
157	.omni_ld (omni_ld),
158	.omni_data (omni_data[2]),
159	.omni_rw_alias (1'b1),
160	.omni_rw1c_alias (1'b0),
161	.omni_rw1s_alias (1'b0),
162	// synopsys translate_on
163	.rst (rst_l_active_high),
164	.rst_val (reset_req_id[2]),
165	.csr_ld (w_ld),
166	.csr_data (csrbus_wr_data[2]),
167	.rw_alias (1'b1),
168	.rw1c_alias (1'b0),
169	.rw1s_alias (1'b0),
170	.hw_ld (1'b0),
171	.hw_data (1'b0),
172	.cp (clk),
173	.q (dmc_pcie_cfg_csrbus_read_data[2])
174	);
175
176	// bit 3
177	csr_sw csr_sw_3
178	(
179	// synopsys translate_off
180	.omni_ld (omni_ld),
181	.omni_data (omni_data[3]),
182	.omni_rw_alias (1'b1),
183	.omni_rw1c_alias (1'b0),
184	.omni_rw1s_alias (1'b0),
185	// synopsys translate_on
186	.rst (rst_l_active_high),
187	.rst_val (reset_req_id[3]),
188	.csr_ld (w_ld),
189	.csr_data (csrbus_wr_data[3]),
190	.rw_alias (1'b1),
191	.rw1c_alias (1'b0),
192	.rw1s_alias (1'b0),
193	.hw_ld (1'b0),
194	.hw_data (1'b0),
195	.cp (clk),
196	.q (dmc_pcie_cfg_csrbus_read_data[3])
197	);
198
199	// bit 4
200	csr_sw csr_sw_4
201	(
202	// synopsys translate_off
203	.omni_ld (omni_ld),
204	.omni_data (omni_data[4]),
205	.omni_rw_alias (1'b1),
206	.omni_rw1c_alias (1'b0),
207	.omni_rw1s_alias (1'b0),
208	// synopsys translate_on
209	.rst (rst_l_active_high),
210	.rst_val (reset_req_id[4]),
211	.csr_ld (w_ld),
212	.csr_data (csrbus_wr_data[4]),
213	.rw_alias (1'b1),
214	.rw1c_alias (1'b0),
215	.rw1s_alias (1'b0),
216	.hw_ld (1'b0),
217	.hw_data (1'b0),
218	.cp (clk),
219	.q (dmc_pcie_cfg_csrbus_read_data[4])
220	);
221
222	// bit 5
223	csr_sw csr_sw_5
224	(
225	// synopsys translate_off
226	.omni_ld (omni_ld),
227	.omni_data (omni_data[5]),
228	.omni_rw_alias (1'b1),
229	.omni_rw1c_alias (1'b0),
230	.omni_rw1s_alias (1'b0),
231	// synopsys translate_on
232	.rst (rst_l_active_high),
233	.rst_val (reset_req_id[5]),
234	.csr_ld (w_ld),
235	.csr_data (csrbus_wr_data[5]),
236	.rw_alias (1'b1),
237	.rw1c_alias (1'b0),
238	.rw1s_alias (1'b0),
239	.hw_ld (1'b0),
240	.hw_data (1'b0),
241	.cp (clk),
242	.q (dmc_pcie_cfg_csrbus_read_data[5])
243	);
244
245	// bit 6
246	csr_sw csr_sw_6
247	(
248	// synopsys translate_off
249	.omni_ld (omni_ld),
250	.omni_data (omni_data[6]),
251	.omni_rw_alias (1'b1),
252	.omni_rw1c_alias (1'b0),
253	.omni_rw1s_alias (1'b0),
254	// synopsys translate_on
255	.rst (rst_l_active_high),
256	.rst_val (reset_req_id[6]),
257	.csr_ld (w_ld),
258	.csr_data (csrbus_wr_data[6]),
259	.rw_alias (1'b1),
260	.rw1c_alias (1'b0),
261	.rw1s_alias (1'b0),
262	.hw_ld (1'b0),
263	.hw_data (1'b0),
264	.cp (clk),
265	.q (dmc_pcie_cfg_csrbus_read_data[6])
266	);
267
268	// bit 7
269	csr_sw csr_sw_7
270	(
271	// synopsys translate_off
272	.omni_ld (omni_ld),
273	.omni_data (omni_data[7]),
274	.omni_rw_alias (1'b1),
275	.omni_rw1c_alias (1'b0),
276	.omni_rw1s_alias (1'b0),
277	// synopsys translate_on
278	.rst (rst_l_active_high),
279	.rst_val (reset_req_id[7]),
280	.csr_ld (w_ld),
281	.csr_data (csrbus_wr_data[7]),
282	.rw_alias (1'b1),
283	.rw1c_alias (1'b0),
284	.rw1s_alias (1'b0),
285	.hw_ld (1'b0),
286	.hw_data (1'b0),
287	.cp (clk),
288	.q (dmc_pcie_cfg_csrbus_read_data[7])
289	);
290
291	// bit 8
292	csr_sw csr_sw_8
293	(
294	// synopsys translate_off
295	.omni_ld (omni_ld),
296	.omni_data (omni_data[8]),
297	.omni_rw_alias (1'b1),
298	.omni_rw1c_alias (1'b0),
299	.omni_rw1s_alias (1'b0),
300	// synopsys translate_on
301	.rst (rst_l_active_high),
302	.rst_val (reset_req_id[8]),
303	.csr_ld (w_ld),
304	.csr_data (csrbus_wr_data[8]),
305	.rw_alias (1'b1),
306	.rw1c_alias (1'b0),
307	.rw1s_alias (1'b0),
308	.hw_ld (1'b0),
309	.hw_data (1'b0),
310	.cp (clk),
311	.q (dmc_pcie_cfg_csrbus_read_data[8])
312	);
313
314	// bit 9
315	csr_sw csr_sw_9
316	(
317	// synopsys translate_off
318	.omni_ld (omni_ld),
319	.omni_data (omni_data[9]),
320	.omni_rw_alias (1'b1),
321	.omni_rw1c_alias (1'b0),
322	.omni_rw1s_alias (1'b0),
323	// synopsys translate_on
324	.rst (rst_l_active_high),
325	.rst_val (reset_req_id[9]),
326	.csr_ld (w_ld),
327	.csr_data (csrbus_wr_data[9]),
328	.rw_alias (1'b1),
329	.rw1c_alias (1'b0),
330	.rw1s_alias (1'b0),
331	.hw_ld (1'b0),
332	.hw_data (1'b0),
333	.cp (clk),
334	.q (dmc_pcie_cfg_csrbus_read_data[9])
335	);
336
337	// bit 10
338	csr_sw csr_sw_10
339	(
340	// synopsys translate_off
341	.omni_ld (omni_ld),
342	.omni_data (omni_data[10]),
343	.omni_rw_alias (1'b1),
344	.omni_rw1c_alias (1'b0),
345	.omni_rw1s_alias (1'b0),
346	// synopsys translate_on
347	.rst (rst_l_active_high),
348	.rst_val (reset_req_id[10]),
349	.csr_ld (w_ld),
350	.csr_data (csrbus_wr_data[10]),
351	.rw_alias (1'b1),
352	.rw1c_alias (1'b0),
353	.rw1s_alias (1'b0),
354	.hw_ld (1'b0),
355	.hw_data (1'b0),
356	.cp (clk),
357	.q (dmc_pcie_cfg_csrbus_read_data[10])
358	);
359
360	// bit 11
361	csr_sw csr_sw_11
362	(
363	// synopsys translate_off
364	.omni_ld (omni_ld),
365	.omni_data (omni_data[11]),
366	.omni_rw_alias (1'b1),
367	.omni_rw1c_alias (1'b0),
368	.omni_rw1s_alias (1'b0),
369	// synopsys translate_on
370	.rst (rst_l_active_high),
371	.rst_val (reset_req_id[11]),
372	.csr_ld (w_ld),
373	.csr_data (csrbus_wr_data[11]),
374	.rw_alias (1'b1),
375	.rw1c_alias (1'b0),
376	.rw1s_alias (1'b0),
377	.hw_ld (1'b0),
378	.hw_data (1'b0),
379	.cp (clk),
380	.q (dmc_pcie_cfg_csrbus_read_data[11])
381	);
382
383	// bit 12
384	csr_sw csr_sw_12
385	(
386	// synopsys translate_off
387	.omni_ld (omni_ld),
388	.omni_data (omni_data[12]),
389	.omni_rw_alias (1'b1),
390	.omni_rw1c_alias (1'b0),
391	.omni_rw1s_alias (1'b0),
392	// synopsys translate_on
393	.rst (rst_l_active_high),
394	.rst_val (reset_req_id[12]),
395	.csr_ld (w_ld),
396	.csr_data (csrbus_wr_data[12]),
397	.rw_alias (1'b1),
398	.rw1c_alias (1'b0),
399	.rw1s_alias (1'b0),
400	.hw_ld (1'b0),
401	.hw_data (1'b0),
402	.cp (clk),
403	.q (dmc_pcie_cfg_csrbus_read_data[12])
404	);
405
406	// bit 13
407	csr_sw csr_sw_13
408	(
409	// synopsys translate_off
410	.omni_ld (omni_ld),
411	.omni_data (omni_data[13]),
412	.omni_rw_alias (1'b1),
413	.omni_rw1c_alias (1'b0),
414	.omni_rw1s_alias (1'b0),
415	// synopsys translate_on
416	.rst (rst_l_active_high),
417	.rst_val (reset_req_id[13]),
418	.csr_ld (w_ld),
419	.csr_data (csrbus_wr_data[13]),
420	.rw_alias (1'b1),
421	.rw1c_alias (1'b0),
422	.rw1s_alias (1'b0),
423	.hw_ld (1'b0),
424	.hw_data (1'b0),
425	.cp (clk),
426	.q (dmc_pcie_cfg_csrbus_read_data[13])
427	);
428
429	// bit 14
430	csr_sw csr_sw_14
431	(
432	// synopsys translate_off
433	.omni_ld (omni_ld),
434	.omni_data (omni_data[14]),
435	.omni_rw_alias (1'b1),
436	.omni_rw1c_alias (1'b0),
437	.omni_rw1s_alias (1'b0),
438	// synopsys translate_on
439	.rst (rst_l_active_high),
440	.rst_val (reset_req_id[14]),
441	.csr_ld (w_ld),
442	.csr_data (csrbus_wr_data[14]),
443	.rw_alias (1'b1),
444	.rw1c_alias (1'b0),
445	.rw1s_alias (1'b0),
446	.hw_ld (1'b0),
447	.hw_data (1'b0),
448	.cp (clk),
449	.q (dmc_pcie_cfg_csrbus_read_data[14])
450	);
451
452	// bit 15
453	csr_sw csr_sw_15
454	(
455	// synopsys translate_off
456	.omni_ld (omni_ld),
457	.omni_data (omni_data[15]),
458	.omni_rw_alias (1'b1),
459	.omni_rw1c_alias (1'b0),
460	.omni_rw1s_alias (1'b0),
461	// synopsys translate_on
462	.rst (rst_l_active_high),
463	.rst_val (reset_req_id[15]),
464	.csr_ld (w_ld),
465	.csr_data (csrbus_wr_data[15]),
466	.rw_alias (1'b1),
467	.rw1c_alias (1'b0),
468	.rw1s_alias (1'b0),
469	.hw_ld (1'b0),
470	.hw_data (1'b0),
471	.cp (clk),
472	.q (dmc_pcie_cfg_csrbus_read_data[15])
473	);
474
475	assign dmc_pcie_cfg_csrbus_read_data[16] = 1'b0; // bit 16
476	assign dmc_pcie_cfg_csrbus_read_data[17] = 1'b0; // bit 17
477	assign dmc_pcie_cfg_csrbus_read_data[18] = 1'b0; // bit 18
478	assign dmc_pcie_cfg_csrbus_read_data[19] = 1'b0; // bit 19
479	assign dmc_pcie_cfg_csrbus_read_data[20] = 1'b0; // bit 20
480	assign dmc_pcie_cfg_csrbus_read_data[21] = 1'b0; // bit 21
481	assign dmc_pcie_cfg_csrbus_read_data[22] = 1'b0; // bit 22
482	assign dmc_pcie_cfg_csrbus_read_data[23] = 1'b0; // bit 23
483	// bit 24
484	csr_sw csr_sw_24
485	(
486	// synopsys translate_off
487	.omni_ld (omni_ld),
488	.omni_data (omni_data[24]),
489	.omni_rw_alias (1'b1),
490	.omni_rw1c_alias (1'b0),
491	.omni_rw1s_alias (1'b0),
492	// synopsys translate_on
493	.rst (rst_l_active_high),
494	.rst_val (reset_bus_num[0]),
495	.csr_ld (w_ld),
496	.csr_data (csrbus_wr_data[24]),
497	.rw_alias (1'b1),
498	.rw1c_alias (1'b0),
499	.rw1s_alias (1'b0),
500	.hw_ld (1'b0),
501	.hw_data (1'b0),
502	.cp (clk),
503	.q (dmc_pcie_cfg_csrbus_read_data[24])
504	);
505
506	// bit 25
507	csr_sw csr_sw_25
508	(
509	// synopsys translate_off
510	.omni_ld (omni_ld),
511	.omni_data (omni_data[25]),
512	.omni_rw_alias (1'b1),
513	.omni_rw1c_alias (1'b0),
514	.omni_rw1s_alias (1'b0),
515	// synopsys translate_on
516	.rst (rst_l_active_high),
517	.rst_val (reset_bus_num[1]),
518	.csr_ld (w_ld),
519	.csr_data (csrbus_wr_data[25]),
520	.rw_alias (1'b1),
521	.rw1c_alias (1'b0),
522	.rw1s_alias (1'b0),
523	.hw_ld (1'b0),
524	.hw_data (1'b0),
525	.cp (clk),
526	.q (dmc_pcie_cfg_csrbus_read_data[25])
527	);
528
529	// bit 26
530	csr_sw csr_sw_26
531	(
532	// synopsys translate_off
533	.omni_ld (omni_ld),
534	.omni_data (omni_data[26]),
535	.omni_rw_alias (1'b1),
536	.omni_rw1c_alias (1'b0),
537	.omni_rw1s_alias (1'b0),
538	// synopsys translate_on
539	.rst (rst_l_active_high),
540	.rst_val (reset_bus_num[2]),
541	.csr_ld (w_ld),
542	.csr_data (csrbus_wr_data[26]),
543	.rw_alias (1'b1),
544	.rw1c_alias (1'b0),
545	.rw1s_alias (1'b0),
546	.hw_ld (1'b0),
547	.hw_data (1'b0),
548	.cp (clk),
549	.q (dmc_pcie_cfg_csrbus_read_data[26])
550	);
551
552	// bit 27
553	csr_sw csr_sw_27
554	(
555	// synopsys translate_off
556	.omni_ld (omni_ld),
557	.omni_data (omni_data[27]),
558	.omni_rw_alias (1'b1),
559	.omni_rw1c_alias (1'b0),
560	.omni_rw1s_alias (1'b0),
561	// synopsys translate_on
562	.rst (rst_l_active_high),
563	.rst_val (reset_bus_num[3]),
564	.csr_ld (w_ld),
565	.csr_data (csrbus_wr_data[27]),
566	.rw_alias (1'b1),
567	.rw1c_alias (1'b0),
568	.rw1s_alias (1'b0),
569	.hw_ld (1'b0),
570	.hw_data (1'b0),
571	.cp (clk),
572	.q (dmc_pcie_cfg_csrbus_read_data[27])
573	);
574
575	// bit 28
576	csr_sw csr_sw_28
577	(
578	// synopsys translate_off
579	.omni_ld (omni_ld),
580	.omni_data (omni_data[28]),
581	.omni_rw_alias (1'b1),
582	.omni_rw1c_alias (1'b0),
583	.omni_rw1s_alias (1'b0),
584	// synopsys translate_on
585	.rst (rst_l_active_high),
586	.rst_val (reset_bus_num[4]),
587	.csr_ld (w_ld),
588	.csr_data (csrbus_wr_data[28]),
589	.rw_alias (1'b1),
590	.rw1c_alias (1'b0),
591	.rw1s_alias (1'b0),
592	.hw_ld (1'b0),
593	.hw_data (1'b0),
594	.cp (clk),
595	.q (dmc_pcie_cfg_csrbus_read_data[28])
596	);
597
598	// bit 29
599	csr_sw csr_sw_29
600	(
601	// synopsys translate_off
602	.omni_ld (omni_ld),
603	.omni_data (omni_data[29]),
604	.omni_rw_alias (1'b1),
605	.omni_rw1c_alias (1'b0),
606	.omni_rw1s_alias (1'b0),
607	// synopsys translate_on
608	.rst (rst_l_active_high),
609	.rst_val (reset_bus_num[5]),
610	.csr_ld (w_ld),
611	.csr_data (csrbus_wr_data[29]),
612	.rw_alias (1'b1),
613	.rw1c_alias (1'b0),
614	.rw1s_alias (1'b0),
615	.hw_ld (1'b0),
616	.hw_data (1'b0),
617	.cp (clk),
618	.q (dmc_pcie_cfg_csrbus_read_data[29])
619	);
620
621	// bit 30
622	csr_sw csr_sw_30
623	(
624	// synopsys translate_off
625	.omni_ld (omni_ld),
626	.omni_data (omni_data[30]),
627	.omni_rw_alias (1'b1),
628	.omni_rw1c_alias (1'b0),
629	.omni_rw1s_alias (1'b0),
630	// synopsys translate_on
631	.rst (rst_l_active_high),
632	.rst_val (reset_bus_num[6]),
633	.csr_ld (w_ld),
634	.csr_data (csrbus_wr_data[30]),
635	.rw_alias (1'b1),
636	.rw1c_alias (1'b0),
637	.rw1s_alias (1'b0),
638	.hw_ld (1'b0),
639	.hw_data (1'b0),
640	.cp (clk),
641	.q (dmc_pcie_cfg_csrbus_read_data[30])
642	);
643
644	// bit 31
645	csr_sw csr_sw_31
646	(
647	// synopsys translate_off
648	.omni_ld (omni_ld),
649	.omni_data (omni_data[31]),
650	.omni_rw_alias (1'b1),
651	.omni_rw1c_alias (1'b0),
652	.omni_rw1s_alias (1'b0),
653	// synopsys translate_on
654	.rst (rst_l_active_high),
655	.rst_val (reset_bus_num[7]),
656	.csr_ld (w_ld),
657	.csr_data (csrbus_wr_data[31]),
658	.rw_alias (1'b1),
659	.rw1c_alias (1'b0),
660	.rw1s_alias (1'b0),
661	.hw_ld (1'b0),
662	.hw_data (1'b0),
663	.cp (clk),
664	.q (dmc_pcie_cfg_csrbus_read_data[31])
665	);
666
667	assign dmc_pcie_cfg_csrbus_read_data[32] = 1'b0; // bit 32
668	assign dmc_pcie_cfg_csrbus_read_data[33] = 1'b0; // bit 33
669	assign dmc_pcie_cfg_csrbus_read_data[34] = 1'b0; // bit 34
670	assign dmc_pcie_cfg_csrbus_read_data[35] = 1'b0; // bit 35
671	assign dmc_pcie_cfg_csrbus_read_data[36] = 1'b0; // bit 36
672	assign dmc_pcie_cfg_csrbus_read_data[37] = 1'b0; // bit 37
673	assign dmc_pcie_cfg_csrbus_read_data[38] = 1'b0; // bit 38
674	assign dmc_pcie_cfg_csrbus_read_data[39] = 1'b0; // bit 39
675	assign dmc_pcie_cfg_csrbus_read_data[40] = 1'b0; // bit 40
676	assign dmc_pcie_cfg_csrbus_read_data[41] = 1'b0; // bit 41
677	assign dmc_pcie_cfg_csrbus_read_data[42] = 1'b0; // bit 42
678	assign dmc_pcie_cfg_csrbus_read_data[43] = 1'b0; // bit 43
679	assign dmc_pcie_cfg_csrbus_read_data[44] = 1'b0; // bit 44
680	assign dmc_pcie_cfg_csrbus_read_data[45] = 1'b0; // bit 45
681	assign dmc_pcie_cfg_csrbus_read_data[46] = 1'b0; // bit 46
682	assign dmc_pcie_cfg_csrbus_read_data[47] = 1'b0; // bit 47
683	assign dmc_pcie_cfg_csrbus_read_data[48] = 1'b0; // bit 48
684	assign dmc_pcie_cfg_csrbus_read_data[49] = 1'b0; // bit 49
685	assign dmc_pcie_cfg_csrbus_read_data[50] = 1'b0; // bit 50
686	assign dmc_pcie_cfg_csrbus_read_data[51] = 1'b0; // bit 51
687	assign dmc_pcie_cfg_csrbus_read_data[52] = 1'b0; // bit 52
688	assign dmc_pcie_cfg_csrbus_read_data[53] = 1'b0; // bit 53
689	assign dmc_pcie_cfg_csrbus_read_data[54] = 1'b0; // bit 54
690	assign dmc_pcie_cfg_csrbus_read_data[55] = 1'b0; // bit 55
691	assign dmc_pcie_cfg_csrbus_read_data[56] = 1'b0; // bit 56
692	assign dmc_pcie_cfg_csrbus_read_data[57] = 1'b0; // bit 57
693	assign dmc_pcie_cfg_csrbus_read_data[58] = 1'b0; // bit 58
694	assign dmc_pcie_cfg_csrbus_read_data[59] = 1'b0; // bit 59
695	assign dmc_pcie_cfg_csrbus_read_data[60] = 1'b0; // bit 60
696	assign dmc_pcie_cfg_csrbus_read_data[61] = 1'b0; // bit 61
697	assign dmc_pcie_cfg_csrbus_read_data[62] = 1'b0; // bit 62
698	assign dmc_pcie_cfg_csrbus_read_data[63] = 1'b0; // bit 63
699
700	endmodule // dmu_cru_csr_dmc_pcie_cfg_entry