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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_cru_defines.h
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmu_cru_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`ifdef FIRE_DLC_CRU_DEFINES
39`else
40`define FIRE_DLC_CRU_DEFINES
41
42`define FIRE_DLC_CRU_INSTANCE_ID_VALUE_A 1'h0
43`define FIRE_DLC_CRU_INSTANCE_ID_VALUE_B 1'h1
44
45//-------------------------------------------------------
46//----- Variable definitions for register fire_dlc_cru_csr_dmc_dbg_sel_a_reg
47//-------------------------------------------------------
48
49`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_HW_ADDR 27'b000000011001010011000000000
50`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR 30'b000000011001010011000000000000
51`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_A_REG_HW_ADDR 27'b000000011101010011000000000
52`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_A_REG_ADDR 30'b000000011101010011000000000000
53
54`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WIDTH 64
55`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_DEPTH 1
56`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SLC 63:0
57`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_INT_SLC 63:0
58`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_POSITION 0
59`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_LOW_ADDR_WIDTH 0
60`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_ADDR_RANGE 26:0
61`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000001111111111
62`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
63`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000001111111111
64`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
65`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
66`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
67`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
68`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000001111111111
69`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111110000000000
70`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
71`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
72`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_INTERNAL_REG 1
73`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_ZERO_TIME_OMNI 1
74`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_NUM_FIELDS 3
75`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_FID 0
76`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_SLC 9:6
77`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_WIDTH 4
78`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_INT_SLC 3:0
79`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_POSITION 6
80`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000
81`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
82`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_POR_VALUE 4'b0000
83`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_FID 1
84`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_SLC 5:3
85`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_WIDTH 3
86`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_INT_SLC 2:0
87`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_POSITION 3
88`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111000
89`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
90`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_POR_VALUE 3'b000
91`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_FID 2
92`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_SLC 2:0
93`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_WIDTH 3
94`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_INT_SLC 2:0
95`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_POSITION 0
96`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000111
97`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
98`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_POR_VALUE 3'b000
99
100//-------------------------------------------------------
101//----- Variable definitions for register fire_dlc_cru_csr_dmc_dbg_sel_b_reg
102//-------------------------------------------------------
103
104`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_HW_ADDR 27'b000000011001010011000000001
105`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR 30'b000000011001010011000000001000
106`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_B_REG_HW_ADDR 27'b000000011101010011000000001
107`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_B_REG_ADDR 30'b000000011101010011000000001000
108
109`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH 64
110`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_DEPTH 1
111`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SLC 63:0
112`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_INT_SLC 63:0
113`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_POSITION 0
114`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_LOW_ADDR_WIDTH 0
115`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_ADDR_RANGE 26:0
116`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000001111111111
117`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
118`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000001111111111
119`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
120`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
121`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
122`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
123`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000001111111111
124`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111110000000000
125`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
126`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
127`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_INTERNAL_REG 1
128`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_ZERO_TIME_OMNI 1
129`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_NUM_FIELDS 3
130`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_FID 0
131`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_SLC 9:6
132`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_WIDTH 4
133`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_INT_SLC 3:0
134`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_POSITION 6
135`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000
136`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
137`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_POR_VALUE 4'b0000
138`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_FID 1
139`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_SLC 5:3
140`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_WIDTH 3
141`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_INT_SLC 2:0
142`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_POSITION 3
143`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111000
144`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
145`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_POR_VALUE 3'b000
146`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_FID 2
147`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_SLC 2:0
148`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_WIDTH 3
149`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_INT_SLC 2:0
150`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_POSITION 0
151`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000111
152`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
153`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_POR_VALUE 3'b000
154
155//-------------------------------------------------------
156//----- Variable definitions for register fire_dlc_cru_csr_dmc_pcie_cfg
157//-------------------------------------------------------
158
159`define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_HW_ADDR 27'b000000011001010011000100000
160`define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR 30'b000000011001010011000100000000
161`define FIRE_DLC_CRU_CSR_B_DMC_PCIE_CFG_HW_ADDR 27'b000000011101010011000100000
162`define FIRE_DLC_CRU_CSR_B_DMC_PCIE_CFG_ADDR 30'b000000011101010011000100000000
163
164`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH 64
165`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_DEPTH 1
166`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_SLC 63:0
167`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_INT_SLC 63:0
168`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_POSITION 0
169`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_LOW_ADDR_WIDTH 0
170`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_ADDR_RANGE 26:0
171`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_READ_MASK 64'b0000000000000000000000000000000011111111000000001111111111111111
172`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
173`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WRITE_MASK 64'b0000000000000000000000000000000011111111000000001111111111111111
174`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
175`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
176`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
177`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
178`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_RMASK 64'b0000000000000000000000000000000011111111000000001111111111111111
179`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000111111110000000000000000
180`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
181`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
182`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_INTERNAL_REG 1
183`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_ZERO_TIME_OMNI 1
184`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_NUM_FIELDS 2
185`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_FID 0
186`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_SLC 31:24
187`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_WIDTH 8
188`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_INT_SLC 7:0
189`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_POSITION 24
190`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_FMASK 64'b0000000000000000000000000000000011111111000000000000000000000000
191`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
192`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_POR_VALUE 8'b00000000
193`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_FID 1
194`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_SLC 15:0
195`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_WIDTH 16
196`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_INT_SLC 15:0
197`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_POSITION 0
198`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
199`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
200`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_POR_VALUE 16'b0000000000000000
201
202
203`endif
Full OpenSPARC design & verification tarball including full HDL.