Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_cru_stage_mux_only.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_cru_stage_mux_only.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// 
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// choice is available it will apply instead, Sun elects to use only 
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// ========== Copyright Header End ============================================
module dmu_cru_stage_mux_only 
	(
	clk,
	read_data_0,
	dmc_dbg_sel_a_reg_select_pulse,
	dmc_dbg_sel_a_reg_select_pulse_out,
	dmc_dbg_sel_b_reg_select_pulse,
	dmc_dbg_sel_b_reg_select_pulse_out,
	dmc_pcie_cfg_select_pulse,
	dmc_pcie_cfg_select_pulse_out,
	daemon_csrbus_wr_in,
	daemon_csrbus_wr_out,
	daemon_csrbus_wr_data_in,
	daemon_csrbus_wr_data_out,
	read_data_0_out,
	rst_l,
	rst_l_out
	);

//====================================================
//     Polarity declarations
//====================================================
input  clk;  // Clock signal
input  [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0;  // Read Data
input  dmc_dbg_sel_a_reg_select_pulse;  // select
output dmc_dbg_sel_a_reg_select_pulse_out;  // select
input  dmc_dbg_sel_b_reg_select_pulse;  // select
output dmc_dbg_sel_b_reg_select_pulse_out;  // select
input  dmc_pcie_cfg_select_pulse;  // select
output dmc_pcie_cfg_select_pulse_out;  // select
input  daemon_csrbus_wr_in;  // csrbus_wr
output daemon_csrbus_wr_out;  // csrbus_wr
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in;  // SW write data
output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out;  // SW write
                                                                 // data
output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out;  // Read Data
input  rst_l;  // HW reset
output rst_l_out;  // HW reset

//====================================================
//     Type declarations
//====================================================
wire clk;  // Clock signal
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0;  // Read Data
wire dmc_dbg_sel_a_reg_select_pulse;  // select
wire dmc_dbg_sel_a_reg_select_pulse_out;  // select
wire dmc_dbg_sel_b_reg_select_pulse;  // select
wire dmc_dbg_sel_b_reg_select_pulse_out;  // select
wire dmc_pcie_cfg_select_pulse;  // select
wire dmc_pcie_cfg_select_pulse_out;  // select
wire daemon_csrbus_wr_in;  // csrbus_wr
wire daemon_csrbus_wr_out;  // csrbus_wr
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in;  // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out;  // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out;  // Read Data
wire rst_l;  // HW reset
wire rst_l_out;  // HW reset


//====================================================
//     Assignments only
//====================================================
assign dmc_dbg_sel_a_reg_select_pulse_out = dmc_dbg_sel_a_reg_select_pulse;
assign dmc_dbg_sel_b_reg_select_pulse_out = dmc_dbg_sel_b_reg_select_pulse;
assign dmc_pcie_cfg_select_pulse_out = dmc_pcie_cfg_select_pulse;
assign rst_l_out = rst_l;
assign daemon_csrbus_wr_out      = daemon_csrbus_wr_in;
assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in;


//=====================================================
//      OUTPUT: read_data_out
//=====================================================
dmu_cru_csrpipe_5 dmu_cru_csrpipe_5_inst_1
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.reg_in	(1'b0),
	.reg_out	(1'b0),
	.data0	(read_data_0),
	.sel0	(1'b1),
	.data1	(64'b0),
	.sel1	(1'b1),
	.data2	(64'b0),
	.sel2	(1'b1),
	.data3	(64'b0),
	.sel3	(1'b1),
	.data4	(64'b0),
	.sel4	(1'b1),
	.out	(read_data_0_out)
	);

endmodule // dmu_cru_stage_mux_only