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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_diu.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_diu | |
36 | ( | |
37 | // Control Signals | |
38 | l2clk, | |
39 | clk, | |
40 | rst_l, | |
41 | scan_in, | |
42 | tcu_array_bypass, | |
43 | tcu_scan_en, | |
44 | tcu_se_scancollar_in, | |
45 | tcu_array_wr_inhibit, | |
46 | tcu_pce_ov, | |
47 | tcu_aclk, | |
48 | tcu_bclk, | |
49 | scan_out, | |
50 | ||
51 | // TMU's DIM - DIU Interface | |
52 | tm2di_wr, | |
53 | tm2di_addr, | |
54 | tm2di_data, | |
55 | tm2di_bmask, | |
56 | tm2di_dpar, | |
57 | ||
58 | // IMU's DMS - DIU Interface | |
59 | im2di_wr, | |
60 | im2di_addr, | |
61 | im2di_data, | |
62 | im2di_bmask, | |
63 | im2di_dpar, | |
64 | ||
65 | // CLU's CTM - DIU Interface | |
66 | // CLU's CTM - DIU | |
67 | cl2di_addr, | |
68 | cl2di_rd_en, | |
69 | ||
70 | // DIU - CLU's CTM Interface | |
71 | di2cl_data, | |
72 | di2cl_dpar, | |
73 | di2cl_bmask, | |
74 | ||
75 | dmu_diu_read_data, | |
76 | dmu_mb0_run, | |
77 | dmu_mb0_addr, | |
78 | dmu_mb0_wdata, | |
79 | dmu_mb0_diu_wr_en, | |
80 | dmu_mb0_diu_rd_en | |
81 | ||
82 | ); | |
83 | ||
84 | ////////////////////////////////////////////////////////////////////// | |
85 | //************************* Parameters ************************* | |
86 | ////////////////////////////////////////////////////////////////////// | |
87 | ||
88 | parameter MEM_WIDTH = `FIRE_DLC_CRD_DATA_WDTH+`FIRE_DLC_CRD_BMASK_WDTH+`FIRE_DLC_CRD_DPAR_WDTH; | |
89 | ||
90 | ////////////////////////////////////////////////////////////////////// | |
91 | //************************* Port Declarations ******************* | |
92 | ////////////////////////////////////////////////////////////////////// | |
93 | ||
94 | // Control signals | |
95 | ||
96 | input l2clk; | |
97 | input clk; | |
98 | input rst_l; | |
99 | input scan_in; | |
100 | input tcu_array_bypass; | |
101 | input tcu_scan_en; | |
102 | input tcu_se_scancollar_in; | |
103 | input tcu_array_wr_inhibit; | |
104 | input tcu_pce_ov; | |
105 | input tcu_aclk; | |
106 | input tcu_bclk; | |
107 | output scan_out; | |
108 | ||
109 | // TMU's DIM - DIU Interface | |
110 | input tm2di_wr; | |
111 | input [`FIRE_DLC_TRD_ADDR_WDTH-1:0] tm2di_addr; // Address width, to address 128 entries DMA / 64 entries PIO 1 bit select | |
112 | input [`FIRE_DLC_TRD_DATA_WDTH-1:0] tm2di_data; // Data width, 16 bytes | |
113 | input [`FIRE_DLC_TRD_BMASK_WDTH-1:0] tm2di_bmask; // 16 bit bmask | |
114 | input [`FIRE_DLC_TRD_DPAR_WDTH-1:0] tm2di_dpar; // Parity width 32 bit parity on data 1 bit for 16 bit bmask | |
115 | ||
116 | // IMU's DMS - DIU Interface | |
117 | input im2di_wr; | |
118 | input [`FIRE_DLC_IRD_ADDR_WDTH-1:0] im2di_addr; // Address width, to address 16 entries | |
119 | input [`FIRE_DLC_IRD_DATA_WDTH-1:0] im2di_data; // Data width, 16 bytes | |
120 | input [`FIRE_DLC_IRD_BMASK_WDTH-1:0] im2di_bmask; // 16 bit bmask | |
121 | input [`FIRE_DLC_IRD_DPAR_WDTH-1:0] im2di_dpar; // Parity width 32 bit parity on data 1 bit for 16 bit bmask | |
122 | ||
123 | // CLU's CTM - DIU Interface | |
124 | // CLU's CTM - DIU | |
125 | input [`FIRE_DLC_CRD_ADDR_WDTH-1:0] cl2di_addr; // Address width, to address 128 entries DMA / 64 entries PIO / 16 entries INT 2 bit select | |
126 | input cl2di_rd_en; // BP 5-12-05 n2 rd enable to diu ram for power savings | |
127 | ||
128 | // DIU - CLU's CTM | |
129 | output [`FIRE_DLC_CRD_DATA_WDTH-1:0] di2cl_data; // Data with, 16 bytes | |
130 | output [`FIRE_DLC_CRD_DPAR_WDTH-1:0] di2cl_dpar; // Parity width 32 bit parity on data 1 bit for 16 bit bmask | |
131 | output [`FIRE_DLC_CRD_BMASK_WDTH-1:0] di2cl_bmask; // 16 bit bmask | |
132 | ||
133 | // MEMBIST signals | |
134 | output [MEM_WIDTH-1:0] dmu_diu_read_data; | |
135 | input dmu_mb0_run; | |
136 | input [7:0] dmu_mb0_addr; | |
137 | input [7:0] dmu_mb0_wdata; | |
138 | input dmu_mb0_diu_wr_en; | |
139 | input dmu_mb0_diu_rd_en; | |
140 | ||
141 | ////////////////////////////////////////////////////////////////////// | |
142 | //************************* Wires and Regs ********************** | |
143 | ////////////////////////////////////////////////////////////////////// | |
144 | ||
145 | // flops | |
146 | reg data_sel; | |
147 | reg [MEM_WIDTH-1:0] idm2mux_int_data_out; | |
148 | ||
149 | // non flops | |
150 | reg [MEM_WIDTH-1:0] di2cl_data_out; | |
151 | wire [MEM_WIDTH-1:0] idr2mux_dma_pio_data_out; | |
152 | wire [MEM_WIDTH-1:0] n_idm2mux_int_data_out; | |
153 | ||
154 | ||
155 | ////////////////////////////////////////////////////////////////////// | |
156 | //*************** Submodule Instantiations *********************** | |
157 | ////////////////////////////////////////////////////////////////////// | |
158 | ||
159 | // PIO / DMA data RAM | |
160 | assign dmu_diu_read_data = idr2mux_dma_pio_data_out; | |
161 | ||
162 | dmu_diu_idr idr | |
163 | ( | |
164 | // Control Signals | |
165 | .l2clk (l2clk), | |
166 | .clk (clk), | |
167 | .scan_in (scan_in), | |
168 | .tcu_array_bypass (tcu_array_bypass), | |
169 | .tcu_scan_en (tcu_scan_en), | |
170 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
171 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
172 | .tcu_pce_ov (tcu_pce_ov), | |
173 | .tcu_aclk (tcu_aclk), | |
174 | .tcu_bclk (tcu_bclk), | |
175 | .scan_out (scan_out), | |
176 | ||
177 | // TMU's DIM - DIU to PDR Interface | |
178 | .tm2di_wr (tm2di_wr), | |
179 | .tm2di_addr (tm2di_addr), | |
180 | .tm2di_data (tm2di_data), | |
181 | .tm2di_bmask (tm2di_bmask), | |
182 | .tm2di_dpar (tm2di_dpar), | |
183 | ||
184 | // CLU's CTM - DIU to PDR Interface | |
185 | // CLU's CTM - PDR | |
186 | .cl2idr_addr (cl2di_addr[7:0]), | |
187 | .cl2di_rd_en (cl2di_rd_en), | |
188 | ||
189 | // PDR - Mux | |
190 | .idr2mux_dma_pio_data_out (idr2mux_dma_pio_data_out), | |
191 | .dmu_mb0_run (dmu_mb0_run), | |
192 | .dmu_mb0_addr (dmu_mb0_addr), | |
193 | .dmu_mb0_wdata (dmu_mb0_wdata), | |
194 | .dmu_mb0_diu_wr_en (dmu_mb0_diu_wr_en), | |
195 | .dmu_mb0_diu_rd_en (dmu_mb0_diu_rd_en) | |
196 | ); | |
197 | ||
198 | // Interupt data memory | |
199 | ||
200 | dmu_diu_idm idm | |
201 | ( | |
202 | // Control Signals | |
203 | .clk (clk), | |
204 | .rst_l (rst_l), | |
205 | ||
206 | // IMU's DMS - DIU Interface | |
207 | .im2di_wr (im2di_wr), | |
208 | .im2di_addr (im2di_addr), | |
209 | .im2di_data (im2di_data), | |
210 | .im2di_bmask (im2di_bmask), | |
211 | .im2di_dpar (im2di_dpar), | |
212 | ||
213 | // CLU's CTM - DIU to PDR Interface | |
214 | // CLU's CTM - PDR | |
215 | .cl2idm_addr (cl2di_addr[5:2]), | |
216 | ||
217 | // IDM - Mux | |
218 | .n_idm2mux_int_data_out (n_idm2mux_int_data_out) | |
219 | ); | |
220 | ||
221 | ////////////////////////////////////////////////////////////////////// | |
222 | // ******** Combinational Logic ************************************ | |
223 | ////////////////////////////////////////////////////////////////////// | |
224 | ||
225 | assign di2cl_data = di2cl_data_out[`FIRE_DLC_CRD_DATA_WDTH-1:0]; | |
226 | assign di2cl_bmask = di2cl_data_out[`FIRE_DLC_CRD_DATA_WDTH+`FIRE_DLC_CRD_BMASK_WDTH-1:`FIRE_DLC_CRD_DATA_WDTH]; | |
227 | assign di2cl_dpar = di2cl_data_out[MEM_WIDTH-1:`FIRE_DLC_CRD_DATA_WDTH+`FIRE_DLC_CRD_BMASK_WDTH]; | |
228 | ||
229 | // 0in mux -in idr2mux_dma_pio_data_out idm2mux_int_data_out -out di2cl_data_out -select data_sel -binary | |
230 | ||
231 | // decode logic for reads mux to select ram data for PIO/DMA or INT data from flops | |
232 | ||
233 | always @(data_sel or idr2mux_dma_pio_data_out or idm2mux_int_data_out) | |
234 | begin | |
235 | if (data_sel == 0) | |
236 | di2cl_data_out = idr2mux_dma_pio_data_out; | |
237 | else | |
238 | di2cl_data_out = idm2mux_int_data_out; | |
239 | end | |
240 | ||
241 | ////////////////////////////////////////////////////////////////////// | |
242 | // *********** Sequential Logic ************************************ | |
243 | ////////////////////////////////////////////////////////////////////// | |
244 | ||
245 | always @(posedge clk) | |
246 | if(~rst_l) begin | |
247 | data_sel <= 1'b0; | |
248 | end | |
249 | else begin | |
250 | data_sel <= cl2di_addr[8]; | |
251 | end | |
252 | ||
253 | always @(posedge clk) | |
254 | if(~rst_l) begin | |
255 | idm2mux_int_data_out <= {MEM_WIDTH{1'b0}}; | |
256 | end | |
257 | else begin | |
258 | idm2mux_int_data_out <= n_idm2mux_int_data_out; | |
259 | end | |
260 | ||
261 | endmodule // dmu_diu |