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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_diu_idm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_diu_idm | |
36 | ( | |
37 | // Control Signals | |
38 | clk, | |
39 | rst_l, | |
40 | ||
41 | // IMU's DMS - DIU's IDM Interface | |
42 | im2di_wr, | |
43 | im2di_addr, | |
44 | im2di_data, | |
45 | im2di_bmask, | |
46 | im2di_dpar, | |
47 | ||
48 | ||
49 | // CLU's CTM - DIU's IDM Interface | |
50 | // CLU's CTM - PDR | |
51 | cl2idm_addr, | |
52 | ||
53 | // DIU's IDM - DIU's Mux | |
54 | ||
55 | n_idm2mux_int_data_out | |
56 | ); | |
57 | ||
58 | ||
59 | ////////////////////////////////////////////////////////////////////// | |
60 | //************************* Parameters ************************* | |
61 | ////////////////////////////////////////////////////////////////////// | |
62 | ||
63 | parameter MEM_WIDTH = `FIRE_DLC_IRD_DATA_WDTH+`FIRE_DLC_IRD_BMASK_WDTH+`FIRE_DLC_IRD_DPAR_WDTH; | |
64 | parameter INT_NUM = 16; | |
65 | ||
66 | ////////////////////////////////////////////////////////////////////// | |
67 | //************************* Port Declarations ******************* | |
68 | ////////////////////////////////////////////////////////////////////// | |
69 | ||
70 | // Control signals | |
71 | input clk; | |
72 | input rst_l; | |
73 | ||
74 | // IMU's DMS - DIU's IDM Interface | |
75 | input im2di_wr; | |
76 | input [`FIRE_DLC_IRD_ADDR_WDTH-1:0] im2di_addr; // Address width, to address 16 entries | |
77 | input [`FIRE_DLC_IRD_DATA_WDTH-1:0] im2di_data; // Data width, 16 bytes | |
78 | input [`FIRE_DLC_IRD_BMASK_WDTH-1:0] im2di_bmask; // 16 bit bmask | |
79 | input [`FIRE_DLC_IRD_DPAR_WDTH-1:0] im2di_dpar; // Parity width 32 bit parity (4bits) on data 1 bit for 16 bit bmask | |
80 | ||
81 | // CLU's CTM - DIU Interface | |
82 | // CLU's CTM - DIU | |
83 | input [`FIRE_DLC_IRD_ADDR_WDTH-1:0] cl2idm_addr; // Address width, to access 16 entries INT | |
84 | ||
85 | // DIU's IDM - DIU's Mux | |
86 | output [MEM_WIDTH-1:0] n_idm2mux_int_data_out; | |
87 | ||
88 | ////////////////////////////////////////////////////////////////////// | |
89 | //************************* Wires and Regs ********************** | |
90 | ////////////////////////////////////////////////////////////////////// | |
91 | ||
92 | // registers that are flops | |
93 | ||
94 | reg [MEM_WIDTH-1:0] int_data[0:INT_NUM-1]; | |
95 | ||
96 | ////////////////////////////////////////////////////////////////////// | |
97 | // ******** Combinational Logic ************************************ | |
98 | ////////////////////////////////////////////////////////////////////// | |
99 | ||
100 | /* #0in memory_access -read_addr cl2idm_addr -read (!im2di_wr) -write_addr im2di_addr -write im2di_wr | |
101 | -single_write -read_data idm2mux_int_data_out -write_data ({im2di_dpar, im2di_bmask, im2di_data}) */ | |
102 | ||
103 | // Checks that any data written on waddr is read on raddr before it is overwritten. In | |
104 | // addition, it checks that the data read from the memory is correct. Also checks that | |
105 | // no location is read by raddr and written by waddr in the same cycle. | |
106 | ||
107 | assign n_idm2mux_int_data_out = int_data[cl2idm_addr]; | |
108 | ||
109 | ////////////////////////////////////////////////////////////////////// | |
110 | // *********** Sequential Logic ************************************ | |
111 | ////////////////////////////////////////////////////////////////////// | |
112 | ||
113 | always @ (posedge clk) | |
114 | if(~rst_l) begin : int_data_rst | |
115 | integer j; | |
116 | for (j = 0; j < INT_NUM; j = j + 1) begin | |
117 | int_data[j] <= {MEM_WIDTH{1'b0}}; | |
118 | end | |
119 | end | |
120 | else begin | |
121 | if(im2di_wr) | |
122 | int_data[im2di_addr] <= ({im2di_dpar, im2di_bmask, im2di_data}); | |
123 | end | |
124 | ||
125 | endmodule // dmu_diu_idm |