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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_diu_idr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_diu_idr | |
36 | ( | |
37 | // Control Signals | |
38 | l2clk, | |
39 | clk, | |
40 | scan_in, | |
41 | tcu_array_bypass, | |
42 | tcu_scan_en, | |
43 | tcu_se_scancollar_in, | |
44 | tcu_array_wr_inhibit, | |
45 | tcu_pce_ov, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | scan_out, | |
49 | ||
50 | // TMU's DIM - DIU Interface | |
51 | tm2di_wr, | |
52 | tm2di_addr, | |
53 | tm2di_data, | |
54 | tm2di_bmask, | |
55 | tm2di_dpar, | |
56 | ||
57 | // CLU's CTM - DIU Interface | |
58 | // CLU's CTM - DIU | |
59 | cl2idr_addr, | |
60 | cl2di_rd_en, | |
61 | ||
62 | // DIU's IDR - DIU's Mux | |
63 | idr2mux_dma_pio_data_out, | |
64 | ||
65 | dmu_mb0_run, | |
66 | dmu_mb0_addr, | |
67 | dmu_mb0_wdata, | |
68 | dmu_mb0_diu_wr_en, | |
69 | dmu_mb0_diu_rd_en | |
70 | ); | |
71 | ||
72 | ////////////////////////////////////////////////////////////////////// | |
73 | //************************* Parameters ************************* | |
74 | ////////////////////////////////////////////////////////////////////// | |
75 | ||
76 | parameter MEM_WIDTH = `FIRE_DLC_TRD_DATA_WDTH+`FIRE_DLC_TRD_BMASK_WDTH+`FIRE_DLC_TRD_DPAR_WDTH; | |
77 | // parameter MEM_TIEHIGH = 1'b1; | |
78 | // parameter MEM_TIELOW = 1'b0; | |
79 | ||
80 | ////////////////////////////////////////////////////////////////////// | |
81 | //************************* Port Declarations ******************* | |
82 | ////////////////////////////////////////////////////////////////////// | |
83 | ||
84 | // Control signals | |
85 | input l2clk; | |
86 | input clk; | |
87 | input scan_in; | |
88 | input tcu_array_bypass; | |
89 | input tcu_scan_en; | |
90 | input tcu_se_scancollar_in; | |
91 | input tcu_array_wr_inhibit; | |
92 | input tcu_pce_ov; | |
93 | input tcu_aclk; | |
94 | input tcu_bclk; | |
95 | output scan_out; | |
96 | ||
97 | // TMU's DIM - DIU Interface | |
98 | input tm2di_wr; | |
99 | input [`FIRE_DLC_TRD_ADDR_WDTH-1:0] tm2di_addr; // Address width, to address 128 entries DMA / 64 entries PIO 1 bit select | |
100 | input [`FIRE_DLC_TRD_DATA_WDTH-1:0] tm2di_data; // Data width, 16 bytes | |
101 | input [`FIRE_DLC_TRD_BMASK_WDTH-1:0] tm2di_bmask; // 16 bit bmask | |
102 | input [`FIRE_DLC_TRD_DPAR_WDTH-1:0] tm2di_dpar; // Parity width 32 bit parity on data 1 bit for 16 bit bmask | |
103 | ||
104 | // CLU's CTM - DIU Interface | |
105 | // CLU's CTM - DIU | |
106 | input [`FIRE_DLC_CRD_ADDR_WDTH-2:0] cl2idr_addr; // Address width, to address 128 entries DMA / 64 entries PIO / 16 entries INT 2 bit select | |
107 | input cl2di_rd_en; // rd enable for diu ram for n2 power savings BP 5-12-05 | |
108 | ||
109 | // DIU's PDR - CLU's CTM (128 + 16 + 5 = 149) | |
110 | output [MEM_WIDTH-1:0] idr2mux_dma_pio_data_out; // RAM data output | |
111 | ||
112 | // MBIST signals | |
113 | input dmu_mb0_run; | |
114 | ||
115 | input [7:0] dmu_mb0_addr; | |
116 | input [7:0] dmu_mb0_wdata; | |
117 | input dmu_mb0_diu_wr_en; | |
118 | input dmu_mb0_diu_rd_en; | |
119 | ||
120 | ////////////////////////////////////////////////////////////////////// | |
121 | //*************** Submodule Instantiations *********************** | |
122 | ////////////////////////////////////////////////////////////////////// | |
123 | ||
124 | /* #0in memory_access -read_addr cl2idr_addr -read (!tm2di_wr) -write_addr tm2di_addr -write tm2di_wr | |
125 | -single_write -read_data idr2mux_dma_pio_data_out -write_data ({tm2di_dpar, tm2di_bmask, tm2di_data}) */ | |
126 | ||
127 | // Checks that any data written on waddr is read on raddr before it is overwritten. In | |
128 | // addition, it checks that the data read from the memory is correct. Also checks that | |
129 | // no location is read by raddr and written by waddr in the same cycle. | |
130 | /* | |
131 | fire_dlc_ram192x149_211hd4 ram192x149_211hd4 | |
132 | ( | |
133 | // address ports | |
134 | .aadr (cl2idr_addr), | |
135 | .badr (tm2di_addr), | |
136 | ||
137 | // clock ports | |
138 | .clka (l2clk), | |
139 | .clkb (l2clk), | |
140 | ||
141 | // data input ports | |
142 | .dib ({tm2di_dpar, tm2di_bmask, tm2di_data}), | |
143 | ||
144 | ||
145 | // data output ports | |
146 | ||
147 | .doa (idr2mux_dma_pio_data_out), | |
148 | ||
149 | // port enables | |
150 | .ena (MEM_TIEHIGH), | |
151 | .enb (MEM_TIEHIGH), | |
152 | ||
153 | // write enables | |
154 | .web (tm2di_wr) | |
155 | ); | |
156 | */ | |
157 | //BP N2 9-21-04 add the scan bypass mux | |
158 | // note: that {tm2di_dpar, tm2di_bmask, tm2di_data} come directly from flops in dmu_tmu_dim_datapath.v | |
159 | wire [MEM_WIDTH-1:0] dma_pio_data_out; | |
160 | assign idr2mux_dma_pio_data_out = tcu_array_bypass ? {tm2di_dpar, tm2di_bmask, tm2di_data} : dma_pio_data_out; | |
161 | ||
162 | //SV 02/24/05 added BIST logic | |
163 | wire [148:0] din_ram ; | |
164 | wire [7:0] rd_addr_ram, wr_addr_ram ; | |
165 | wire wr_en_ram, rd_en_ram ; | |
166 | ||
167 | assign din_ram = dmu_mb0_run ? ({dmu_mb0_wdata[4:0],{18{dmu_mb0_wdata}}}) : ({tm2di_dpar, tm2di_bmask, tm2di_data}) ; | |
168 | assign rd_addr_ram = dmu_mb0_run ? dmu_mb0_addr[7:0] : cl2idr_addr ; | |
169 | assign wr_addr_ram = dmu_mb0_run ? dmu_mb0_addr[7:0] : tm2di_addr ; | |
170 | assign wr_en_ram = dmu_mb0_run ? dmu_mb0_diu_wr_en : tm2di_wr ; | |
171 | assign rd_en_ram = dmu_mb0_run ? dmu_mb0_diu_rd_en : cl2di_rd_en ; | |
172 | ||
173 | ||
174 | //BP n2 6-16-04 new ram model | |
175 | ||
176 | // /* 0in memory_access -read_addr cl2idr_addr -read (cl2idr_addr != tm2di_addr) | |
177 | /* 0in memory_access -read_addr cl2idr_addr -read (cl2di_rd_en & (cl2idr_addr != tm2di_addr) ) | |
178 | -write_addr tm2di_addr | |
179 | -latency 1 -write tm2di_wr | |
180 | -read_data dma_pio_data_out -write_data ({tm2di_dpar, tm2di_bmask, tm2di_data}) -group mbist_mode */ | |
181 | ||
182 | // Checks that any data written on waddr is read on raddr before it is overwritten. In | |
183 | // addition, it checks that the data read from the memory is correct. Also checks that | |
184 | // no location is read by raddr and written by waddr in the same cycle. | |
185 | n2_dmu_dp_144x149s_cust diu_dma_ram144x149 | |
186 | ( | |
187 | // address ports | |
188 | .rd_addr (rd_addr_ram), | |
189 | .wr_addr (wr_addr_ram), | |
190 | ||
191 | // clock ports | |
192 | .clk (l2clk), | |
193 | ||
194 | // data input ports | |
195 | .din (din_ram), | |
196 | ||
197 | // data output ports | |
198 | .dout (dma_pio_data_out), | |
199 | ||
200 | // port enables | |
201 | .rd_en (rd_en_ram), | |
202 | .wr_en (wr_en_ram), | |
203 | ||
204 | ||
205 | // scan ports | |
206 | .scan_in (scan_in), | |
207 | .tcu_scan_en (tcu_scan_en), | |
208 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
209 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
210 | .tcu_pce_ov (tcu_pce_ov), | |
211 | .pce (1'b1), | |
212 | .tcu_aclk (tcu_aclk), | |
213 | .tcu_bclk (tcu_bclk), | |
214 | .scan_out (scan_out) | |
215 | ); | |
216 | ||
217 | ||
218 | endmodule // dmu_diu_idr |