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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_dou.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_dou | |
36 | ( | |
37 | // Control Signals | |
38 | l2clk, | |
39 | clk, | |
40 | rst_l, | |
41 | scan_in, | |
42 | tcu_array_bypass, | |
43 | tcu_scan_en, | |
44 | tcu_se_scancollar_in, | |
45 | tcu_se_scancollar_out, | |
46 | tcu_array_wr_inhibit, | |
47 | tcu_pce_ov, | |
48 | tcu_aclk, | |
49 | tcu_bclk, | |
50 | scan_out, | |
51 | ||
52 | // CLU's CRM - DOU's DMA Interface | |
53 | cl2do_dma_wr, | |
54 | cl2do_dma_addr, | |
55 | cl2do_dma_data, | |
56 | cl2do_dma_dpar, | |
57 | ||
58 | // CLU's CRM - DOU's PIO Interface | |
59 | cl2do_pio_wr, | |
60 | cl2do_pio_addr, | |
61 | cl2do_pio_data, | |
62 | cl2do_pio_dpar, | |
63 | ||
64 | // ILU's EIL - DOU Interface | |
65 | // ILU's EIL - DOU | |
66 | y2k_buf_addr, | |
67 | ||
68 | // DOU - ILU's EIL | |
69 | k2y_buf_data, | |
70 | k2y_buf_dpar, | |
71 | ||
72 | // MBIST signals | |
73 | dmu_mb0_run, | |
74 | dmu_mb0_addr, | |
75 | dmu_mb0_wdata, | |
76 | dmu_mb0_dou_dma_data_wr_en, | |
77 | dmu_mb0_dou_dma_data_rd_en, | |
78 | dmu_mb0_dou_pio_data_wr_en, | |
79 | dmu_mb0_dou_pio_data_rd_en, | |
80 | dmu_dou_pio_read_data, | |
81 | dmu_dou_dma_read_data | |
82 | ||
83 | ); | |
84 | ||
85 | ////////////////////////////////////////////////////////////////////// | |
86 | //************************* Parameters ************************* | |
87 | ////////////////////////////////////////////////////////////////////// | |
88 | ||
89 | parameter MEM_WIDTH = `FIRE_DLC_ERD_DATA_WDTH+`FIRE_DLC_ERD_DPAR_WDTH; | |
90 | ||
91 | ////////////////////////////////////////////////////////////////////// | |
92 | //************************* Port Declarations ******************* | |
93 | ////////////////////////////////////////////////////////////////////// | |
94 | ||
95 | // Control signals | |
96 | input l2clk; // clock to rams only, since they already have headers | |
97 | input clk; | |
98 | input rst_l; | |
99 | input scan_in; | |
100 | input tcu_array_bypass; | |
101 | input tcu_scan_en; | |
102 | input tcu_se_scancollar_in; | |
103 | input tcu_se_scancollar_out; | |
104 | input tcu_array_wr_inhibit; | |
105 | input tcu_pce_ov; | |
106 | input tcu_aclk; | |
107 | input tcu_bclk; | |
108 | output scan_out; | |
109 | ||
110 | // CLU's CRM - DOU's EDR DMA Interface | |
111 | input cl2do_dma_wr; | |
112 | input [`FIRE_DLC_CDD_ADDR_WDTH-1:0] cl2do_dma_addr; // Address width, to address 128 entries DMA | |
113 | input [`FIRE_DLC_CDD_DATA_WDTH-1:0] cl2do_dma_data; // Data width, 16 bytes | |
114 | input [`FIRE_DLC_CDD_DPAR_WDTH-1:0] cl2do_dma_dpar; // Parity width 32 bit parity on data | |
115 | ||
116 | // CLU's CRM - DOU's EPR PIO Interface | |
117 | input cl2do_pio_wr; | |
118 | input [`FIRE_DLC_CPD_ADDR_WDTH-1:0] cl2do_pio_addr; // Address width, to address 64 entries PIO | |
119 | input [`FIRE_DLC_CPD_DATA_WDTH-1:0] cl2do_pio_data; // Data width, 16 bytes | |
120 | input [`FIRE_DLC_CPD_DPAR_WDTH-1:0] cl2do_pio_dpar; // Parity width 32 bit parity on data | |
121 | ||
122 | // ILU's EIL - DOU Interface | |
123 | input [`FIRE_DLC_ERD_ADDR_WDTH-1:0] y2k_buf_addr; // Address width, to address 128 entries DMA / 64 entries PIO | |
124 | ||
125 | output [`FIRE_DLC_ERD_DATA_WDTH-1:0] k2y_buf_data; // Data width, 16 bytes | |
126 | output [`FIRE_DLC_ERD_DPAR_WDTH-1:0] k2y_buf_dpar; // Parity width 32 bit parity on data | |
127 | ||
128 | output [MEM_WIDTH-1:0] dmu_dou_pio_read_data; | |
129 | output [MEM_WIDTH-1:0] dmu_dou_dma_read_data; | |
130 | input dmu_mb0_run; | |
131 | input [7:0] dmu_mb0_addr; | |
132 | input [7:0] dmu_mb0_wdata; | |
133 | input dmu_mb0_dou_pio_data_wr_en; | |
134 | input dmu_mb0_dou_pio_data_rd_en; | |
135 | input dmu_mb0_dou_dma_data_wr_en; | |
136 | input dmu_mb0_dou_dma_data_rd_en; | |
137 | ||
138 | ////////////////////////////////////////////////////////////////////// | |
139 | //************************* Wires and Regs ********************** | |
140 | ////////////////////////////////////////////////////////////////////// | |
141 | ||
142 | // flops | |
143 | reg data_sel; | |
144 | ||
145 | // non flops | |
146 | reg [MEM_WIDTH-1:0] k2y_data_out; | |
147 | wire [MEM_WIDTH-1:0] edr2mux_dma_data_out; | |
148 | wire [MEM_WIDTH-1:0] epr2mux_pio_data_out; | |
149 | ||
150 | ||
151 | ////////////////////////////////////////////////////////////////////// | |
152 | //*************** Submodule Instantiations *********************** | |
153 | ////////////////////////////////////////////////////////////////////// | |
154 | ||
155 | assign dmu_dou_pio_read_data = epr2mux_pio_data_out; | |
156 | assign dmu_dou_dma_read_data = edr2mux_dma_data_out; | |
157 | // DMA data RAM | |
158 | ||
159 | dmu_dou_edr edr | |
160 | ( | |
161 | // Control Signals | |
162 | .l2clk (l2clk), | |
163 | .clk (clk), | |
164 | .scan_in (scan_in), | |
165 | .tcu_array_bypass (tcu_array_bypass), | |
166 | .tcu_scan_en (tcu_scan_en), | |
167 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
168 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
169 | .tcu_pce_ov (tcu_pce_ov), | |
170 | .tcu_aclk (tcu_aclk), | |
171 | .tcu_bclk (tcu_bclk), | |
172 | .scan_out (scan_out), | |
173 | ||
174 | // CLU's CRM - DOU's EDR DMA Interface | |
175 | .cl2do_dma_wr (cl2do_dma_wr), | |
176 | .cl2do_dma_addr (cl2do_dma_addr), | |
177 | .cl2do_dma_data (cl2do_dma_data), | |
178 | .cl2do_dma_dpar (cl2do_dma_dpar), | |
179 | ||
180 | // ILU's EIL - DOU Interface | |
181 | // ILU's EIL - DOU | |
182 | .y2edr_addr (y2k_buf_addr[6:0]), | |
183 | ||
184 | // EDR - Mux | |
185 | .edr2mux_dma_data_out (edr2mux_dma_data_out), | |
186 | ||
187 | .dmu_mb0_run (dmu_mb0_run), | |
188 | .dmu_mb0_addr (dmu_mb0_addr[6:0]), | |
189 | .dmu_mb0_wdata (dmu_mb0_wdata), | |
190 | .dmu_mb0_dou_dma_data_wr_en (dmu_mb0_dou_dma_data_wr_en), | |
191 | .dmu_mb0_dou_dma_data_rd_en (dmu_mb0_dou_dma_data_rd_en) | |
192 | ||
193 | ); | |
194 | ||
195 | // PIO data RAM | |
196 | ||
197 | dmu_dou_epr epr | |
198 | ( | |
199 | // Control Signals | |
200 | .l2clk (l2clk), | |
201 | .clk (clk), | |
202 | .scan_in (scan_in), | |
203 | .tcu_array_bypass (tcu_array_bypass), | |
204 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
205 | .tcu_se_scancollar_out (tcu_se_scancollar_out), | |
206 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
207 | .tcu_pce_ov (tcu_pce_ov), | |
208 | .tcu_aclk (tcu_aclk), | |
209 | .tcu_bclk (tcu_bclk), | |
210 | .scan_out (), | |
211 | ||
212 | // CLU's CRM - DOU's PIO Interface | |
213 | .cl2do_pio_wr (cl2do_pio_wr), | |
214 | .cl2do_pio_addr (cl2do_pio_addr), | |
215 | .cl2do_pio_data (cl2do_pio_data), | |
216 | .cl2do_pio_dpar (cl2do_pio_dpar), | |
217 | ||
218 | // ILU's EIL - DOU Interface | |
219 | // ILU's EIL - DOU | |
220 | .y2epr_addr (y2k_buf_addr[5:0]), | |
221 | ||
222 | // EDR - Mux | |
223 | .epr2mux_pio_data_out (epr2mux_pio_data_out), | |
224 | ||
225 | .dmu_mb0_run (dmu_mb0_run), | |
226 | .dmu_mb0_addr (dmu_mb0_addr[3:0]), | |
227 | .dmu_mb0_wdata (dmu_mb0_wdata), | |
228 | .dmu_mb0_dou_pio_data_wr_en (dmu_mb0_dou_pio_data_wr_en), | |
229 | .dmu_mb0_dou_pio_data_rd_en (dmu_mb0_dou_pio_data_rd_en) | |
230 | ); | |
231 | ||
232 | ////////////////////////////////////////////////////////////////////// | |
233 | // ******** Combinational Logic ************************************ | |
234 | ////////////////////////////////////////////////////////////////////// | |
235 | ||
236 | assign k2y_buf_data = k2y_data_out[`FIRE_DLC_ERD_DATA_WDTH-1:0]; | |
237 | assign k2y_buf_dpar = k2y_data_out[MEM_WIDTH-1:`FIRE_DLC_ERD_DATA_WDTH]; | |
238 | ||
239 | // 0in mux -in edr2mux_dma_data_out epr2mux_pio_data_out -out k2y_data_out -select data_sel -binary | |
240 | ||
241 | // decode logic for reads (mux to select data from PIO or DMA ram) | |
242 | ||
243 | always @(data_sel or edr2mux_dma_data_out or epr2mux_pio_data_out) | |
244 | begin | |
245 | if (data_sel == 0) | |
246 | k2y_data_out = edr2mux_dma_data_out; | |
247 | else | |
248 | k2y_data_out = epr2mux_pio_data_out; | |
249 | end | |
250 | ||
251 | always @(posedge clk) | |
252 | if(~rst_l) begin | |
253 | data_sel <= 1'b0; | |
254 | end | |
255 | else begin | |
256 | data_sel <= y2k_buf_addr[7]; | |
257 | end | |
258 | ||
259 | endmodule // dmu_dou | |
260 |