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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_dou_edr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_dou_edr | |
36 | ( | |
37 | // Control Signals | |
38 | l2clk, | |
39 | clk, | |
40 | scan_in, | |
41 | tcu_array_bypass, | |
42 | tcu_scan_en, | |
43 | tcu_se_scancollar_in, | |
44 | tcu_array_wr_inhibit, | |
45 | tcu_pce_ov, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | scan_out, | |
49 | ||
50 | // CLU's CRM - DOU's EDR DMA Interface | |
51 | cl2do_dma_wr, | |
52 | cl2do_dma_addr, | |
53 | cl2do_dma_data, | |
54 | cl2do_dma_dpar, | |
55 | ||
56 | // ILU's EIL - DOU Interface | |
57 | // ILU's EIL - DOU | |
58 | y2edr_addr, | |
59 | ||
60 | // EDR - Mux | |
61 | edr2mux_dma_data_out, | |
62 | ||
63 | dmu_mb0_run, | |
64 | dmu_mb0_addr, | |
65 | dmu_mb0_wdata, | |
66 | dmu_mb0_dou_dma_data_wr_en, | |
67 | dmu_mb0_dou_dma_data_rd_en | |
68 | ||
69 | ||
70 | ); | |
71 | ||
72 | ////////////////////////////////////////////////////////////////////// | |
73 | //************************* Parameters ************************* | |
74 | ////////////////////////////////////////////////////////////////////// | |
75 | ||
76 | parameter MEM_WIDTH = `FIRE_DLC_ERD_DATA_WDTH+`FIRE_DLC_ERD_DPAR_WDTH; | |
77 | parameter MEM_TIEHIGH = 1'b1; | |
78 | // parameter MEM_TIELOW = 1'b0; | |
79 | ||
80 | ||
81 | ////////////////////////////////////////////////////////////////////// | |
82 | //************************* Port Declarations ******************* | |
83 | ////////////////////////////////////////////////////////////////////// | |
84 | ||
85 | // Control signals | |
86 | ||
87 | input l2clk; | |
88 | input clk; | |
89 | input scan_in; | |
90 | input tcu_array_bypass; | |
91 | input tcu_scan_en; | |
92 | input tcu_se_scancollar_in; | |
93 | input tcu_array_wr_inhibit; | |
94 | input tcu_pce_ov; | |
95 | input tcu_aclk; | |
96 | input tcu_bclk; | |
97 | output scan_out; | |
98 | ||
99 | // CLU's CRM - DOU's EDR DMA Interface | |
100 | input cl2do_dma_wr; | |
101 | input [`FIRE_DLC_CDD_ADDR_WDTH-1:0] cl2do_dma_addr; // Address width, to address 128 entries DMA | |
102 | input [`FIRE_DLC_CDD_DATA_WDTH-1:0] cl2do_dma_data; // Data width, 16 bytes | |
103 | input [`FIRE_DLC_CDD_DPAR_WDTH-1:0] cl2do_dma_dpar; // Parity width 32 bit parity on data | |
104 | ||
105 | // ILU's EIL - DOU Interface | |
106 | input [`FIRE_DLC_ERD_ADDR_WDTH-2:0] y2edr_addr; // Address width, to address 128 entries DMA / 64 entries PIO | |
107 | ||
108 | // DOU's EDR - Mux | |
109 | output [MEM_WIDTH-1:0] edr2mux_dma_data_out; // RAM data output | |
110 | ||
111 | // MBIST signals | |
112 | input dmu_mb0_run; | |
113 | ||
114 | input [6:0] dmu_mb0_addr; | |
115 | input [7:0] dmu_mb0_wdata; | |
116 | input dmu_mb0_dou_dma_data_wr_en; | |
117 | input dmu_mb0_dou_dma_data_rd_en; | |
118 | ||
119 | ////////////////////////////////////////////////////////////////////// | |
120 | //*************** Submodule Instantiations *********************** | |
121 | ////////////////////////////////////////////////////////////////////// | |
122 | /* | |
123 | fire_dlc_ram128x132_211hd4 ram128x132_211hd4 | |
124 | ( | |
125 | // address ports | |
126 | .aadr (y2edr_addr), | |
127 | .badr (cl2do_dma_addr), | |
128 | ||
129 | // clock ports | |
130 | .clka (l2clk), | |
131 | .clkb (l2clk), | |
132 | ||
133 | // data input ports | |
134 | .dib ({cl2do_dma_dpar, cl2do_dma_data}), | |
135 | ||
136 | // data output ports | |
137 | .doa (edr2mux_dma_data_out), | |
138 | ||
139 | // port enables | |
140 | .ena (MEM_TIEHIGH), | |
141 | .enb (MEM_TIEHIGH), | |
142 | ||
143 | // write enables | |
144 | .web (cl2do_dma_wr) | |
145 | ); | |
146 | */ | |
147 | ||
148 | //BP n2 6-04-04 new ram model | |
149 | //BP n2 9-22-04, add scan bypass mux | |
150 | // note: {cl2do_dma_dpar, cl2do_dma_data} come directly from flops in clu | |
151 | wire [MEM_WIDTH-1:0] dma_ram_data_out; | |
152 | ||
153 | //SV 02/24/05 added BIST logic | |
154 | wire [131:0] din_ram ; | |
155 | wire [6:0] rd_addr_ram, wr_addr_ram ; | |
156 | wire wr_en_ram, rd_en_ram ; | |
157 | ||
158 | assign din_ram = dmu_mb0_run ? ({dmu_mb0_wdata[3:0],{16{dmu_mb0_wdata}}}) : ({cl2do_dma_dpar, cl2do_dma_data}) ; | |
159 | assign rd_addr_ram = dmu_mb0_run ? dmu_mb0_addr[6:0] : y2edr_addr ; | |
160 | assign wr_addr_ram = dmu_mb0_run ? dmu_mb0_addr[6:0] : cl2do_dma_addr ; | |
161 | assign wr_en_ram = dmu_mb0_run ? dmu_mb0_dou_dma_data_wr_en : cl2do_dma_wr ; | |
162 | assign rd_en_ram = dmu_mb0_run ? dmu_mb0_dou_dma_data_rd_en : MEM_TIEHIGH ; | |
163 | ||
164 | /* 0in memory_access -read_addr y2edr_addr -read (y2edr_addr != cl2do_dma_addr) | |
165 | -write_addr cl2do_dma_addr | |
166 | -latency 1 -write cl2do_dma_wr | |
167 | -read_data dma_ram_data_out -write_data ({cl2do_dma_dpar, cl2do_dma_data}) -group mbist_mode */ | |
168 | ||
169 | assign edr2mux_dma_data_out = tcu_array_bypass ? {cl2do_dma_dpar, cl2do_dma_data} : dma_ram_data_out; | |
170 | ||
171 | n2_dmu_dp_128x132s_cust dou_dma_ram128x132 | |
172 | ( | |
173 | // address ports | |
174 | .rd_addr (rd_addr_ram), | |
175 | .wr_addr (wr_addr_ram), | |
176 | ||
177 | // clock ports | |
178 | .clk (l2clk), | |
179 | ||
180 | // data input ports | |
181 | .din (din_ram), | |
182 | ||
183 | // data output ports | |
184 | .dout (dma_ram_data_out), | |
185 | ||
186 | // port enables | |
187 | .rd_en (rd_en_ram), | |
188 | ||
189 | // write enables | |
190 | .wr_en (wr_en_ram), | |
191 | ||
192 | // scan ports | |
193 | .scan_in (scan_in), | |
194 | .tcu_scan_en (tcu_scan_en), | |
195 | .tcu_se_scancollar_in (tcu_se_scancollar_in), | |
196 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
197 | .tcu_pce_ov (tcu_pce_ov), | |
198 | .pce (1'b1), | |
199 | .tcu_aclk (tcu_aclk), | |
200 | .tcu_bclk (tcu_bclk), | |
201 | .scan_out (scan_out) | |
202 | ); | |
203 | ||
204 | ||
205 | endmodule // dmu_dou_edr | |
206 |