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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_dsn.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_dsn.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
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30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_dsn (
36 // clocks, scan
37 l1clk,
38 rst_l,
39
40 // upstream from DMU TO SIU
41 dmu_sii_hdr_vld,
42 dmu_sii_reqbypass,
43 dmu_sii_datareq,
44 dmu_sii_datareq16,
45 dmu_sii_data,
46 dmu_sii_parity,
47 dmu_sii_be_parity,
48 dmu_sii_be,
49
50 // downstream from SIU TO DMU
51 sio_dmu_hdr_vld,
52
53 sii_dmu_wrack_tag,
54 sii_dmu_wrack_par,
55 sii_dmu_wrack_vld,
56 sio_dmu_data,
57 sio_dmu_parity,
58
59 // ========== NCU CSR ==========
60 // downstream
61 dmu_ncu_stall,
62 ncu_dmu_vld,
63 ncu_dmu_data,
64 // upstream
65 ncu_dmu_stall,
66 dmu_ncu_vld,
67 dmu_ncu_data,
68 // ========== NCU CSR ==========
69
70 // ========== DMU RING ==========
71 // PCI-ex CSR ring
72 j2d_csr_ring_out,
73 d2j_csr_ring_in,
74
75 // ========== DMU RING ==========
76
77
78 // ========== DMU PIO ==========
79 // downstream
80 ncu_dmu_pio_hdr_vld,
81 ncu_dmu_mmu_addr_vld,
82 ncu_dmu_pio_data,
83 ncu_dmu_d_pei, // n2 RAS
84 ncu_dmu_siicr_pei, // n2 RAS
85 ncu_dmu_ctag_uei, // n2 RAS
86 ncu_dmu_ctag_cei, // n2 RAS
87 ncu_dmu_ncucr_pei, // n2 RAS
88 ncu_dmu_iei, // n2 RAS
89 dmu_ncu_wrack_vld,
90 dmu_ncu_wrack_tag,
91 dmu_ncu_wrack_par,
92 dmu_ncu_d_pe, // n2 RAS
93 dmu_ncu_siicr_pe, // n2 RAS
94 dmu_ncu_ctag_ue, // n2 RAS
95 dmu_ncu_ctag_ce, // n2 RAS
96 dmu_ncu_ncucr_pe, // n2 RAS
97 dmu_ncu_ie, // n2 RAS
98 // ========== DMU PIO ==========
99
100 // ========== DMU Mondo ==========
101 ncu_dmu_mondo_ack,
102 ncu_dmu_mondo_nack,
103 ncu_dmu_mondo_id,
104 ncu_dmu_mondo_id_par,
105 // ========== DMU Mondo ==========
106
107 // ========== DMU/DSN command port ==========
108 d2j_cmd,
109 d2j_addr,
110 d2j_ctag,
111 d2j_cmd_vld,
112 // ========== DMU/DSN command port==========
113
114 // ========== DMU/DSN data port ==========
115 d2j_data,
116 d2j_bmsk,
117 d2j_data_par,
118 d2j_data_vld,
119 // ========== DMU/DSN data port==========
120
121 // ========== CTM DMA Wrack Port ==========
122 j2d_d_wrack_tag,
123 j2d_d_wrack_vld,
124 // ========== CTM DMA Wrack Port==========
125
126 // ========== CTM PIO Wrack Port ==========
127 d2j_p_wrack_tag,
128 d2j_p_wrack_vld,
129 // ========== CTM PIO Wrack Port==========
130
131 // ========== CRM Command Completion Port ==========
132 j2d_di_cmd,
133 j2d_di_ctag,
134 j2d_di_cmd_vld,
135 // ========== CRM Command Completion Port==========
136
137 // ========== CRM Command Request Port ==========
138 j2d_p_cmd,
139 j2d_p_addr,
140 j2d_p_bmsk,
141 j2d_p_ctag,
142 j2d_p_cmd_vld,
143 // ========== CRM Command Request Port==========
144
145 // ========== CRM Data Completion Port ==========
146 j2d_d_data,
147 j2d_d_data_par,
148 j2d_d_data_err,
149 j2d_d_data_vld,
150 // ========== CRM Data Completion Port==========
151
152 // ========== CRM Data Request Port ==========
153 j2d_p_data,
154 j2d_p_data_par,
155 j2d_p_data_vld,
156 // ========== CRM Data Request Port==========
157
158 // ========== DMU MMU Invalidate Port ==========
159 j2d_mmu_addr_vld,
160 j2d_mmu_addr,
161 // ========== DMU/DSN MMU Invalidate Port==========
162
163 // ========== DSN MMU NCU force parity error in ram ==========
164 dsn_dmc_iei,
165 // ========== DSN MMU NCU force parity error in ram ==========
166
167 // ========== DSN CRU debug bus to dbg.sv ==========
168 cr2ds_dbg_sel_a,
169 cr2ds_dbg_sel_b,
170 ds2cr_dbg_a,
171 ds2cr_dbg_b,
172 // ========== DSN CRU debug bus to dbg.sv ==========
173
174 // ========== DSN stall to/from dbg.sv ==========
175 dbg1_dmu_stall,
176 dbg1_dmu_resume,
177 dmu_dbg1_stall_ack,
178 ds2cl_stall
179 // ========== DSN stall to/from dbg.sv ==========
180);
181
182
183
184
185 // clocks, scan
186 input l1clk; // PINDEF:TOP io clock
187 input rst_l; // PINDEF:TOP
188
189
190 // upstream from DMU TO SIU
191 output dmu_sii_hdr_vld; // PINDEF:TOP DMU requesting to send packet to SIU
192 output dmu_sii_reqbypass; // PINDEF:TOP DMU requesting to send packet to bypass queue of SIU
193 output dmu_sii_datareq; // PINDEF:TOP DMU requesting to send packet w/data to SIU
194 output dmu_sii_datareq16; // PINDEF:TOP DMU requesting to send packet w/16B only
195 output [127:0] dmu_sii_data; // PINDEF:TOP Packet from DMU to SIU
196 output [7:0] dmu_sii_parity; // PINDEF:TOP Packet parity from DMU to SIU
197 output dmu_sii_be_parity; // PINDEF:TOP byte enable parity from DMU to SIU
198 output [15:0] dmu_sii_be; // PINDEF:TOP Packet byte enables from DMU to SIU
199
200 // downstream from SIU TO DMU
201 input sio_dmu_hdr_vld; // PINDEF:TOP SIU requesting to send DMA rd cpl to DMU
202 input [3:0] sii_dmu_wrack_tag; // PINDEF:TOP credit value returned to DMU for all DMA writes/int.
203 input sii_dmu_wrack_par; // PINDEF:TOP odd parity for sii_dmu_wrack_tag[3:0]
204 input sii_dmu_wrack_vld; // PINDEF:TOP asserted by SII to indicate a DMA write credit is returned
205 input [127:0] sio_dmu_data; // PINDEF:TOP Packet from SIU to DMU
206 input [7:0] sio_dmu_parity; // PINDEF:TOP Packet parity from SIU to DMU
207
208
209
210
211 // ========== NCU CSR ==========
212 // downstream
213 output dmu_ncu_stall; // PINDEF:TOP DMUCSR back pressure to NCU.
214 input ncu_dmu_vld; // PINDEF:TOP NCU to DMU CSR data valid.
215 input [31:0] ncu_dmu_data; // PINDEF:TOP NCU to DMU CSR data bus.
216 // upstream
217 input ncu_dmu_stall; // PINDEF:TOP NCU back pressure to DMU.
218 output dmu_ncu_vld; // PINDEF:TOP DMU to NCU CSR data valid.
219 output [31:0] dmu_ncu_data; // PINDEF:TOP DMU to NCU CSR data bus.
220 // ========== NCU CSR ==========
221
222 // ========== DMU CSR ==========
223 // PCI-ex ring
224 output [31:0] j2d_csr_ring_out; // csr ring out to PCI-ex(DMU/PEU)
225 input [31:0] d2j_csr_ring_in; // csr ring in from PCI-ex(DMU/PEU)
226
227 // ========== DMU CSR ==========
228
229
230 // ========== DMU PIO ==========
231 // downstream
232 input ncu_dmu_pio_hdr_vld; // PINDEF:TOP NCU to DSN pio_data header is valid
233 input ncu_dmu_mmu_addr_vld; // PINDEF:TOP NCU to DMU pio_data mmu invalidate vector is valid
234 input [63:0] ncu_dmu_pio_data; // PINDEF:TOP NCU to DMU pio_data bus.
235 input ncu_dmu_d_pei; // n2 RAS
236 input ncu_dmu_siicr_pei; // n2 RAS
237 input ncu_dmu_ctag_uei; // n2 RAS
238 input ncu_dmu_ctag_cei; // n2 RAS
239 input ncu_dmu_ncucr_pei; // n2 RAS
240 input ncu_dmu_iei; // n2 RAS
241 output dmu_ncu_wrack_vld; // PINDEF:TOP DMU to NCU release credit is valid
242 output [3:0] dmu_ncu_wrack_tag; // PINDEF:TOP DMU to NCU release credit value
243 output dmu_ncu_wrack_par; // PINDEF:TOP parity on dmu_ncu_wrack_tag[3:0]
244 output dmu_ncu_d_pe; // n2 RAS
245 output dmu_ncu_siicr_pe; // n2 RAS
246 output dmu_ncu_ctag_ue; // n2 RAS
247 output dmu_ncu_ctag_ce; // n2 RAS
248 output dmu_ncu_ncucr_pe; // n2 RAS
249 output dmu_ncu_ie; // n2 RAS
250 // ========== DMU PIO ==========
251
252 // ========== DMU Mondo ==========
253 input ncu_dmu_mondo_ack; // PINDEF:TOP Mondo Interrupt ack
254 input ncu_dmu_mondo_nack; // PINDEF:TOP Mondo Interrupt nack
255 input [5:0] ncu_dmu_mondo_id; // PINDEF:TOP Mondo Interrupt ID
256 input ncu_dmu_mondo_id_par; // PINDEF:TOP odd parity on ncu_dmu_mondo_id
257 // ========== DMU Mondo ==========
258
259 // ========== DMU/DSN command port ==========
260 input [3:0] d2j_cmd; // PINDEF:BOTTOM
261 input [36:0] d2j_addr; // PINDEF:BOTTOM
262 input [15:0] d2j_ctag; // PINDEF:BOTTOM
263 input d2j_cmd_vld; // PINDEF:BOTTOM
264 // ========== DMU/DSN command port==========
265
266 // ========== DMU/DSN data port ==========
267 input [127:0] d2j_data; // PINDEF:BOTTOM
268 input [15:0] d2j_bmsk; // PINDEF:BOTTOM
269 input [4:0] d2j_data_par; // PINDEF:BOTTOM
270 input d2j_data_vld; // PINDEF:BOTTOM
271 // ========== DMU/DSN data port==========
272
273 // ========== CTM DMA Wrack Port ==========
274 output [3:0] j2d_d_wrack_tag; // PINDEF:BOTTOM
275 output j2d_d_wrack_vld; // PINDEF:BOTTOM
276 // ========== CTM DMA Wrack Port==========
277
278 // ========== CTM PIO Wrack Port ==========
279 input [3:0] d2j_p_wrack_tag; // PINDEF:BOTTOM
280 input d2j_p_wrack_vld; // PINDEF:BOTTOM
281 // ========== CTM PIO Wrack Port==========
282
283 // ========== CRM Command Completion Port ==========
284 output [1:0] j2d_di_cmd; // PINDEF:BOTTOM
285 output [15:0] j2d_di_ctag; // PINDEF:BOTTOM
286 output j2d_di_cmd_vld; // PINDEF:BOTTOM
287 // ========== CRM Command Completion Port==========
288
289 // ========== CRM Command Request Port ==========
290 output [3:0] j2d_p_cmd; // PINDEF:BOTTOM
291 output [35:0] j2d_p_addr; // PINDEF:BOTTOM
292 output [15:0] j2d_p_bmsk; // PINDEF:BOTTOM
293 output [10:0] j2d_p_ctag; // PINDEF:BOTTOM
294 output j2d_p_cmd_vld; // PINDEF:BOTTOM
295 // ========== CRM Command Request Port==========
296
297 // ========== CRM Data Completion Port ==========
298 output [127:0] j2d_d_data; // PINDEF:BOTTOM
299 output [3:0] j2d_d_data_par; // PINDEF:BOTTOM
300 output j2d_d_data_err; // PINDEF:BOTTOM
301 output j2d_d_data_vld; // PINDEF:BOTTOM
302 // ========== CRM Data Completion Port==========
303
304 // ========== CRM Data Request Port ==========
305 output [127:0] j2d_p_data; // PINDEF:BOTTOM
306 output [3:0] j2d_p_data_par; // PINDEF:BOTTOM
307 output j2d_p_data_vld; // PINDEF:BOTTOM
308 // ========== CRM Data Request Port==========
309
310 // ========== DMU/DSN MMU Invalidate Port ==========
311 output j2d_mmu_addr_vld; // PINDEF:BOTTOM
312 output [42:6] j2d_mmu_addr; // PINDEF:BOTTOM
313 // ========== DMU/DSN MMU Invalidate Port==========
314
315 // ========== DSN MMU NCU force parity error in ram ==========
316 output dsn_dmc_iei;
317 // ========== DSN MMU NCU force parity error in ram ==========
318
319 // ========== DSN CRU debug bus ==========
320 input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2ds_dbg_sel_a;
321 input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2ds_dbg_sel_b;
322 output [`FIRE_DEBUG_WDTH-1:0] ds2cr_dbg_a;
323 output [`FIRE_DEBUG_WDTH-1:0] ds2cr_dbg_b;
324 // ========== DSN CRU debug bus ==========
325
326 // ========== DSN dbg stall ==========
327 input dbg1_dmu_stall;
328 input dbg1_dmu_resume;
329 output dmu_dbg1_stall_ack;
330 output ds2cl_stall;
331 // ========== DSN dbg srall ==========
332
333 //------------------------------------------------------------------------
334 // dmu_dsn_ccc_fsm Wires
335 //------------------------------------------------------------------------
336
337wire fsm2arb_done,rd_ack_vld,rd_nack_vld,fsm2pkt_valid;
338
339 //------------------------------------------------------------------------
340 // dmu_dsn_ccc_pkt Wires
341 //------------------------------------------------------------------------
342
343wire [31:0] j2d_csr_ring_out;
344
345 //------------------------------------------------------------------------
346 // dmu_dsn_ccc_dep Wires
347 //------------------------------------------------------------------------
348
349wire [63:0] data_out;
350wire dep2fsm_acc_vio,dep2fsm_done,dep2fsm_valid;
351
352 //------------------------------------------------------------------------
353 // dmu_dsn_ucb_flow Wires
354 //------------------------------------------------------------------------
355
356wire rd_req_vld,wr_req_vld,ack_busy,reset;
357wire [5:0] thr_id_in;
358wire [1:0] buf_id_in;
359wire [26:0] addr_in;
360wire [63:0] data_in;
361wire [`FIRE_DEBUG_WDTH-1:0] ucb2ctl_dbg_grp_a_1;
362wire [4:0] fsm2ctl_dbg_grp_b_1;
363wire [2:0] pkt2ctl_dbg_grp_b_1;
364
365
366dmu_dsn_ctl dmu_dsn_ctl (
367 .l1clk (l1clk), // input (dmu_dsn_ctl) <= ()
368 .rst_l (rst_l), // input (dmu_dsn_ccc_fsm,dmu_dsn_ccc_pkt,dmu_dsn_ctl) <= ()
369 .reset (reset), // output () => (dmu_dsn_ccc_fsm,dmu_dsn_ccc_pkt,dmu_dsn_ctl)
370 .dmu_sii_hdr_vld (dmu_sii_hdr_vld), // output (dmu_dsn_ctl) => ()
371 .dmu_sii_reqbypass (dmu_sii_reqbypass), // output (dmu_dsn_ctl) => ()
372 .dmu_sii_datareq (dmu_sii_datareq), // output (dmu_dsn_ctl) => ()
373 .dmu_sii_datareq16 (dmu_sii_datareq16), // output (dmu_dsn_ctl) => ()
374 .dmu_sii_data (dmu_sii_data[127:0]), // output (dmu_dsn_ctl) => ()
375 .dmu_sii_parity (dmu_sii_parity[7:0]), // output (dmu_dsn_ctl) => ()
376 .dmu_sii_be_parity (dmu_sii_be_parity), // output (dmu_dsn_ctl) => ()
377 .dmu_sii_be (dmu_sii_be[15:0]), // output (dmu_dsn_ctl) => ()
378 .sio_dmu_hdr_vld (sio_dmu_hdr_vld), // input (dmu_dsn_ctl) <= ()
379 .sii_dmu_wrack_tag (sii_dmu_wrack_tag[3:0]), // output (dmu_dsn_ctl) => ()
380 .sii_dmu_wrack_par (sii_dmu_wrack_par), // output (dmu_dsn_ctl) => ()
381 .sii_dmu_wrack_vld (sii_dmu_wrack_vld), // output (dmu_dsn_ctl) => ()
382 .sio_dmu_data (sio_dmu_data[127:0]), // input (dmu_dsn_ctl) <= ()
383 .sio_dmu_parity (sio_dmu_parity[7:0]), // input (dmu_dsn_ctl) <= ()
384 .ncu_dmu_pio_hdr_vld (ncu_dmu_pio_hdr_vld), // input (dmu_dsn_ctl) <= ()
385 .ncu_dmu_mmu_addr_vld (ncu_dmu_mmu_addr_vld), // input (dmu_dsn_ctl) <= ()
386 .ncu_dmu_pio_data (ncu_dmu_pio_data[63:0]), // input (dmu_dsn_ctl) <= ()
387 .ncu_dmu_d_pei (ncu_dmu_d_pei), // input (dmu_dsn_ctl) <= () n2 RAS
388 .ncu_dmu_siicr_pei (ncu_dmu_siicr_pei), // input (dmu_dsn_ctl) <= () n2 RAS
389 .ncu_dmu_ctag_uei (ncu_dmu_ctag_uei), // input (dmu_dsn_ctl) <= () n2 RAS
390 .ncu_dmu_ctag_cei (ncu_dmu_ctag_cei), // input (dmu_dsn_ctl) <= () n2 RAS
391 .ncu_dmu_ncucr_pei (ncu_dmu_ncucr_pei), // input (dmu_dsn_ctl) <= () n2 RAS
392 .ncu_dmu_iei (ncu_dmu_iei), // input (dmu_dsn_ctl) <= () n2 RAS
393 .dmu_ncu_wrack_vld (dmu_ncu_wrack_vld), // input (dmu_dsn_ctl) <= ()
394 .dmu_ncu_wrack_tag (dmu_ncu_wrack_tag[3:0]), // input (dmu_dsn_ctl) <= ()
395 .dmu_ncu_wrack_par (dmu_ncu_wrack_par), // input (dmu_dsn_ctl) <= ()
396 .dmu_ncu_d_pe (dmu_ncu_d_pe), // input (dmu_dsn_ctl) <= () n2 RAS
397 .dmu_ncu_siicr_pe (dmu_ncu_siicr_pe), // input (dmu_dsn_ctl) <= () n2 RAS
398 .dmu_ncu_ctag_ue (dmu_ncu_ctag_ue), // input (dmu_dsn_ctl) <= () n2 RAS
399 .dmu_ncu_ctag_ce (dmu_ncu_ctag_ce), // input (dmu_dsn_ctl) <= () n2 RAS
400 .dmu_ncu_ncucr_pe (dmu_ncu_ncucr_pe), // input (dmu_dsn_ctl) <= () n2 RAS
401 .dmu_ncu_ie (dmu_ncu_ie), // input (dmu_dsn_ctl) <= () n2 RAS
402 .ncu_dmu_mondo_ack (ncu_dmu_mondo_ack), // input (dmu_dsn_ctl) <= ()
403 .ncu_dmu_mondo_nack (ncu_dmu_mondo_nack), // input (dmu_dsn_ctl) <= ()
404 .ncu_dmu_mondo_id (ncu_dmu_mondo_id[5:0]), // input (dmu_dsn_ctl) <= ()
405 .ncu_dmu_mondo_id_par (ncu_dmu_mondo_id_par), // input (dmu_dsn_ctl) <= ()
406 .d2j_cmd (d2j_cmd[3:0]), // input (dmu_dsn_ctl) <= ()
407 .d2j_addr (d2j_addr[36:0]), // input (dmu_dsn_ctl) <= ()
408 .d2j_ctag (d2j_ctag[15:0]), // input (dmu_dsn_ctl) <= ()
409 .d2j_cmd_vld (d2j_cmd_vld), // input (dmu_dsn_ctl) <= ()
410 .d2j_data (d2j_data[127:0]), // input (dmu_dsn_ctl) <= ()
411 .d2j_bmsk (d2j_bmsk[15:0]), // input (dmu_dsn_ctl) <= ()
412 .d2j_data_par (d2j_data_par[4:0]), // input (dmu_dsn_ctl) <= ()
413 .d2j_data_vld (d2j_data_vld), // input (dmu_dsn_ctl) <= ()
414 .j2d_d_wrack_tag (j2d_d_wrack_tag[3:0]), // output (dmu_dsn_ctl) => ()
415 .j2d_d_wrack_vld (j2d_d_wrack_vld), // output (dmu_dsn_ctl) => ()
416 .d2j_p_wrack_tag (d2j_p_wrack_tag[3:0]), // input (dmu_dsn_ctl) <= ()
417 .d2j_p_wrack_vld (d2j_p_wrack_vld), // input (dmu_dsn_ctl) <= ()
418 .j2d_di_cmd (j2d_di_cmd[1:0]), // output (dmu_dsn_ctl) => ()
419 .j2d_di_ctag (j2d_di_ctag[15:0]), // output (dmu_dsn_ctl) => ()
420 .j2d_di_cmd_vld (j2d_di_cmd_vld), // output (dmu_dsn_ctl) => ()
421 .j2d_p_cmd (j2d_p_cmd[3:0]), // output (dmu_dsn_ctl) => ()
422 .j2d_p_addr (j2d_p_addr[35:0]), // output (dmu_dsn_ctl) => ()
423 .j2d_p_bmsk (j2d_p_bmsk[15:0]), // output (dmu_dsn_ctl) => ()
424 .j2d_p_ctag (j2d_p_ctag[10:0]), // output (dmu_dsn_ctl) => ()
425 .j2d_p_cmd_vld (j2d_p_cmd_vld), // output (dmu_dsn_ctl) => ()
426 .j2d_d_data (j2d_d_data[127:0]), // output (dmu_dsn_ctl) => ()
427 .j2d_d_data_par (j2d_d_data_par[3:0]), // output (dmu_dsn_ctl) => ()
428 .j2d_d_data_err (j2d_d_data_err), // output (dmu_dsn_ctl) => ()
429 .j2d_d_data_vld (j2d_d_data_vld), // output (dmu_dsn_ctl) => ()
430 .j2d_p_data (j2d_p_data[127:0]), // output (dmu_dsn_ctl) => ()
431 .j2d_p_data_par (j2d_p_data_par[3:0]), // output (dmu_dsn_ctl) => ()
432 .j2d_p_data_vld (j2d_p_data_vld), // output (dmu_dsn_ctl) => ()
433 .j2d_mmu_addr_vld (j2d_mmu_addr_vld), // output (dmu_dsn_ctl) => ()
434 .j2d_mmu_addr (j2d_mmu_addr[42:6]), // output (dmu_dsn_ctl) => ()
435 .dsn_dmc_iei (dsn_dmc_iei), // output (dmu_dsn_ctl) => ()
436 .cr2ds_dbg_sel_a (cr2ds_dbg_sel_a[5:0]), // input (dmu_dsn_ctl) <= ()
437 .cr2ds_dbg_sel_b (cr2ds_dbg_sel_b[5:0]), // input (dmu_dsn_ctl) <= ()
438 .ds2cr_dbg_a (ds2cr_dbg_a), // output (dmu_dsn_ctl) => ()
439 .ds2cr_dbg_b (ds2cr_dbg_b), // output (dmu_dsn_ctl) => ()
440 .ucb2ctl_dbg_grp_a_1 (ucb2ctl_dbg_grp_a_1), // input (dmu_dsn_ctl) <= (dmu_dsn_ucb_flow)
441 .fsm2ctl_dbg_grp_b_1 (fsm2ctl_dbg_grp_b_1), // input (dmu_dsn_ctl) <= (dmu_dsn_ccc_fsm)
442 .pkt2ctl_dbg_grp_b_1 (pkt2ctl_dbg_grp_b_1), // input (dmu_dsn_ctl) <= (dmu_dsn_ccc_fsm)
443 .dbg1_dmu_stall (dbg1_dmu_stall), // input (dmu_dsn_ctl) <= (dmu_dsn_ccc_fsm)
444 .dbg1_dmu_resume (dbg1_dmu_resume), // input (dmu_dsn_ctl) <= (dmu_dsn_ccc_fsm)
445 .dmu_dbg1_stall_ack (dmu_dbg1_stall_ack), // input (dmu_dsn_ctl) <= (dmu_dsn_ccc_fsm)
446 .ds2cl_stall (ds2cl_stall) // input (dmu_dsn_ctl) <= (dmu_dsn_ccc_fsm)
447
448
449 );
450
451
452dmu_dsn_ccc_fsm dmu_dsn_ccc_fsm (
453 .clk (l1clk), // input (dmu_dsn_ccc_fsm,dmu_dsn_ccc_pkt) <= ()
454 .rst_l (rst_l), // input (dmu_dsn_ccc_fsm,dmu_dsn_ccc_pkt,dmu_dsn_ctl) <= ()
455 .rd_req_vld (rd_req_vld), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ucb_flow)
456 .wr_req_vld (wr_req_vld), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ucb_flow)
457 .dep2fsm_acc_vio (dep2fsm_acc_vio), // input (dmu_dsn_ccc_fsm) <= (dmu_dsn_ccc_dep)
458 .dep2fsm_done (dep2fsm_done), // input (dmu_dsn_ccc_fsm) <= (dmu_dsn_ccc_dep)
459 .dep2fsm_valid (dep2fsm_valid), // input (dmu_dsn_ccc_fsm) <= (dmu_dsn_ccc_dep)
460 .ack_busy (ack_busy), // input (dmu_dsn_ccc_fsm) <= (dmu_dsn_ucb_flow)
461 .fsm2arb_done (fsm2arb_done), // output (dmu_dsn_ccc_fsm) => (dmu_dsn_ucb_flow)
462 .rd_ack_vld (rd_ack_vld), // output (dmu_dsn_ccc_fsm) => (dmu_dsn_ucb_flow)
463 .rd_nack_vld (rd_nack_vld), // output (dmu_dsn_ccc_fsm) => (dmu_dsn_ucb_flow)
464 .fsm2pkt_valid (fsm2pkt_valid), // output (dmu_dsn_ccc_fsm) => (dmu_dsn_ccc_pkt)
465 .fsm2ctl_dbg_grp_b_1 (fsm2ctl_dbg_grp_b_1[4:0]) // output (dmu_dsn_ccc_fsm) => (dmu_dsn_ctl)
466 );
467
468dmu_dsn_ccc_pkt dmu_dsn_ccc_pkt (
469 .clk (l1clk), // input (dmu_dsn_ccc_fsm,dmu_dsn_ccc_pkt) <= ()
470 .rst_l (rst_l), // input (dmu_dsn_ccc_fsm,dmu_dsn_ccc_pkt,dmu_dsn_ctl) <= ()
471 .cdp2pkt_data (data_in[63:0]), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ucb_flow)
472 .buf_id_in (buf_id_in[1:0]), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ucb_flow)
473 .cdp2pkt_addr (addr_in[26:0]), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ucb_flow)
474 .fsm2pkt_valid (fsm2pkt_valid), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ccc_fsm)
475 .wr_req_vld (wr_req_vld), // input (dmu_dsn_ccc_pkt) <= (dmu_dsn_ucb_flow)
476 .j2d_csr_ring_out (j2d_csr_ring_out[31:0]),// output (dmu_dsn_ccc_pkt) => ()
477 .pkt2ctl_dbg_grp_b_1 (pkt2ctl_dbg_grp_b_1[2:0])// output (dmu_dsn_ccc_pkt) => ()
478 );
479
480dmu_dsn_ccc_dep dmu_dsn_ccc_dep (
481 .clk (l1clk), // input (dmu_dsn_ccc_dep,dmu_dsn_ccc_pkt) <= ()
482 .rst_l (rst_l), // input (dmu_dsn_ccc_dep,dmu_dsn_ccc_pkt,dmu_dsn_ctl) <= ()
483 .dep2cdp_data (data_out[63:0]), // output (dmu_dsn_ccc_dep) => (dmu_dsn_ucb_flow)
484 .dep2fsm_acc_vio (dep2fsm_acc_vio), // output (dmu_dsn_ccc_dep) => (dep2fsm_acc_vio)
485 .dep2fsm_done (dep2fsm_done), // output (dmu_dsn_ccc_dep) => (dep2fsm_done)
486 .dep2fsm_valid (dep2fsm_valid), // output (dmu_dsn_ccc_dep) => (dep2fsm_valid)
487 .d2j_csr_ring_in (d2j_csr_ring_in[31:0])// input (dmu_dsn_ccc_dep) <= ()
488 );
489
490
491
492dmu_dsn_ucb_flow dmu_dsn_ucb_flow (
493 .enl2clk (l1clk), // input (dmu_dsn_ucb_flow,dmu_dsn_ucb_in32,dmu_dsn_ucb_out32) <= ()
494 .reset (reset), // input (dmu_dsn_ucb_flow,dmu_dsn_ucb_in32,dmu_dsn_ucb_out32) <= ()
495 .ncu_dmu_vld (ncu_dmu_vld), // input (dmu_dsn_ucb_flow) <= ()
496 .ncu_dmu_data (ncu_dmu_data[31:0]), // input (dmu_dsn_ucb_flow) <= ()
497 .dmu_ncu_stall (dmu_ncu_stall), // output (dmu_dsn_ucb_flow) => ()
498 .dmu_ncu_vld (dmu_ncu_vld), // output (dmu_dsn_ucb_flow) => ()
499 .dmu_ncu_data (dmu_ncu_data[31:0]), // output (dmu_dsn_ucb_flow) => ()
500 .ncu_dmu_stall (ncu_dmu_stall), // input (dmu_dsn_ucb_flow) <= ()
501 .rd_req_vld (rd_req_vld), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_flow)
502 .wr_req_vld (wr_req_vld), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_flow)
503 .thr_id_in (thr_id_in[5:0]), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_flow)
504 .buf_id_in (buf_id_in[1:0]), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_flow)
505 .addr_in (addr_in[26:0]), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_flow)
506 .data_in (data_in[63:0]), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_flow)
507 .req_acpted (fsm2arb_done), // input (dmu_dsn_ucb_flow) <= (dmu_dsn_ccc_fsm)
508 .rd_ack_vld (rd_ack_vld), // input (dmu_dsn_ucb_flow) <= (dmu_dsn_ucb_fsm)
509 .rd_nack_vld (rd_nack_vld), // input (dmu_dsn_ucb_flow) <= (dmu_dsn_ucb_fsm)
510 .thr_id_out (thr_id_in[5:0]), // input (dmu_dsn_ucb_flow) <= (dmu_dsn_ucb_flow)
511 .buf_id_out (buf_id_in[1:0]), // input (dmu_dsn_ucb_flow) <= (dmu_dsn_ucb_flow)
512 .data_out (data_out[63:0]), // input (dmu_dsn_ucb_flow) <= (dmu_dsn_ccc_dep)
513 .ack_busy (ack_busy), // output (dmu_dsn_ucb_flow) => (dmu_dsn_ucb_fsm)
514 .ucb2ctl_dbg_grp_a_1 (ucb2ctl_dbg_grp_a_1) // output (dmu_dsn_ucb_flow) => (dmu_dsn_ctl)
515 );
516
517
518
519endmodule
520
521
Full OpenSPARC design & verification tarball including full HDL.