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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_dsn_ucb_out32.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_dsn_ucb_out32 ( | |
36 | // Global // | |
37 | enl2clk, | |
38 | reset, | |
39 | // UCB bus // | |
40 | vld, | |
41 | data, | |
42 | stall, | |
43 | // Local unit // | |
44 | outdata_buf_busy, | |
45 | outdata_buf_wr, | |
46 | outdata_buf_in, | |
47 | outdata_vec_in ); | |
48 | ||
49 | ||
50 | // Globals | |
51 | input enl2clk; | |
52 | input reset; | |
53 | ||
54 | // UCB bus interface | |
55 | output vld; | |
56 | output [31:0] data; | |
57 | input stall; | |
58 | ||
59 | // Local interface | |
60 | output outdata_buf_busy; | |
61 | input outdata_buf_wr; | |
62 | input [127:0] outdata_buf_in; | |
63 | input [3:0] outdata_vec_in; | |
64 | ||
65 | ||
66 | ||
67 | // Local signals | |
68 | reg stall_d1; | |
69 | reg [3:0] outdata_vec; | |
70 | wire [3:0] outdata_vec_next; | |
71 | reg [127:0] outdata_buf; | |
72 | wire [127:0] outdata_buf_next; | |
73 | wire load_outdata; | |
74 | wire shift_outdata; | |
75 | ||
76 | ||
77 | //////////////////////////////////////////////////////////////////////// | |
78 | // Code starts here | |
79 | //////////////////////////////////////////////////////////////////////// | |
80 | /************************************************************ | |
81 | * UCB bus interface flops | |
82 | ************************************************************/ | |
83 | assign vld = outdata_vec[0]; | |
84 | assign data[31:0] = outdata_buf[31:0]; | |
85 | /* | |
86 | dffr #(1) stall_d1_ff (.d(stall), | |
87 | .clk(enl2clk), | |
88 | .reset(reset), | |
89 | .q(stall_d1) ); | |
90 | */ | |
91 | always @(posedge enl2clk ) begin | |
92 | if (reset) begin | |
93 | stall_d1 <= 1'b0; | |
94 | end | |
95 | else begin | |
96 | stall_d1 <= stall; | |
97 | end | |
98 | end | |
99 | ||
100 | ||
101 | /************************************************************ | |
102 | * Outbound Data | |
103 | ************************************************************/ | |
104 | // BP 7-26-05 dbg needs reads to be at least 8 cycles apart, verify here | |
105 | // with 0in checker | |
106 | // 0in assert_window -start load_outdata -start_count 1 -stop_count 9 -not_in load_outdata | |
107 | // accept new data only if there is none being processed | |
108 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; | |
109 | ||
110 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; | |
111 | ||
112 | assign shift_outdata = outdata_vec[0] & ~stall_d1; | |
113 | ||
114 | assign outdata_vec_next[3:0] = load_outdata ? outdata_vec_in[3:0]: | |
115 | shift_outdata ? (outdata_vec[3:0] >> 1) : | |
116 | outdata_vec[3:0]; | |
117 | /* | |
118 | dffr #(4) outdata_vec_ff (.d(outdata_vec_next[3:0]), | |
119 | .clk(enl2clk), | |
120 | .reset(reset), | |
121 | .q(outdata_vec[3:0]) ); | |
122 | */ | |
123 | assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0]: | |
124 | shift_outdata ? (outdata_buf[127:0] >> 32): | |
125 | outdata_buf[127:0]; | |
126 | /* | |
127 | dff #(128) outdata_buf_ff (.d(outdata_buf_next[127:0]), | |
128 | .clk(enl2clk), | |
129 | .q(outdata_buf[127:0]) ); | |
130 | */ | |
131 | always @(posedge enl2clk ) begin | |
132 | if (reset) begin | |
133 | outdata_vec[3:0] <= 4'b0; | |
134 | end | |
135 | else begin | |
136 | outdata_vec[3:0] <= outdata_vec_next[3:0]; | |
137 | end | |
138 | end | |
139 | ||
140 | always @(posedge enl2clk ) | |
141 | if (reset) begin | |
142 | outdata_buf[127:0] <= 128'b0; | |
143 | end | |
144 | else begin | |
145 | outdata_buf[127:0] <= outdata_buf_next[127:0]; | |
146 | end | |
147 | ||
148 | ||
149 | endmodule // dmu_dsn_ucb_out32 | |
150 | ||
151 | ||
152 | ||
153 | ||
154 | ||
155 |