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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_addr_decode.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_cib_addr_decode | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | daemon_csrbus_valid, | |
40 | daemon_csrbus_addr, | |
41 | csrbus_src_bus, | |
42 | daemon_csrbus_wr, | |
43 | daemon_csrbus_wr_out, | |
44 | daemon_csrbus_wr_data, | |
45 | daemon_csrbus_wr_data_out, | |
46 | daemon_csrbus_mapped, | |
47 | csrbus_acc_vio, | |
48 | daemon_transaction_in_progress, | |
49 | instance_id, | |
50 | daemon_csrbus_done, | |
51 | ilu_log_en_select_pulse, | |
52 | ilu_int_en_select_pulse, | |
53 | ilu_en_err_select, | |
54 | ilu_log_err_select_pulse, | |
55 | ilu_log_err_rw1c_alias, | |
56 | ilu_log_err_rw1s_alias, | |
57 | pec_int_en_select_pulse, | |
58 | pec_en_err_select, | |
59 | ilu_diagnos_select_pulse | |
60 | ); | |
61 | ||
62 | //==================================================================== | |
63 | // Polarity declarations | |
64 | //==================================================================== | |
65 | input clk; // Clock signal | |
66 | input rst_l; // Reset | |
67 | input daemon_csrbus_valid; // Daemon_Valid | |
68 | input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
69 | input [1:0] csrbus_src_bus; // Source bus | |
70 | input daemon_csrbus_wr; // Read/Write signal | |
71 | output daemon_csrbus_wr_out; // Read/Write signal | |
72 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
73 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
74 | output daemon_csrbus_mapped; // mapped | |
75 | output csrbus_acc_vio; // acc_vio | |
76 | input daemon_transaction_in_progress; // daemon_transaction_in_progress | |
77 | input instance_id; // Instance ID | |
78 | output daemon_csrbus_done; // Operation is done | |
79 | output ilu_log_en_select_pulse; // select signal | |
80 | output ilu_int_en_select_pulse; // select signal | |
81 | output ilu_en_err_select; // select signal | |
82 | output ilu_log_err_select_pulse; // select signal | |
83 | output ilu_log_err_rw1c_alias; // alias signal | |
84 | output ilu_log_err_rw1s_alias; // alias signal | |
85 | output pec_int_en_select_pulse; // select signal | |
86 | output pec_en_err_select; // select signal | |
87 | output ilu_diagnos_select_pulse; // select signal | |
88 | ||
89 | //==================================================================== | |
90 | // Type declarations | |
91 | //==================================================================== | |
92 | wire clk; // Clock signal | |
93 | wire rst_l; // Reset | |
94 | wire daemon_csrbus_valid; // Daemon_Valid | |
95 | wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
96 | wire [1:0] csrbus_src_bus; // Source bus | |
97 | wire daemon_csrbus_wr; // Read/Write signal | |
98 | reg daemon_csrbus_wr_out; // Read/Write signal | |
99 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
100 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
101 | wire daemon_csrbus_mapped; // mapped | |
102 | wire csrbus_acc_vio; // acc_vio | |
103 | wire daemon_transaction_in_progress; // daemon_transaction_in_progress | |
104 | wire instance_id; // Instance ID | |
105 | wire daemon_csrbus_done; // Operation is done | |
106 | reg ilu_log_en_select_pulse; // select signal | |
107 | reg ilu_int_en_select_pulse; // select signal | |
108 | reg ilu_en_err_select; // select signal | |
109 | reg ilu_log_err_select_pulse; // select signal | |
110 | wire ilu_log_err_rw1c_alias; // alias signal | |
111 | wire ilu_log_err_rw1s_alias; // alias signal | |
112 | reg pec_int_en_select_pulse; // select signal | |
113 | reg pec_en_err_select; // select signal | |
114 | reg ilu_diagnos_select_pulse; // select signal | |
115 | ||
116 | ||
117 | //==================================================================== | |
118 | // Clocked valid | |
119 | //==================================================================== | |
120 | reg clocked_valid; | |
121 | reg clocked_valid_pulse; | |
122 | always @(posedge clk) | |
123 | begin | |
124 | if(~rst_l) | |
125 | begin | |
126 | clocked_valid <= 1'b0; | |
127 | clocked_valid_pulse <= 1'b0; | |
128 | end | |
129 | else | |
130 | begin | |
131 | clocked_valid <= daemon_csrbus_valid; | |
132 | clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid; | |
133 | end | |
134 | end | |
135 | ||
136 | //==================================================================== | |
137 | // Address Decode | |
138 | //==================================================================== | |
139 | reg ilu_log_en_addr_decoded; | |
140 | reg ilu_int_en_addr_decoded; | |
141 | reg ilu_en_err_addr_decoded; | |
142 | reg ilu_log_err_rw1c_alias_addr_decoded; | |
143 | reg ilu_log_err_rw1s_alias_addr_decoded; | |
144 | reg pec_int_en_addr_decoded; | |
145 | reg pec_en_err_addr_decoded; | |
146 | reg ilu_diagnos_addr_decoded; | |
147 | ||
148 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) | |
149 | begin | |
150 | if (~daemon_csrbus_valid) | |
151 | begin | |
152 | ilu_log_en_addr_decoded = 1'b0; | |
153 | ilu_int_en_addr_decoded = 1'b0; | |
154 | ilu_en_err_addr_decoded = 1'b0; | |
155 | ilu_log_err_rw1c_alias_addr_decoded = 1'b0; | |
156 | ilu_log_err_rw1s_alias_addr_decoded = 1'b0; | |
157 | pec_int_en_addr_decoded = 1'b0; | |
158 | pec_en_err_addr_decoded = 1'b0; | |
159 | ilu_diagnos_addr_decoded = 1'b0; | |
160 | end | |
161 | else | |
162 | case (instance_id) | |
163 | ||
164 | `FIRE_DLC_ILU_CIB_INSTANCE_ID_VALUE_A: | |
165 | begin | |
166 | ilu_log_en_addr_decoded = | |
167 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ADDR; | |
168 | ilu_int_en_addr_decoded = | |
169 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ADDR; | |
170 | ilu_en_err_addr_decoded = | |
171 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ADDR; | |
172 | ilu_log_err_rw1c_alias_addr_decoded = | |
173 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR; | |
174 | ilu_log_err_rw1s_alias_addr_decoded = | |
175 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR; | |
176 | pec_int_en_addr_decoded = | |
177 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ADDR; | |
178 | pec_en_err_addr_decoded = | |
179 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ADDR; | |
180 | ilu_diagnos_addr_decoded = | |
181 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ADDR; | |
182 | end | |
183 | ||
184 | `FIRE_DLC_ILU_CIB_INSTANCE_ID_VALUE_B: | |
185 | begin | |
186 | ilu_log_en_addr_decoded = | |
187 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_EN_HW_ADDR; | |
188 | ilu_int_en_addr_decoded = | |
189 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_ILU_INT_EN_HW_ADDR; | |
190 | ilu_en_err_addr_decoded = | |
191 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_ILU_EN_ERR_HW_ADDR; | |
192 | ilu_log_err_rw1c_alias_addr_decoded = | |
193 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR; | |
194 | ilu_log_err_rw1s_alias_addr_decoded = | |
195 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR; | |
196 | pec_int_en_addr_decoded = | |
197 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_PEC_INT_EN_HW_ADDR; | |
198 | pec_en_err_addr_decoded = | |
199 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_PEC_EN_ERR_HW_ADDR; | |
200 | ilu_diagnos_addr_decoded = | |
201 | daemon_csrbus_addr[26:0] == `FIRE_DLC_ILU_CIB_CSR_B_ILU_DIAGNOS_HW_ADDR; | |
202 | end | |
203 | ||
204 | default: | |
205 | begin | |
206 | ilu_log_en_addr_decoded = 1'b0; | |
207 | ilu_int_en_addr_decoded = 1'b0; | |
208 | ilu_en_err_addr_decoded = 1'b0; | |
209 | ilu_log_err_rw1s_alias_addr_decoded = 1'b0; | |
210 | ilu_log_err_rw1c_alias_addr_decoded = 1'b0; | |
211 | pec_int_en_addr_decoded = 1'b0; | |
212 | pec_en_err_addr_decoded = 1'b0; | |
213 | ilu_diagnos_addr_decoded = 1'b0; | |
214 | // vlint flag_system_call off | |
215 | // synopsys translate_off | |
216 | if(daemon_csrbus_valid) | |
217 | begin // axis tbcall_region | |
218 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_ilu_cib_csr is bad"); `endif | |
219 | end // end of tbcall_region | |
220 | // synopsys translate_on | |
221 | // vlint flag_system_call on | |
222 | end | |
223 | endcase | |
224 | end | |
225 | ||
226 | //==================================================================== | |
227 | // Register violations | |
228 | //==================================================================== | |
229 | //----- reg_acc_vio: ilu_log_en | |
230 | reg ilu_log_en_acc_vio; | |
231 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
232 | ilu_log_en_addr_decoded or | |
233 | daemon_transaction_in_progress) | |
234 | begin | |
235 | if (daemon_transaction_in_progress | ~ilu_log_en_addr_decoded) | |
236 | ilu_log_en_acc_vio = 1'b0; | |
237 | else | |
238 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
239 | // reads | |
240 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
241 | ilu_log_en_acc_vio = 1'b0; | |
242 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
243 | ilu_log_en_acc_vio = 1'b0; | |
244 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
245 | ilu_log_en_acc_vio = 1'b0; | |
246 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
247 | ilu_log_en_acc_vio = 1'b0; | |
248 | // writes | |
249 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
250 | ilu_log_en_acc_vio = 1'b0; | |
251 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
252 | ilu_log_en_acc_vio = 1'b0; | |
253 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
254 | ilu_log_en_acc_vio = 1'b0; | |
255 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
256 | ilu_log_en_acc_vio = 1'b0; | |
257 | ||
258 | default: | |
259 | begin | |
260 | ilu_log_en_acc_vio = 1'b0; | |
261 | begin // axis tbcall_region | |
262 | // vlint flag_system_call off | |
263 | // synopsys translate_off | |
264 | `ifdef PR_ERROR if ($time > 1 && rst_l)`PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_ilu_log_en"); `endif | |
265 | // synopsys translate_on | |
266 | // vlint flag_system_call on | |
267 | end // end of tbcall_region | |
268 | end | |
269 | endcase | |
270 | end | |
271 | //----- reg_acc_vio: ilu_int_en | |
272 | reg ilu_int_en_acc_vio; | |
273 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
274 | ilu_int_en_addr_decoded or | |
275 | daemon_transaction_in_progress) | |
276 | begin | |
277 | if (daemon_transaction_in_progress | ~ilu_int_en_addr_decoded) | |
278 | ilu_int_en_acc_vio = 1'b0; | |
279 | else | |
280 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
281 | // reads | |
282 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
283 | ilu_int_en_acc_vio = 1'b0; | |
284 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
285 | ilu_int_en_acc_vio = 1'b0; | |
286 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
287 | ilu_int_en_acc_vio = 1'b0; | |
288 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
289 | ilu_int_en_acc_vio = 1'b0; | |
290 | // writes | |
291 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
292 | ilu_int_en_acc_vio = 1'b0; | |
293 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
294 | ilu_int_en_acc_vio = 1'b0; | |
295 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
296 | ilu_int_en_acc_vio = 1'b0; | |
297 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
298 | ilu_int_en_acc_vio = 1'b0; | |
299 | ||
300 | default: | |
301 | begin | |
302 | ilu_int_en_acc_vio = 1'b0; | |
303 | begin // axis tbcall_region | |
304 | // vlint flag_system_call off | |
305 | // synopsys translate_off | |
306 | `ifdef PR_ERROR if ($time > 1 && rst_l)`PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_ilu_int_en"); `endif | |
307 | // synopsys translate_on | |
308 | // vlint flag_system_call on | |
309 | end // end of tbcall_region | |
310 | end | |
311 | endcase | |
312 | end | |
313 | //----- reg_acc_vio: ilu_en_err | |
314 | reg ilu_en_err_acc_vio; | |
315 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
316 | ilu_en_err_addr_decoded or | |
317 | daemon_transaction_in_progress) | |
318 | begin | |
319 | if (daemon_transaction_in_progress | ~ilu_en_err_addr_decoded) | |
320 | ilu_en_err_acc_vio = 1'b0; | |
321 | else | |
322 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
323 | // reads | |
324 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
325 | ilu_en_err_acc_vio = 1'b0; | |
326 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
327 | ilu_en_err_acc_vio = 1'b0; | |
328 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
329 | ilu_en_err_acc_vio = 1'b0; | |
330 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
331 | ilu_en_err_acc_vio = 1'b0; | |
332 | // writes | |
333 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
334 | ilu_en_err_acc_vio = 1'b0; | |
335 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
336 | ilu_en_err_acc_vio = 1'b0; | |
337 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
338 | ilu_en_err_acc_vio = 1'b0; | |
339 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
340 | ilu_en_err_acc_vio = 1'b0; | |
341 | ||
342 | default: | |
343 | begin | |
344 | ilu_en_err_acc_vio = 1'b0; | |
345 | begin // axis tbcall_region | |
346 | // vlint flag_system_call off | |
347 | // synopsys translate_off | |
348 | `ifdef PR_ERROR if ($time > 1 && rst_l)`PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_ilu_en_err"); `endif | |
349 | // synopsys translate_on | |
350 | // vlint flag_system_call on | |
351 | end // end of tbcall_region | |
352 | end | |
353 | endcase | |
354 | end | |
355 | //----- reg_acc_vio: ilu_log_err | |
356 | reg ilu_log_err_acc_vio; | |
357 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
358 | ilu_log_err_rw1c_alias_addr_decoded or | |
359 | ilu_log_err_rw1s_alias_addr_decoded or | |
360 | daemon_transaction_in_progress) | |
361 | begin | |
362 | if (daemon_transaction_in_progress | | |
363 | ~ (ilu_log_err_rw1c_alias_addr_decoded | ilu_log_err_rw1s_alias_addr_decoded)) | |
364 | ilu_log_err_acc_vio = 1'b0; | |
365 | else | |
366 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
367 | // reads | |
368 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
369 | ilu_log_err_acc_vio = 1'b0; | |
370 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
371 | ilu_log_err_acc_vio = 1'b0; | |
372 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
373 | ilu_log_err_acc_vio = 1'b0; | |
374 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
375 | ilu_log_err_acc_vio = 1'b0; | |
376 | // writes | |
377 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
378 | ilu_log_err_acc_vio = 1'b0; | |
379 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
380 | ilu_log_err_acc_vio = 1'b0; | |
381 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
382 | ilu_log_err_acc_vio = 1'b0; | |
383 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
384 | ilu_log_err_acc_vio = 1'b0; | |
385 | ||
386 | default: | |
387 | begin | |
388 | ilu_log_err_acc_vio = 1'b0; | |
389 | begin // axis tbcall_region | |
390 | // vlint flag_system_call off | |
391 | // synopsys translate_off | |
392 | `ifdef PR_ERROR if ($time > 1 && rst_l)`PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_ilu_log_err_rw1c_alias"); `endif | |
393 | // synopsys translate_on | |
394 | // vlint flag_system_call on | |
395 | end // end of tbcall_region | |
396 | end | |
397 | endcase | |
398 | end | |
399 | //----- reg_acc_vio: pec_int_en | |
400 | reg pec_int_en_acc_vio; | |
401 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
402 | pec_int_en_addr_decoded or | |
403 | daemon_transaction_in_progress) | |
404 | begin | |
405 | if (daemon_transaction_in_progress | ~pec_int_en_addr_decoded) | |
406 | pec_int_en_acc_vio = 1'b0; | |
407 | else | |
408 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
409 | // reads | |
410 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
411 | pec_int_en_acc_vio = 1'b0; | |
412 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
413 | pec_int_en_acc_vio = 1'b0; | |
414 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
415 | pec_int_en_acc_vio = 1'b0; | |
416 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
417 | pec_int_en_acc_vio = 1'b0; | |
418 | // writes | |
419 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
420 | pec_int_en_acc_vio = 1'b0; | |
421 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
422 | pec_int_en_acc_vio = 1'b0; | |
423 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
424 | pec_int_en_acc_vio = 1'b0; | |
425 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
426 | pec_int_en_acc_vio = 1'b0; | |
427 | ||
428 | default: | |
429 | begin | |
430 | pec_int_en_acc_vio = 1'b0; | |
431 | begin // axis tbcall_region | |
432 | // vlint flag_system_call off | |
433 | // synopsys translate_off | |
434 | `ifdef PR_ERROR if ($time > 1 && rst_l)`PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_pec_int_en"); `endif | |
435 | // synopsys translate_on | |
436 | // vlint flag_system_call on | |
437 | end // end of tbcall_region | |
438 | end | |
439 | endcase | |
440 | end | |
441 | //----- reg_acc_vio: pec_en_err | |
442 | reg pec_en_err_acc_vio; | |
443 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
444 | pec_en_err_addr_decoded or | |
445 | daemon_transaction_in_progress) | |
446 | begin | |
447 | if (daemon_transaction_in_progress | ~pec_en_err_addr_decoded) | |
448 | pec_en_err_acc_vio = 1'b0; | |
449 | else | |
450 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
451 | // reads | |
452 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
453 | pec_en_err_acc_vio = 1'b0; | |
454 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
455 | pec_en_err_acc_vio = 1'b0; | |
456 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
457 | pec_en_err_acc_vio = 1'b0; | |
458 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
459 | pec_en_err_acc_vio = 1'b0; | |
460 | // writes | |
461 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
462 | pec_en_err_acc_vio = 1'b0; | |
463 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
464 | pec_en_err_acc_vio = 1'b0; | |
465 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
466 | pec_en_err_acc_vio = 1'b0; | |
467 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
468 | pec_en_err_acc_vio = 1'b0; | |
469 | ||
470 | default: | |
471 | begin | |
472 | pec_en_err_acc_vio = 1'b0; | |
473 | begin // axis tbcall_region | |
474 | // vlint flag_system_call off | |
475 | // synopsys translate_off | |
476 | `ifdef PR_ERROR if ($time > 1 && rst_l)`PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_pec_en_err"); `endif | |
477 | // synopsys translate_on | |
478 | // vlint flag_system_call on | |
479 | end // end of tbcall_region | |
480 | end | |
481 | endcase | |
482 | end | |
483 | //----- reg_acc_vio: ilu_diagnos | |
484 | reg ilu_diagnos_acc_vio; | |
485 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
486 | ilu_diagnos_addr_decoded or | |
487 | daemon_transaction_in_progress) | |
488 | begin | |
489 | if (daemon_transaction_in_progress | ~ilu_diagnos_addr_decoded) | |
490 | ilu_diagnos_acc_vio = 1'b0; | |
491 | else | |
492 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
493 | // reads | |
494 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
495 | ilu_diagnos_acc_vio = 1'b0; | |
496 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
497 | ilu_diagnos_acc_vio = 1'b0; | |
498 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
499 | ilu_diagnos_acc_vio = 1'b0; | |
500 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
501 | ilu_diagnos_acc_vio = 1'b0; | |
502 | // writes | |
503 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
504 | ilu_diagnos_acc_vio = 1'b0; | |
505 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
506 | ilu_diagnos_acc_vio = 1'b0; | |
507 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
508 | ilu_diagnos_acc_vio = 1'b0; | |
509 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
510 | ilu_diagnos_acc_vio = 1'b0; | |
511 | ||
512 | default: | |
513 | begin | |
514 | ilu_diagnos_acc_vio = 1'b0; | |
515 | begin // axis tbcall_region | |
516 | // vlint flag_system_call off | |
517 | // synopsys translate_off | |
518 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_ilu_cib_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_ilu_cib_csr_a_ilu_diagnos"); `endif | |
519 | // synopsys translate_on | |
520 | // vlint flag_system_call on | |
521 | end // end of tbcall_region | |
522 | end | |
523 | endcase | |
524 | end | |
525 | ||
526 | //==================================================================== | |
527 | // Status: daemon_csrbus_mapped / csrbus_acc_vio | |
528 | //==================================================================== | |
529 | //----- OUTPUT: daemon_csrbus_mapped | |
530 | assign daemon_csrbus_mapped = clocked_valid_pulse & | |
531 | ( | |
532 | ilu_log_en_addr_decoded | | |
533 | ilu_int_en_addr_decoded | | |
534 | ilu_en_err_addr_decoded | | |
535 | ilu_log_err_rw1s_alias_addr_decoded | | |
536 | ilu_log_err_rw1c_alias_addr_decoded | | |
537 | pec_int_en_addr_decoded | | |
538 | pec_en_err_addr_decoded | | |
539 | ilu_diagnos_addr_decoded | |
540 | ); | |
541 | ||
542 | ||
543 | // daemon_csrbus_mapped gets asserted after fixed number of cycles | |
544 | // after daemon_csrbus_valid become high | |
545 | /* 0in assert_together -name mapped_after_valid | |
546 | -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1)) | |
547 | -follower $0in_rising_edge(daemon_csrbus_mapped) | |
548 | -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid") | |
549 | -module dmu_ilu_cib_addr_decode | |
550 | -clock clk | |
551 | -active $0in_rising_edge(daemon_csrbus_mapped) | |
552 | */ | |
553 | ||
554 | // daemon_csrbus_mapped is a pulse | |
555 | /* 0in assert_timer -name daemon_csrbus_mapped_pulse | |
556 | -var daemon_csrbus_mapped -max 1 | |
557 | -message "daemon_csrbus_mapped pulse length is not 1" | |
558 | -module dmu_ilu_cib_addr_decode | |
559 | -clock clk | |
560 | */ | |
561 | //----- OUTPUT: csrbus_acc_vio | |
562 | assign csrbus_acc_vio = clocked_valid_pulse & | |
563 | ilu_log_en_acc_vio | | |
564 | ilu_int_en_acc_vio | | |
565 | ilu_en_err_acc_vio | | |
566 | ilu_log_err_acc_vio | | |
567 | pec_int_en_acc_vio | | |
568 | pec_en_err_acc_vio | | |
569 | ilu_diagnos_acc_vio; | |
570 | ||
571 | //==================================================================== | |
572 | // Select | |
573 | //==================================================================== | |
574 | always @(posedge clk) | |
575 | begin | |
576 | if(~rst_l) | |
577 | begin | |
578 | ilu_log_en_select_pulse <= 1'b0; | |
579 | ilu_int_en_select_pulse <= 1'b0; | |
580 | ilu_en_err_select <= 1'b0; | |
581 | ilu_log_err_select_pulse <= 1'b0; | |
582 | pec_int_en_select_pulse <= 1'b0; | |
583 | pec_en_err_select <= 1'b0; | |
584 | ilu_diagnos_select_pulse <= 1'b0; | |
585 | end | |
586 | else | |
587 | begin | |
588 | ilu_log_en_select_pulse <= | |
589 | ~ilu_log_en_acc_vio & | |
590 | clocked_valid_pulse & | |
591 | ilu_log_en_addr_decoded; | |
592 | ||
593 | ilu_int_en_select_pulse <= | |
594 | ~ilu_int_en_acc_vio & | |
595 | clocked_valid_pulse & | |
596 | ilu_int_en_addr_decoded; | |
597 | ||
598 | ilu_en_err_select <= | |
599 | ~ilu_en_err_acc_vio & | |
600 | ilu_en_err_addr_decoded; | |
601 | ||
602 | ilu_log_err_select_pulse <= | |
603 | ~ilu_log_err_acc_vio & | |
604 | clocked_valid_pulse & | |
605 | ( | |
606 | ilu_log_err_rw1c_alias_addr_decoded | | |
607 | ilu_log_err_rw1s_alias_addr_decoded | |
608 | ); | |
609 | ||
610 | pec_int_en_select_pulse <= | |
611 | ~pec_int_en_acc_vio & | |
612 | clocked_valid_pulse & | |
613 | pec_int_en_addr_decoded; | |
614 | ||
615 | pec_en_err_select <= | |
616 | ~pec_en_err_acc_vio & | |
617 | pec_en_err_addr_decoded; | |
618 | ||
619 | ilu_diagnos_select_pulse <= | |
620 | ~ilu_diagnos_acc_vio & | |
621 | clocked_valid_pulse & | |
622 | ilu_diagnos_addr_decoded; | |
623 | ||
624 | end | |
625 | end | |
626 | ||
627 | //==================================================================== | |
628 | // daemon_csrbus_wr / daemon_csrbus_wr_data | |
629 | //==================================================================== | |
630 | always @(posedge clk) | |
631 | begin | |
632 | if(~rst_l) | |
633 | begin | |
634 | daemon_csrbus_wr_out <= 1'b0; | |
635 | daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0; | |
636 | end | |
637 | else | |
638 | begin | |
639 | daemon_csrbus_wr_out <= daemon_csrbus_wr; | |
640 | daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data; | |
641 | end | |
642 | end | |
643 | ||
644 | //==================================================================== | |
645 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming | |
646 | //==================================================================== | |
647 | ||
648 | //==================================================================== | |
649 | // Alias | |
650 | //==================================================================== | |
651 | assign ilu_log_err_rw1c_alias= | |
652 | ilu_log_err_rw1c_alias_addr_decoded; | |
653 | ||
654 | assign ilu_log_err_rw1s_alias= | |
655 | ilu_log_err_rw1s_alias_addr_decoded; | |
656 | ||
657 | ||
658 | //==================================================================== | |
659 | // OUTPUT: daemon_csrbus_done (pipelining) | |
660 | //==================================================================== | |
661 | //----- DONE for internal/extern registers | |
662 | reg stage_1_daemon_csrbus_done_internal_0; | |
663 | reg stage_1_daemon_csrbus_done_internal_1; | |
664 | reg stage_2_daemon_csrbus_done_internal_0; | |
665 | ||
666 | always @(posedge clk) | |
667 | begin | |
668 | if(~rst_l) | |
669 | begin | |
670 | stage_1_daemon_csrbus_done_internal_0 <= 1'b0; | |
671 | stage_1_daemon_csrbus_done_internal_1 <= 1'b0; | |
672 | end | |
673 | else | |
674 | begin | |
675 | stage_1_daemon_csrbus_done_internal_0 <= | |
676 | ilu_log_en_select_pulse | | |
677 | ilu_int_en_select_pulse | | |
678 | ilu_log_err_select_pulse | | |
679 | pec_int_en_select_pulse | | |
680 | ilu_diagnos_select_pulse | | |
681 | ilu_en_err_select & clocked_valid_pulse; | |
682 | stage_1_daemon_csrbus_done_internal_1 <= | |
683 | pec_en_err_select & clocked_valid_pulse; | |
684 | end | |
685 | if(~rst_l) | |
686 | begin | |
687 | stage_2_daemon_csrbus_done_internal_0 <= 1'b0; | |
688 | end | |
689 | else | |
690 | begin | |
691 | stage_2_daemon_csrbus_done_internal_0 <= | |
692 | stage_1_daemon_csrbus_done_internal_0 | | |
693 | stage_1_daemon_csrbus_done_internal_1; | |
694 | end | |
695 | end | |
696 | ||
697 | //----- OUTPUT: daemon_csrbus_done | |
698 | assign daemon_csrbus_done = daemon_csrbus_valid & | |
699 | ( | |
700 | stage_2_daemon_csrbus_done_internal_0 | |
701 | ); | |
702 | ||
703 | // daemon_csrbus_done gets asserted only when csrbus_valid is high | |
704 | /* 0in assert -name daemon_csrbus_done_high | |
705 | -var daemon_csrbus_valid -active daemon_csrbus_done | |
706 | -message "csrbus_done got asserted while csrbus_valid is low" | |
707 | -module dmu_ilu_cib_addr_decode | |
708 | -clock clk | |
709 | */ | |
710 | ||
711 | // daemon_csrbus_done is a pulse | |
712 | /* 0in assert_timer -name daemon_csrbus_done_pulse | |
713 | -var daemon_csrbus_done -max 1 | |
714 | -message "csrbus_done pulse length is not 1" | |
715 | -module dmu_ilu_cib_addr_decode | |
716 | -clock clk | |
717 | */ | |
718 | ||
719 | endmodule // dmu_ilu_cib_addr_decode |