[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_ilu_cib_cim.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_ilu_cib_cim.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
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// choice is available it will apply instead, Sun elects to use only 
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// ========== Copyright Header End ============================================
module dmu_ilu_cib_cim (
			     clk,
		             rst_l,
			     
			     // ilu <-> tlu misc
			     p2d_mps,
			     p2d_ue_int,
			     p2d_ce_int,
			     p2d_oe_int,
			     
			     // to dbg port
			     dbg_ue_int,
			     dbg_ce_int,
			     dbg_oe_int,
			     
			     // D-P drain interface
//			     d2p_drain,
			     p2d_drain,
			     
			     // ilu <-> dmu misc
			     y2k_mps,
			     y2k_int_l,
		     	     
			     // internal interface
			     iil2cib_ihb_pe,
			     cib2iil_ihb_pe_drain,
			     cib2iil_pec_drain,
			     cib2eil_ihb_pe_drain,
			     cib2eil_pec_drain,
			     
			     // DCM interface
			     pec_int_en_pec_hw_read,
			     pec_int_en_pec_ilu_hw_read,
			     pec_int_en_pec_ue_hw_read,
			     pec_int_en_pec_ce_hw_read,
			     pec_int_en_pec_oe_hw_read,
			     pec_en_err_ilu_ext_read_data,
			     pec_en_err_ue_ext_read_data,
			     pec_en_err_ce_ext_read_data,
			     pec_en_err_oe_ext_read_data,
			     ilu_int_en_spare3_s_hw_read,
			     ilu_int_en_spare2_s_hw_read,
			     ilu_int_en_spare1_s_hw_read,
			     ilu_int_en_ihb_pe_s_hw_read,
			     ilu_int_en_spare3_p_hw_read,
			     ilu_int_en_spare2_p_hw_read,
			     ilu_int_en_spare1_p_hw_read,
			     ilu_int_en_ihb_pe_p_hw_read,
			     ilu_log_en_spare3_hw_read,
			     ilu_log_en_spare2_hw_read,
			     ilu_log_en_spare1_hw_read,
			     ilu_log_en_ihb_pe_hw_read,
			     ilu_en_err_spare3_s_ext_read_data,
			     ilu_en_err_spare2_s_ext_read_data,
			     ilu_en_err_spare1_s_ext_read_data,
			     ilu_en_err_ihb_pe_s_ext_read_data,
			     ilu_en_err_spare3_p_ext_read_data,
			     ilu_en_err_spare2_p_ext_read_data,
			     ilu_en_err_spare1_p_ext_read_data,
			     ilu_en_err_ihb_pe_p_ext_read_data,
			     ilu_log_err_spare3_s_hw_set,
			     ilu_log_err_spare3_s_hw_read,
			     ilu_log_err_spare2_s_hw_set,
			     ilu_log_err_spare2_s_hw_read,
			     ilu_log_err_spare1_s_hw_set,
			     ilu_log_err_spare1_s_hw_read,
			     ilu_log_err_ihb_pe_s_hw_set,
			     ilu_log_err_ihb_pe_s_hw_read,
			     ilu_log_err_spare3_p_hw_set,
			     ilu_log_err_spare3_p_hw_read,
			     ilu_log_err_spare2_p_hw_set,
			     ilu_log_err_spare2_p_hw_read,
			     ilu_log_err_spare1_p_hw_set,
			     ilu_log_err_spare1_p_hw_read,
			     ilu_log_err_ihb_pe_p_hw_set,
			     ilu_log_err_ihb_pe_p_hw_read );
  
  //synopsys sync_set_reset "rst_l"

  // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

  //------------------------------------------------------------------------
  //  Clock and Reset Signals
  //------------------------------------------------------------------------
  input		  clk;		    // input clock
  input 	  rst_l;            // soft reset
      
  //------------------------------------------------------------------------
  // ilu <-> tlu misc. interface
  //------------------------------------------------------------------------
  input [`FIRE_P2D_MPS_WDTH-1:0] p2d_mps;           // max. payld size
  input 			 p2d_ue_int;        // uncorrectable error
  input 			 p2d_ce_int;        // correctable error
  input 			 p2d_oe_int;        // other error
 
  output 			 dbg_ue_int;        // to dbg port only
  output 			 dbg_ce_int;        // to dbg port only
  output 			 dbg_oe_int;        // to dbg port only
  //------------------------------------------------------------------------
  //  
  //  DMC - PEC drain interface
  //------------------------------------------------------------------------
  input 	  p2d_drain;
//  output 	  d2p_drain;

  //------------------------------------------------------------------------
  //  ilu <-> dmu misc. interface
  //------------------------------------------------------------------------
  output [`FIRE_DLC_MPS-1:0] y2k_mps;         // max. payld size to CMU
  output 		     y2k_int_l;       // interrupt req to IMU

  //------------------------------------------------------------------------
  //  Internal module interface
  //------------------------------------------------------------------------
  input 	  iil2cib_ihb_pe;  // ingress header parity error
  output          cib2iil_ihb_pe_drain; // caused by iil2cib_ihb_pe
  output          cib2iil_pec_drain;    // caused by p2d_drain
  output          cib2eil_ihb_pe_drain;
  output          cib2eil_pec_drain;
  
  //------------------------------------------------------------------------
  //  DCM interface
  //------------------------------------------------------------------------

  input pec_int_en_pec_hw_read;  // This signal provides the current value of
                                // pec_int_en_pec.
  input  pec_int_en_pec_ilu_hw_read;  // data bus for hw loading of
                                     // pec_int_en_pec_ilu.
  input  pec_int_en_pec_ue_hw_read;  // data bus for hw loading of
                                    // pec_int_en_pec_ue.
  input  pec_int_en_pec_ce_hw_read;  // data bus for hw loading of
                                      // pec_int_en_pec_ce.
  input  pec_int_en_pec_oe_hw_read;  // data bus for hw loading of
                                    // pec_int_en_pec_oe.
  output [0:0] pec_en_err_ilu_ext_read_data;  // Ext read data (decode)
  output [0:0] pec_en_err_ue_ext_read_data;  // Ext read data (decode)
  output [0:0] pec_en_err_ce_ext_read_data;  // Ext read data (decode)
  output [0:0] pec_en_err_oe_ext_read_data;  // Ext read data (decode)

  input        ilu_int_en_spare3_s_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_spare3_s.
  input        ilu_int_en_spare2_s_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_spare2_s.
  input        ilu_int_en_spare1_s_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_spare1_s.
  input        ilu_int_en_ihb_pe_s_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_ihb_pe_s.
  input        ilu_int_en_spare3_p_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_spare3_p.
  input        ilu_int_en_spare2_p_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_spare2_p.
  input        ilu_int_en_spare1_p_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_spare1_p.
  input        ilu_int_en_ihb_pe_p_hw_read;  // This signal provides the current value
                                             // of ilu_int_en_ihb_pe_p.
  input        ilu_log_en_spare3_hw_read;  // This signal provides the current value of
                                             // ilu_log_en_spare3.
  input        ilu_log_en_spare2_hw_read;  // This signal provides the current value of
                                             // ilu_log_en_spare2.
  input        ilu_log_en_spare1_hw_read;  // This signal provides the current value of
                                   // ilu_log_en_spare1.
  input        ilu_log_en_ihb_pe_hw_read;  // This signal provides the current value of
                                   // ilu_log_en_ihb_pe.
  output [0:0] ilu_en_err_spare3_s_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_spare2_s_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_spare1_s_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_ihb_pe_s_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_spare3_p_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_spare2_p_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_spare1_p_ext_read_data;  // Ext read data (decode)
  output [0:0] ilu_en_err_ihb_pe_p_ext_read_data;  // Ext read data (decode)
  output       ilu_log_err_spare3_s_hw_set;  // Hardware set signal for
                                     // ilu_log_err_spare3_s. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_spare3_s_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_spare3_s.
  output       ilu_log_err_spare2_s_hw_set;  // Hardware set signal for
                                     // ilu_log_err_spare2_s. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_spare2_s_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_spare2_s.
  output       ilu_log_err_spare1_s_hw_set;  // Hardware set signal for
                                     // ilu_log_err_spare1_s. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_spare1_s_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_spare1_s.
  output       ilu_log_err_ihb_pe_s_hw_set;  // Hardware set signal for
                                     // ilu_log_err_ihb_pe_s. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_ihb_pe_s_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_ihb_pe_s.
  output       ilu_log_err_spare3_p_hw_set;  // Hardware set signal for
                                     // ilu_log_err_spare3_p. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_spare3_p_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_spare3_p.
  output       ilu_log_err_spare2_p_hw_set;  // Hardware set signal for
                                     // ilu_log_err_spare2_p. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_spare2_p_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_spare2_p.
  output       ilu_log_err_spare1_p_hw_set;  // Hardware set signal for
                                     // ilu_log_err_spare1_p. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_spare1_p_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_spare1_p.
  output       ilu_log_err_ihb_pe_p_hw_set;  // Hardware set signal for
                                     // ilu_log_err_ihb_pe_p. When set
                                     // ilu_log_err will be set to one.
  input        ilu_log_err_ihb_pe_p_hw_read;  // This signal provides the current value
                                      // of ilu_log_err_ihb_pe_p.
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  reg 	          y2k_int_l;
  reg             ihb_pe_drain_reg; // set & hold, used for drain signals
  reg 		  ilu_ihb_pe_reg;  // on & off, used for setting CSR bit

  reg 		  ilu_spare3_err;
  reg 		  ilu_spare2_err;
  reg 		  ilu_spare1_err;

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~
  
  // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  wire 		  pec_int;
  
  wire 		  il2il_int;
  wire 		  ue_int;
  wire 		  ce_int;
  wire 		  oe_int;
  wire 		  tlu_drain;

//  wire 		  to_drain;

  // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<

  //------------------------------------------------------------------------
  // drain state - 
  //------------------------------------------------------------------------
//  assign to_drain = iil2cib_ihb_pe | tlu_drain;

  always @ (posedge clk) begin
    if (~rst_l) ihb_pe_drain_reg <= 1'b0;
    else if (iil2cib_ihb_pe) ihb_pe_drain_reg <= 1'b1;
  end

  assign cib2iil_ihb_pe_drain = ihb_pe_drain_reg;
  assign cib2iil_pec_drain = tlu_drain; // sync flopped

  assign cib2eil_ihb_pe_drain = ihb_pe_drain_reg;
  assign cib2eil_pec_drain = tlu_drain; // tlu_drain is sync flopped
  
//  assign cib2iil_drain = drain_reg;
//  assign cib2eil_drain = drain_reg;
//  assign d2p_drain = drain_reg;

  //------------------------------------------------------------------------
  // ilu int, err
  //------------------------------------------------------------------------

  assign ilu_en_err_spare3_s_ext_read_data = ilu_int_en_spare3_s_hw_read & 
	                                     ilu_log_err_spare3_s_hw_read;
  assign ilu_en_err_spare2_s_ext_read_data = ilu_int_en_spare2_s_hw_read & 
	                                     ilu_log_err_spare2_s_hw_read;
  assign ilu_en_err_spare1_s_ext_read_data = ilu_int_en_spare1_s_hw_read & 
	                                     ilu_log_err_spare1_s_hw_read;
  assign ilu_en_err_ihb_pe_s_ext_read_data = ilu_int_en_ihb_pe_s_hw_read & 
	                                     ilu_log_err_ihb_pe_s_hw_read;
  assign ilu_en_err_spare3_p_ext_read_data = ilu_int_en_spare3_p_hw_read & 
	                                     ilu_log_err_spare3_p_hw_read;
  assign ilu_en_err_spare2_p_ext_read_data = ilu_int_en_spare2_p_hw_read & 
	                                     ilu_log_err_spare2_p_hw_read;
  assign ilu_en_err_spare1_p_ext_read_data = ilu_int_en_spare1_p_hw_read & 
	                                     ilu_log_err_spare1_p_hw_read;
  assign ilu_en_err_ihb_pe_p_ext_read_data = ilu_int_en_ihb_pe_p_hw_read & 
	                                     ilu_log_err_ihb_pe_p_hw_read;

  always @ (posedge clk) begin // iil2cib_ihb_pe is not flopped in iil
    if (~rst_l) ilu_ihb_pe_reg <= 1'b0;
    else if (iil2cib_ihb_pe) ilu_ihb_pe_reg <= 1'b1;
    else ilu_ihb_pe_reg <= 1'b0;
  end

  always @ (posedge clk) begin
    if (~rst_l) begin
      ilu_spare3_err <= 1'b0;
      ilu_spare2_err <= 1'b0;
      ilu_spare1_err <= 1'b0;
    end
    else begin
      ilu_spare3_err <= 1'b0;
      ilu_spare2_err <= 1'b0;
      ilu_spare1_err <= 1'b0;
    end
  end
       
  assign ilu_log_err_spare3_s_hw_set = ilu_log_err_spare3_p_hw_read & ilu_spare3_err
	                               & ilu_log_en_spare3_hw_read;
  assign ilu_log_err_spare2_s_hw_set = ilu_log_err_spare2_p_hw_read & ilu_spare2_err
                                       & ilu_log_en_spare2_hw_read;
  assign ilu_log_err_spare1_s_hw_set = ilu_log_err_spare1_p_hw_read & ilu_spare1_err
	                               & ilu_log_en_spare1_hw_read;
  assign ilu_log_err_ihb_pe_s_hw_set = ilu_log_err_ihb_pe_p_hw_read & ilu_ihb_pe_reg
	                               & ilu_log_en_ihb_pe_hw_read;
  
  assign ilu_log_err_spare3_p_hw_set = ~ilu_log_err_spare3_p_hw_read & ilu_spare3_err
	                               & ilu_log_en_spare3_hw_read;
  assign ilu_log_err_spare2_p_hw_set = ~ilu_log_err_spare2_p_hw_read & ilu_spare2_err
                                       & ilu_log_en_spare2_hw_read;
  assign ilu_log_err_spare1_p_hw_set = ~ilu_log_err_spare1_p_hw_read & ilu_spare1_err
	                               & ilu_log_en_spare1_hw_read;
  assign ilu_log_err_ihb_pe_p_hw_set = ~ilu_log_err_ihb_pe_p_hw_read & ilu_ihb_pe_reg
	                               & ilu_log_en_ihb_pe_hw_read;

  //------------------------------------------------------------------------
  // PEC core int, err
  //------------------------------------------------------------------------
  assign il2il_int = ilu_en_err_spare3_s_ext_read_data |
	 ilu_en_err_spare2_s_ext_read_data |
	 ilu_en_err_spare1_s_ext_read_data |
	 ilu_en_err_ihb_pe_s_ext_read_data |
	 ilu_en_err_spare3_p_ext_read_data |
	 ilu_en_err_spare2_p_ext_read_data |
	 ilu_en_err_spare1_p_ext_read_data |
	 ilu_en_err_ihb_pe_p_ext_read_data;
  
  assign pec_en_err_ilu_ext_read_data = pec_int_en_pec_hw_read &
	 pec_int_en_pec_ilu_hw_read &
	 il2il_int;

  assign pec_en_err_ue_ext_read_data = pec_int_en_pec_hw_read & 
	 pec_int_en_pec_ue_hw_read &
	 ue_int;

  assign pec_en_err_ce_ext_read_data = pec_int_en_pec_hw_read & 
	 pec_int_en_pec_ce_hw_read &
	 ce_int;

  assign pec_en_err_oe_ext_read_data = pec_int_en_pec_hw_read & 
	 pec_int_en_pec_oe_hw_read &
	 oe_int;

  assign pec_int = pec_en_err_ilu_ext_read_data |
	 pec_en_err_ue_ext_read_data |
	 pec_en_err_ce_ext_read_data |
	 pec_en_err_oe_ext_read_data;

  always @ (posedge clk) begin
    if (!rst_l) begin
      y2k_int_l <= 1'b1;
    end
    else begin
      y2k_int_l <= ~pec_int;
    end
  end
  
//BP N2 3-10-05 add signals to dbg after synchronizers  
assign	dbg_ue_int	= ue_int;
assign	dbg_ce_int	= ce_int;
assign	dbg_oe_int	= oe_int;
  // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

  // sync-flop instantiations for p2d_ue_int
//  pcie_common_sync_flop #(1) ue_int_sync_flop(
//                                              .clk(clk),
//                                              .din(p2d_ue_int),
//                                              .dout(ue_int));
  cl_a1_clksyncff_4x ue_int_sync_flop ( .d(p2d_ue_int), .si(1'b0), .q( ue_int), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );


  // sync-flop instantiations for p2d_ce_int
//  pcie_common_sync_flop #(1) ce_int_sync_flop(
//                                              .clk(clk),
//                                              .din(p2d_ce_int),
//                                              .dout(ce_int));
 cl_a1_clksyncff_4x ce_int_sync_flop ( .d(p2d_ce_int), .si(1'b0), .q( ce_int), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );


  // sync-flop instantiations for p2d_oe_int
//  pcie_common_sync_flop #(1) oe_int_sync_flop(
//                                              .clk(clk),
//                                              .din(p2d_oe_int),
//                                              .dout(oe_int));
  cl_a1_clksyncff_4x oe_int_sync_flop ( .d(p2d_oe_int), .si(1'b0), .q( oe_int), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );


  // sync-flop instantiations for p2d_mps
//  pcie_common_sync_flop #(`FIRE_P2D_MPS_WDTH) mps_sync_flop(
//							    .clk(clk),
//							    .din(p2d_mps),
//							    .dout(y2k_mps));
  cl_a1_clksyncff_4x mps_sync_flop_2 ( .d(p2d_mps[2]), .si(1'b0), .q( y2k_mps[2]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x mps_sync_flop_1 ( .d(p2d_mps[1]), .si(1'b0), .q( y2k_mps[1]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x mps_sync_flop_0 ( .d(p2d_mps[0]), .si(1'b0), .q( y2k_mps[0]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );

  // sync-flop instantiations for p2d_drain
//  pcie_common_sync_flop #(1) drain_sync_flop(
//                                              .clk(clk),
//                                              .din(p2d_drain),
//                                              .dout(tlu_drain));
  cl_a1_clksyncff_4x drain_sync_flop ( .d(p2d_drain), .si(1'b0), .q( tlu_drain), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );

					      
endmodule // dmu_ilu_cib_cim
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_ilu_cib_cim.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
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	34	// ========== Copyright Header End ============================================
	35	module dmu_ilu_cib_cim (
	36	clk,
	37	rst_l,
	38
	39	// ilu <-> tlu misc
	40	p2d_mps,
	41	p2d_ue_int,
	42	p2d_ce_int,
	43	p2d_oe_int,
	44
	45	// to dbg port
	46	dbg_ue_int,
	47	dbg_ce_int,
	48	dbg_oe_int,
	49
	50	// D-P drain interface
	51	// d2p_drain,
	52	p2d_drain,
	53
	54	// ilu <-> dmu misc
	55	y2k_mps,
	56	y2k_int_l,
	57
	58	// internal interface
	59	iil2cib_ihb_pe,
	60	cib2iil_ihb_pe_drain,
	61	cib2iil_pec_drain,
	62	cib2eil_ihb_pe_drain,
	63	cib2eil_pec_drain,
	64
65	// DCM interface
66	pec_int_en_pec_hw_read,
67	pec_int_en_pec_ilu_hw_read,
68	pec_int_en_pec_ue_hw_read,
69	pec_int_en_pec_ce_hw_read,
70	pec_int_en_pec_oe_hw_read,
71	pec_en_err_ilu_ext_read_data,
72	pec_en_err_ue_ext_read_data,
73	pec_en_err_ce_ext_read_data,
74	pec_en_err_oe_ext_read_data,
75	ilu_int_en_spare3_s_hw_read,
76	ilu_int_en_spare2_s_hw_read,
77	ilu_int_en_spare1_s_hw_read,
78	ilu_int_en_ihb_pe_s_hw_read,
79	ilu_int_en_spare3_p_hw_read,
80	ilu_int_en_spare2_p_hw_read,
81	ilu_int_en_spare1_p_hw_read,
82	ilu_int_en_ihb_pe_p_hw_read,
83	ilu_log_en_spare3_hw_read,
84	ilu_log_en_spare2_hw_read,
85	ilu_log_en_spare1_hw_read,
86	ilu_log_en_ihb_pe_hw_read,
87	ilu_en_err_spare3_s_ext_read_data,
88	ilu_en_err_spare2_s_ext_read_data,
89	ilu_en_err_spare1_s_ext_read_data,
90	ilu_en_err_ihb_pe_s_ext_read_data,
91	ilu_en_err_spare3_p_ext_read_data,
92	ilu_en_err_spare2_p_ext_read_data,
93	ilu_en_err_spare1_p_ext_read_data,
94	ilu_en_err_ihb_pe_p_ext_read_data,
95	ilu_log_err_spare3_s_hw_set,
96	ilu_log_err_spare3_s_hw_read,
97	ilu_log_err_spare2_s_hw_set,
98	ilu_log_err_spare2_s_hw_read,
99	ilu_log_err_spare1_s_hw_set,
100	ilu_log_err_spare1_s_hw_read,
101	ilu_log_err_ihb_pe_s_hw_set,
102	ilu_log_err_ihb_pe_s_hw_read,
103	ilu_log_err_spare3_p_hw_set,
104	ilu_log_err_spare3_p_hw_read,
105	ilu_log_err_spare2_p_hw_set,
106	ilu_log_err_spare2_p_hw_read,
107	ilu_log_err_spare1_p_hw_set,
108	ilu_log_err_spare1_p_hw_read,
109	ilu_log_err_ihb_pe_p_hw_set,
110	ilu_log_err_ihb_pe_p_hw_read );
111
112	//synopsys sync_set_reset "rst_l"
113
114	// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
115
116	//------------------------------------------------------------------------
117	// Clock and Reset Signals
118	//------------------------------------------------------------------------
119	input clk; // input clock
120	input rst_l; // soft reset
121
122	//------------------------------------------------------------------------
123	// ilu <-> tlu misc. interface
124	//------------------------------------------------------------------------
125	input [`FIRE_P2D_MPS_WDTH-1:0] p2d_mps; // max. payld size
126	input p2d_ue_int; // uncorrectable error
127	input p2d_ce_int; // correctable error
128	input p2d_oe_int; // other error
129
130	output dbg_ue_int; // to dbg port only
131	output dbg_ce_int; // to dbg port only
132	output dbg_oe_int; // to dbg port only
133	//------------------------------------------------------------------------
134	//
135	// DMC - PEC drain interface
136	//------------------------------------------------------------------------
137	input p2d_drain;
138	// output d2p_drain;
139
140	//------------------------------------------------------------------------
141	// ilu <-> dmu misc. interface
142	//------------------------------------------------------------------------
143	output [`FIRE_DLC_MPS-1:0] y2k_mps; // max. payld size to CMU
144	output y2k_int_l; // interrupt req to IMU
145
146	//------------------------------------------------------------------------
147	// Internal module interface
148	//------------------------------------------------------------------------
149	input iil2cib_ihb_pe; // ingress header parity error
150	output cib2iil_ihb_pe_drain; // caused by iil2cib_ihb_pe
151	output cib2iil_pec_drain; // caused by p2d_drain
152	output cib2eil_ihb_pe_drain;
153	output cib2eil_pec_drain;
154
155	//------------------------------------------------------------------------
156	// DCM interface
157	//------------------------------------------------------------------------
158
159	input pec_int_en_pec_hw_read; // This signal provides the current value of
160	// pec_int_en_pec.
161	input pec_int_en_pec_ilu_hw_read; // data bus for hw loading of
162	// pec_int_en_pec_ilu.
163	input pec_int_en_pec_ue_hw_read; // data bus for hw loading of
164	// pec_int_en_pec_ue.
165	input pec_int_en_pec_ce_hw_read; // data bus for hw loading of
166	// pec_int_en_pec_ce.
167	input pec_int_en_pec_oe_hw_read; // data bus for hw loading of
168	// pec_int_en_pec_oe.
169	output [0:0] pec_en_err_ilu_ext_read_data; // Ext read data (decode)
170	output [0:0] pec_en_err_ue_ext_read_data; // Ext read data (decode)
171	output [0:0] pec_en_err_ce_ext_read_data; // Ext read data (decode)
172	output [0:0] pec_en_err_oe_ext_read_data; // Ext read data (decode)
173
174	input ilu_int_en_spare3_s_hw_read; // This signal provides the current value
175	// of ilu_int_en_spare3_s.
176	input ilu_int_en_spare2_s_hw_read; // This signal provides the current value
177	// of ilu_int_en_spare2_s.
178	input ilu_int_en_spare1_s_hw_read; // This signal provides the current value
179	// of ilu_int_en_spare1_s.
180	input ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value
181	// of ilu_int_en_ihb_pe_s.
182	input ilu_int_en_spare3_p_hw_read; // This signal provides the current value
183	// of ilu_int_en_spare3_p.
184	input ilu_int_en_spare2_p_hw_read; // This signal provides the current value
185	// of ilu_int_en_spare2_p.
186	input ilu_int_en_spare1_p_hw_read; // This signal provides the current value
187	// of ilu_int_en_spare1_p.
188	input ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value
189	// of ilu_int_en_ihb_pe_p.
190	input ilu_log_en_spare3_hw_read; // This signal provides the current value of
191	// ilu_log_en_spare3.
192	input ilu_log_en_spare2_hw_read; // This signal provides the current value of
193	// ilu_log_en_spare2.
194	input ilu_log_en_spare1_hw_read; // This signal provides the current value of
195	// ilu_log_en_spare1.
196	input ilu_log_en_ihb_pe_hw_read; // This signal provides the current value of
197	// ilu_log_en_ihb_pe.
198	output [0:0] ilu_en_err_spare3_s_ext_read_data; // Ext read data (decode)
199	output [0:0] ilu_en_err_spare2_s_ext_read_data; // Ext read data (decode)
200	output [0:0] ilu_en_err_spare1_s_ext_read_data; // Ext read data (decode)
201	output [0:0] ilu_en_err_ihb_pe_s_ext_read_data; // Ext read data (decode)
202	output [0:0] ilu_en_err_spare3_p_ext_read_data; // Ext read data (decode)
203	output [0:0] ilu_en_err_spare2_p_ext_read_data; // Ext read data (decode)
204	output [0:0] ilu_en_err_spare1_p_ext_read_data; // Ext read data (decode)
205	output [0:0] ilu_en_err_ihb_pe_p_ext_read_data; // Ext read data (decode)
206	output ilu_log_err_spare3_s_hw_set; // Hardware set signal for
207	// ilu_log_err_spare3_s. When set
208	// ilu_log_err will be set to one.
209	input ilu_log_err_spare3_s_hw_read; // This signal provides the current value
210	// of ilu_log_err_spare3_s.
211	output ilu_log_err_spare2_s_hw_set; // Hardware set signal for
212	// ilu_log_err_spare2_s. When set
213	// ilu_log_err will be set to one.
214	input ilu_log_err_spare2_s_hw_read; // This signal provides the current value
215	// of ilu_log_err_spare2_s.
216	output ilu_log_err_spare1_s_hw_set; // Hardware set signal for
217	// ilu_log_err_spare1_s. When set
218	// ilu_log_err will be set to one.
219	input ilu_log_err_spare1_s_hw_read; // This signal provides the current value
220	// of ilu_log_err_spare1_s.
221	output ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for
222	// ilu_log_err_ihb_pe_s. When set
223	// ilu_log_err will be set to one.
224	input ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value
225	// of ilu_log_err_ihb_pe_s.
226	output ilu_log_err_spare3_p_hw_set; // Hardware set signal for
227	// ilu_log_err_spare3_p. When set
228	// ilu_log_err will be set to one.
229	input ilu_log_err_spare3_p_hw_read; // This signal provides the current value
230	// of ilu_log_err_spare3_p.
231	output ilu_log_err_spare2_p_hw_set; // Hardware set signal for
232	// ilu_log_err_spare2_p. When set
233	// ilu_log_err will be set to one.
234	input ilu_log_err_spare2_p_hw_read; // This signal provides the current value
235	// of ilu_log_err_spare2_p.
236	output ilu_log_err_spare1_p_hw_set; // Hardware set signal for
237	// ilu_log_err_spare1_p. When set
238	// ilu_log_err will be set to one.
239	input ilu_log_err_spare1_p_hw_read; // This signal provides the current value
240	// of ilu_log_err_spare1_p.
241	output ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for
242	// ilu_log_err_ihb_pe_p. When set
243	// ilu_log_err will be set to one.
244	input ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value
245	// of ilu_log_err_ihb_pe_p.
246
247	// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
248
249	// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
250	reg y2k_int_l;
251	reg ihb_pe_drain_reg; // set & hold, used for drain signals
252	reg ilu_ihb_pe_reg; // on & off, used for setting CSR bit
253
254	reg ilu_spare3_err;
255	reg ilu_spare2_err;
256	reg ilu_spare1_err;
257
258	// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~
259
260	// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
261	wire pec_int;
262
263	wire il2il_int;
264	wire ue_int;
265	wire ce_int;
266	wire oe_int;
267	wire tlu_drain;
268
269	// wire to_drain;
270
271	// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
272
273	//------------------------------------------------------------------------
274	// drain state -
275	//------------------------------------------------------------------------
276	// assign to_drain = iil2cib_ihb_pe \| tlu_drain;
277
278	always @ (posedge clk) begin
279	if (~rst_l) ihb_pe_drain_reg <= 1'b0;
280	else if (iil2cib_ihb_pe) ihb_pe_drain_reg <= 1'b1;
281	end
282
283	assign cib2iil_ihb_pe_drain = ihb_pe_drain_reg;
284	assign cib2iil_pec_drain = tlu_drain; // sync flopped
285
286	assign cib2eil_ihb_pe_drain = ihb_pe_drain_reg;
287	assign cib2eil_pec_drain = tlu_drain; // tlu_drain is sync flopped
288
289	// assign cib2iil_drain = drain_reg;
290	// assign cib2eil_drain = drain_reg;
291	// assign d2p_drain = drain_reg;
292
293	//------------------------------------------------------------------------
294	// ilu int, err
295	//------------------------------------------------------------------------
296
297	assign ilu_en_err_spare3_s_ext_read_data = ilu_int_en_spare3_s_hw_read &
298	ilu_log_err_spare3_s_hw_read;
299	assign ilu_en_err_spare2_s_ext_read_data = ilu_int_en_spare2_s_hw_read &
300	ilu_log_err_spare2_s_hw_read;
301	assign ilu_en_err_spare1_s_ext_read_data = ilu_int_en_spare1_s_hw_read &
302	ilu_log_err_spare1_s_hw_read;
303	assign ilu_en_err_ihb_pe_s_ext_read_data = ilu_int_en_ihb_pe_s_hw_read &
304	ilu_log_err_ihb_pe_s_hw_read;
305	assign ilu_en_err_spare3_p_ext_read_data = ilu_int_en_spare3_p_hw_read &
306	ilu_log_err_spare3_p_hw_read;
307	assign ilu_en_err_spare2_p_ext_read_data = ilu_int_en_spare2_p_hw_read &
308	ilu_log_err_spare2_p_hw_read;
309	assign ilu_en_err_spare1_p_ext_read_data = ilu_int_en_spare1_p_hw_read &
310	ilu_log_err_spare1_p_hw_read;
311	assign ilu_en_err_ihb_pe_p_ext_read_data = ilu_int_en_ihb_pe_p_hw_read &
312	ilu_log_err_ihb_pe_p_hw_read;
313
314	always @ (posedge clk) begin // iil2cib_ihb_pe is not flopped in iil
315	if (~rst_l) ilu_ihb_pe_reg <= 1'b0;
316	else if (iil2cib_ihb_pe) ilu_ihb_pe_reg <= 1'b1;
317	else ilu_ihb_pe_reg <= 1'b0;
318	end
319
320	always @ (posedge clk) begin
321	if (~rst_l) begin
322	ilu_spare3_err <= 1'b0;
323	ilu_spare2_err <= 1'b0;
324	ilu_spare1_err <= 1'b0;
325	end
326	else begin
327	ilu_spare3_err <= 1'b0;
328	ilu_spare2_err <= 1'b0;
329	ilu_spare1_err <= 1'b0;
330	end
331	end
332
333	assign ilu_log_err_spare3_s_hw_set = ilu_log_err_spare3_p_hw_read & ilu_spare3_err
334	& ilu_log_en_spare3_hw_read;
335	assign ilu_log_err_spare2_s_hw_set = ilu_log_err_spare2_p_hw_read & ilu_spare2_err
336	& ilu_log_en_spare2_hw_read;
337	assign ilu_log_err_spare1_s_hw_set = ilu_log_err_spare1_p_hw_read & ilu_spare1_err
338	& ilu_log_en_spare1_hw_read;
339	assign ilu_log_err_ihb_pe_s_hw_set = ilu_log_err_ihb_pe_p_hw_read & ilu_ihb_pe_reg
340	& ilu_log_en_ihb_pe_hw_read;
341
342	assign ilu_log_err_spare3_p_hw_set = ~ilu_log_err_spare3_p_hw_read & ilu_spare3_err
343	& ilu_log_en_spare3_hw_read;
344	assign ilu_log_err_spare2_p_hw_set = ~ilu_log_err_spare2_p_hw_read & ilu_spare2_err
345	& ilu_log_en_spare2_hw_read;
346	assign ilu_log_err_spare1_p_hw_set = ~ilu_log_err_spare1_p_hw_read & ilu_spare1_err
347	& ilu_log_en_spare1_hw_read;
348	assign ilu_log_err_ihb_pe_p_hw_set = ~ilu_log_err_ihb_pe_p_hw_read & ilu_ihb_pe_reg
349	& ilu_log_en_ihb_pe_hw_read;
350
351	//------------------------------------------------------------------------
352	// PEC core int, err
353	//------------------------------------------------------------------------
354	assign il2il_int = ilu_en_err_spare3_s_ext_read_data \|
355	ilu_en_err_spare2_s_ext_read_data \|
356	ilu_en_err_spare1_s_ext_read_data \|
357	ilu_en_err_ihb_pe_s_ext_read_data \|
358	ilu_en_err_spare3_p_ext_read_data \|
359	ilu_en_err_spare2_p_ext_read_data \|
360	ilu_en_err_spare1_p_ext_read_data \|
361	ilu_en_err_ihb_pe_p_ext_read_data;
362
363	assign pec_en_err_ilu_ext_read_data = pec_int_en_pec_hw_read &
364	pec_int_en_pec_ilu_hw_read &
365	il2il_int;
366
367	assign pec_en_err_ue_ext_read_data = pec_int_en_pec_hw_read &
368	pec_int_en_pec_ue_hw_read &
369	ue_int;
370
371	assign pec_en_err_ce_ext_read_data = pec_int_en_pec_hw_read &
372	pec_int_en_pec_ce_hw_read &
373	ce_int;
374
375	assign pec_en_err_oe_ext_read_data = pec_int_en_pec_hw_read &
376	pec_int_en_pec_oe_hw_read &
377	oe_int;
378
379	assign pec_int = pec_en_err_ilu_ext_read_data \|
380	pec_en_err_ue_ext_read_data \|
381	pec_en_err_ce_ext_read_data \|
382	pec_en_err_oe_ext_read_data;
383
384	always @ (posedge clk) begin
385	if (!rst_l) begin
386	y2k_int_l <= 1'b1;
387	end
388	else begin
389	y2k_int_l <= ~pec_int;
390	end
391	end
392
393	//BP N2 3-10-05 add signals to dbg after synchronizers
394	assign dbg_ue_int = ue_int;
395	assign dbg_ce_int = ce_int;
396	assign dbg_oe_int = oe_int;
397	// >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
398
399	// sync-flop instantiations for p2d_ue_int
400	// pcie_common_sync_flop #(1) ue_int_sync_flop(
401	// .clk(clk),
402	// .din(p2d_ue_int),
403	// .dout(ue_int));
404	cl_a1_clksyncff_4x ue_int_sync_flop ( .d(p2d_ue_int), .si(1'b0), .q( ue_int), .so(),
405	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
406
407
408	// sync-flop instantiations for p2d_ce_int
409	// pcie_common_sync_flop #(1) ce_int_sync_flop(
410	// .clk(clk),
411	// .din(p2d_ce_int),
412	// .dout(ce_int));
413	cl_a1_clksyncff_4x ce_int_sync_flop ( .d(p2d_ce_int), .si(1'b0), .q( ce_int), .so(),
414	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
415
416
417	// sync-flop instantiations for p2d_oe_int
418	// pcie_common_sync_flop #(1) oe_int_sync_flop(
419	// .clk(clk),
420	// .din(p2d_oe_int),
421	// .dout(oe_int));
422	cl_a1_clksyncff_4x oe_int_sync_flop ( .d(p2d_oe_int), .si(1'b0), .q( oe_int), .so(),
423	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
424
425
426	// sync-flop instantiations for p2d_mps
427	// pcie_common_sync_flop #(`FIRE_P2D_MPS_WDTH) mps_sync_flop(
428	// .clk(clk),
429	// .din(p2d_mps),
430	// .dout(y2k_mps));
431	cl_a1_clksyncff_4x mps_sync_flop_2 ( .d(p2d_mps[2]), .si(1'b0), .q( y2k_mps[2]), .so(),
432	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
433	cl_a1_clksyncff_4x mps_sync_flop_1 ( .d(p2d_mps[1]), .si(1'b0), .q( y2k_mps[1]), .so(),
434	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
435	cl_a1_clksyncff_4x mps_sync_flop_0 ( .d(p2d_mps[0]), .si(1'b0), .q( y2k_mps[0]), .so(),
436	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
437
438	// sync-flop instantiations for p2d_drain
439	// pcie_common_sync_flop #(1) drain_sync_flop(
440	// .clk(clk),
441	// .din(p2d_drain),
442	// .dout(tlu_drain));
443	cl_a1_clksyncff_4x drain_sync_flop ( .d(p2d_drain), .si(1'b0), .q( tlu_drain), .so(),
444	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
445
446
447
448	endmodule // dmu_ilu_cib_cim
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