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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_ilu_cib_csr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_ilu_cib_csr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_ilu_cib_csr
36 (
37 clk,
38 csrbus_addr,
39 csrbus_wr_data,
40 csrbus_wr,
41 csrbus_valid,
42 csrbus_mapped,
43 csrbus_done,
44 csrbus_read_data,
45 por_l,
46 rst_l,
47 csrbus_src_bus,
48 csrbus_acc_vio,
49 instance_id,
50 ilu_log_en_spare3_hw_read,
51 ilu_log_en_spare2_hw_read,
52 ilu_log_en_spare1_hw_read,
53 ilu_log_en_ihb_pe_hw_read,
54 ilu_int_en_spare3_s_hw_read,
55 ilu_int_en_spare2_s_hw_read,
56 ilu_int_en_spare1_s_hw_read,
57 ilu_int_en_ihb_pe_s_hw_read,
58 ilu_int_en_spare3_p_hw_read,
59 ilu_int_en_spare2_p_hw_read,
60 ilu_int_en_spare1_p_hw_read,
61 ilu_int_en_ihb_pe_p_hw_read,
62 ilu_en_err_spare3_s_ext_read_data,
63 ilu_en_err_spare2_s_ext_read_data,
64 ilu_en_err_spare1_s_ext_read_data,
65 ilu_en_err_ihb_pe_s_ext_read_data,
66 ilu_en_err_spare3_p_ext_read_data,
67 ilu_en_err_spare2_p_ext_read_data,
68 ilu_en_err_spare1_p_ext_read_data,
69 ilu_en_err_ihb_pe_p_ext_read_data,
70 ilu_log_err_spare3_s_hw_set,
71 ilu_log_err_spare3_s_hw_read,
72 ilu_log_err_spare2_s_hw_set,
73 ilu_log_err_spare2_s_hw_read,
74 ilu_log_err_spare1_s_hw_set,
75 ilu_log_err_spare1_s_hw_read,
76 ilu_log_err_ihb_pe_s_hw_set,
77 ilu_log_err_ihb_pe_s_hw_read,
78 ilu_log_err_spare3_p_hw_set,
79 ilu_log_err_spare3_p_hw_read,
80 ilu_log_err_spare2_p_hw_set,
81 ilu_log_err_spare2_p_hw_read,
82 ilu_log_err_spare1_p_hw_set,
83 ilu_log_err_spare1_p_hw_read,
84 ilu_log_err_ihb_pe_p_hw_set,
85 ilu_log_err_ihb_pe_p_hw_read,
86 pec_int_en_pec_hw_read,
87 pec_int_en_pec_ilu_hw_read,
88 pec_int_en_pec_ue_hw_read,
89 pec_int_en_pec_ce_hw_read,
90 pec_int_en_pec_oe_hw_read,
91 pec_en_err_ilu_ext_read_data,
92 pec_en_err_ue_ext_read_data,
93 pec_en_err_ce_ext_read_data,
94 pec_en_err_oe_ext_read_data,
95 ilu_diagnos_enpll1_hw_read,
96 ilu_diagnos_enpll0_hw_read,
97 ilu_diagnos_entx7_hw_read,
98 ilu_diagnos_entx6_hw_read,
99 ilu_diagnos_entx5_hw_read,
100 ilu_diagnos_entx4_hw_read,
101 ilu_diagnos_entx3_hw_read,
102 ilu_diagnos_entx2_hw_read,
103 ilu_diagnos_entx1_hw_read,
104 ilu_diagnos_entx0_hw_read,
105 ilu_diagnos_enrx7_hw_read,
106 ilu_diagnos_enrx6_hw_read,
107 ilu_diagnos_enrx5_hw_read,
108 ilu_diagnos_enrx4_hw_read,
109 ilu_diagnos_enrx3_hw_read,
110 ilu_diagnos_enrx2_hw_read,
111 ilu_diagnos_enrx1_hw_read,
112 ilu_diagnos_enrx0_hw_read,
113 ilu_diagnos_edi_par_hw_read,
114 ilu_diagnos_ehi_par_hw_read,
115 ilu_diagnos_edi_trig_hw_clr,
116 ilu_diagnos_edi_trig_hw_read,
117 ilu_diagnos_ehi_trig_hw_clr,
118 ilu_diagnos_ehi_trig_hw_read,
119 ilu_diagnos_rate_scale_hw_read
120 );
121
122//====================================================
123// Polarity declarations
124//====================================================
125input clk; // Clock signal
126input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
127input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
128input csrbus_wr; // Read/Write signal
129input csrbus_valid; // Valid address
130output csrbus_mapped; // Address is mapped
131output csrbus_done; // Operation is done
132output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
133input por_l; // Reset signal
134input rst_l; // Reset signal
135input [1:0] csrbus_src_bus; // Source bus
136output csrbus_acc_vio; // Violation signal
137input instance_id; // Instance ID
138output ilu_log_en_spare3_hw_read; // This signal provides the current value of
139 // ilu_log_en_spare3.
140output ilu_log_en_spare2_hw_read; // This signal provides the current value of
141 // ilu_log_en_spare2.
142output ilu_log_en_spare1_hw_read; // This signal provides the current value of
143 // ilu_log_en_spare1.
144output ilu_log_en_ihb_pe_hw_read; // This signal provides the current value of
145 // ilu_log_en_ihb_pe.
146output ilu_int_en_spare3_s_hw_read; // This signal provides the current value
147 // of ilu_int_en_spare3_s.
148output ilu_int_en_spare2_s_hw_read; // This signal provides the current value
149 // of ilu_int_en_spare2_s.
150output ilu_int_en_spare1_s_hw_read; // This signal provides the current value
151 // of ilu_int_en_spare1_s.
152output ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value
153 // of ilu_int_en_ihb_pe_s.
154output ilu_int_en_spare3_p_hw_read; // This signal provides the current value
155 // of ilu_int_en_spare3_p.
156output ilu_int_en_spare2_p_hw_read; // This signal provides the current value
157 // of ilu_int_en_spare2_p.
158output ilu_int_en_spare1_p_hw_read; // This signal provides the current value
159 // of ilu_int_en_spare1_p.
160output ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value
161 // of ilu_int_en_ihb_pe_p.
162input [0:0] ilu_en_err_spare3_s_ext_read_data; // Ext read data (decode)
163input [0:0] ilu_en_err_spare2_s_ext_read_data; // Ext read data (decode)
164input [0:0] ilu_en_err_spare1_s_ext_read_data; // Ext read data (decode)
165input [0:0] ilu_en_err_ihb_pe_s_ext_read_data; // Ext read data (decode)
166input [0:0] ilu_en_err_spare3_p_ext_read_data; // Ext read data (decode)
167input [0:0] ilu_en_err_spare2_p_ext_read_data; // Ext read data (decode)
168input [0:0] ilu_en_err_spare1_p_ext_read_data; // Ext read data (decode)
169input [0:0] ilu_en_err_ihb_pe_p_ext_read_data; // Ext read data (decode)
170input ilu_log_err_spare3_s_hw_set; // Hardware set signal for
171 // ilu_log_err_spare3_s. When set
172 // ilu_log_err will be set to one.
173output ilu_log_err_spare3_s_hw_read; // This signal provides the current value
174 // of ilu_log_err_spare3_s.
175input ilu_log_err_spare2_s_hw_set; // Hardware set signal for
176 // ilu_log_err_spare2_s. When set
177 // ilu_log_err will be set to one.
178output ilu_log_err_spare2_s_hw_read; // This signal provides the current value
179 // of ilu_log_err_spare2_s.
180input ilu_log_err_spare1_s_hw_set; // Hardware set signal for
181 // ilu_log_err_spare1_s. When set
182 // ilu_log_err will be set to one.
183output ilu_log_err_spare1_s_hw_read; // This signal provides the current value
184 // of ilu_log_err_spare1_s.
185input ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for
186 // ilu_log_err_ihb_pe_s. When set
187 // ilu_log_err will be set to one.
188output ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value
189 // of ilu_log_err_ihb_pe_s.
190input ilu_log_err_spare3_p_hw_set; // Hardware set signal for
191 // ilu_log_err_spare3_p. When set
192 // ilu_log_err will be set to one.
193output ilu_log_err_spare3_p_hw_read; // This signal provides the current value
194 // of ilu_log_err_spare3_p.
195input ilu_log_err_spare2_p_hw_set; // Hardware set signal for
196 // ilu_log_err_spare2_p. When set
197 // ilu_log_err will be set to one.
198output ilu_log_err_spare2_p_hw_read; // This signal provides the current value
199 // of ilu_log_err_spare2_p.
200input ilu_log_err_spare1_p_hw_set; // Hardware set signal for
201 // ilu_log_err_spare1_p. When set
202 // ilu_log_err will be set to one.
203output ilu_log_err_spare1_p_hw_read; // This signal provides the current value
204 // of ilu_log_err_spare1_p.
205input ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for
206 // ilu_log_err_ihb_pe_p. When set
207 // ilu_log_err will be set to one.
208output ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value
209 // of ilu_log_err_ihb_pe_p.
210output pec_int_en_pec_hw_read; // This signal provides the current value of
211 // pec_int_en_pec.
212output pec_int_en_pec_ilu_hw_read; // This signal provides the current value of
213 // pec_int_en_pec_ilu.
214output pec_int_en_pec_ue_hw_read; // This signal provides the current value of
215 // pec_int_en_pec_ue.
216output pec_int_en_pec_ce_hw_read; // This signal provides the current value of
217 // pec_int_en_pec_ce.
218output pec_int_en_pec_oe_hw_read; // This signal provides the current value of
219 // pec_int_en_pec_oe.
220input [0:0] pec_en_err_ilu_ext_read_data; // Ext read data (decode)
221input [0:0] pec_en_err_ue_ext_read_data; // Ext read data (decode)
222input [0:0] pec_en_err_ce_ext_read_data; // Ext read data (decode)
223input [0:0] pec_en_err_oe_ext_read_data; // Ext read data (decode)
224output ilu_diagnos_enpll1_hw_read; // This signal provides the current value of
225 // ilu_diagnos_enpll1.
226output ilu_diagnos_enpll0_hw_read; // This signal provides the current value of
227 // ilu_diagnos_enpll0.
228output ilu_diagnos_entx7_hw_read; // This signal provides the current value of
229 // ilu_diagnos_entx7.
230output ilu_diagnos_entx6_hw_read; // This signal provides the current value of
231 // ilu_diagnos_entx6.
232output ilu_diagnos_entx5_hw_read; // This signal provides the current value of
233 // ilu_diagnos_entx5.
234output ilu_diagnos_entx4_hw_read; // This signal provides the current value of
235 // ilu_diagnos_entx4.
236output ilu_diagnos_entx3_hw_read; // This signal provides the current value of
237 // ilu_diagnos_entx3.
238output ilu_diagnos_entx2_hw_read; // This signal provides the current value of
239 // ilu_diagnos_entx2.
240output ilu_diagnos_entx1_hw_read; // This signal provides the current value of
241 // ilu_diagnos_entx1.
242output ilu_diagnos_entx0_hw_read; // This signal provides the current value of
243 // ilu_diagnos_entx0.
244output ilu_diagnos_enrx7_hw_read; // This signal provides the current value of
245 // ilu_diagnos_enrx7.
246output ilu_diagnos_enrx6_hw_read; // This signal provides the current value of
247 // ilu_diagnos_enrx6.
248output ilu_diagnos_enrx5_hw_read; // This signal provides the current value of
249 // ilu_diagnos_enrx5.
250output ilu_diagnos_enrx4_hw_read; // This signal provides the current value of
251 // ilu_diagnos_enrx4.
252output ilu_diagnos_enrx3_hw_read; // This signal provides the current value of
253 // ilu_diagnos_enrx3.
254output ilu_diagnos_enrx2_hw_read; // This signal provides the current value of
255 // ilu_diagnos_enrx2.
256output ilu_diagnos_enrx1_hw_read; // This signal provides the current value of
257 // ilu_diagnos_enrx1.
258output ilu_diagnos_enrx0_hw_read; // This signal provides the current value of
259 // ilu_diagnos_enrx0.
260output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read;
261 // This signal provides the current value of ilu_diagnos_edi_par.
262output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read;
263 // This signal provides the current value of ilu_diagnos_ehi_par.
264input ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for
265 // ilu_diagnos_edi_trig. When set
266 // ilu_diagnos will be set to zero.
267output ilu_diagnos_edi_trig_hw_read; // This signal provides the current value
268 // of ilu_diagnos_edi_trig.
269input ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for
270 // ilu_diagnos_ehi_trig. When set
271 // ilu_diagnos will be set to zero.
272output ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value
273 // of ilu_diagnos_ehi_trig.
274output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC] ilu_diagnos_rate_scale_hw_read;
275 // This signal provides the current value of ilu_diagnos_rate_scale.
276
277//====================================================
278// Type declarations
279//====================================================
280wire clk; // Clock signal
281wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
282wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
283wire csrbus_wr; // Read/Write signal
284wire csrbus_valid; // Valid address
285wire csrbus_mapped; // Address is mapped
286wire csrbus_done; // Operation is done
287wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
288wire por_l; // Reset signal
289wire rst_l; // Reset signal
290wire [1:0] csrbus_src_bus; // Source bus
291wire csrbus_acc_vio; // Violation signal
292wire instance_id; // Instance ID
293wire ilu_log_en_spare3_hw_read; // This signal provides the current value of
294 // ilu_log_en_spare3.
295wire ilu_log_en_spare2_hw_read; // This signal provides the current value of
296 // ilu_log_en_spare2.
297wire ilu_log_en_spare1_hw_read; // This signal provides the current value of
298 // ilu_log_en_spare1.
299wire ilu_log_en_ihb_pe_hw_read; // This signal provides the current value of
300 // ilu_log_en_ihb_pe.
301wire ilu_int_en_spare3_s_hw_read; // This signal provides the current value of
302 // ilu_int_en_spare3_s.
303wire ilu_int_en_spare2_s_hw_read; // This signal provides the current value of
304 // ilu_int_en_spare2_s.
305wire ilu_int_en_spare1_s_hw_read; // This signal provides the current value of
306 // ilu_int_en_spare1_s.
307wire ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value of
308 // ilu_int_en_ihb_pe_s.
309wire ilu_int_en_spare3_p_hw_read; // This signal provides the current value of
310 // ilu_int_en_spare3_p.
311wire ilu_int_en_spare2_p_hw_read; // This signal provides the current value of
312 // ilu_int_en_spare2_p.
313wire ilu_int_en_spare1_p_hw_read; // This signal provides the current value of
314 // ilu_int_en_spare1_p.
315wire ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value of
316 // ilu_int_en_ihb_pe_p.
317wire [0:0] ilu_en_err_spare3_s_ext_read_data; // Ext read data (decode)
318wire [0:0] ilu_en_err_spare2_s_ext_read_data; // Ext read data (decode)
319wire [0:0] ilu_en_err_spare1_s_ext_read_data; // Ext read data (decode)
320wire [0:0] ilu_en_err_ihb_pe_s_ext_read_data; // Ext read data (decode)
321wire [0:0] ilu_en_err_spare3_p_ext_read_data; // Ext read data (decode)
322wire [0:0] ilu_en_err_spare2_p_ext_read_data; // Ext read data (decode)
323wire [0:0] ilu_en_err_spare1_p_ext_read_data; // Ext read data (decode)
324wire [0:0] ilu_en_err_ihb_pe_p_ext_read_data; // Ext read data (decode)
325wire ilu_log_err_spare3_s_hw_set; // Hardware set signal for
326 // ilu_log_err_spare3_s. When set ilu_log_err
327 // will be set to one.
328wire ilu_log_err_spare3_s_hw_read; // This signal provides the current value of
329 // ilu_log_err_spare3_s.
330wire ilu_log_err_spare2_s_hw_set; // Hardware set signal for
331 // ilu_log_err_spare2_s. When set ilu_log_err
332 // will be set to one.
333wire ilu_log_err_spare2_s_hw_read; // This signal provides the current value of
334 // ilu_log_err_spare2_s.
335wire ilu_log_err_spare1_s_hw_set; // Hardware set signal for
336 // ilu_log_err_spare1_s. When set ilu_log_err
337 // will be set to one.
338wire ilu_log_err_spare1_s_hw_read; // This signal provides the current value of
339 // ilu_log_err_spare1_s.
340wire ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for
341 // ilu_log_err_ihb_pe_s. When set ilu_log_err
342 // will be set to one.
343wire ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value of
344 // ilu_log_err_ihb_pe_s.
345wire ilu_log_err_spare3_p_hw_set; // Hardware set signal for
346 // ilu_log_err_spare3_p. When set ilu_log_err
347 // will be set to one.
348wire ilu_log_err_spare3_p_hw_read; // This signal provides the current value of
349 // ilu_log_err_spare3_p.
350wire ilu_log_err_spare2_p_hw_set; // Hardware set signal for
351 // ilu_log_err_spare2_p. When set ilu_log_err
352 // will be set to one.
353wire ilu_log_err_spare2_p_hw_read; // This signal provides the current value of
354 // ilu_log_err_spare2_p.
355wire ilu_log_err_spare1_p_hw_set; // Hardware set signal for
356 // ilu_log_err_spare1_p. When set ilu_log_err
357 // will be set to one.
358wire ilu_log_err_spare1_p_hw_read; // This signal provides the current value of
359 // ilu_log_err_spare1_p.
360wire ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for
361 // ilu_log_err_ihb_pe_p. When set ilu_log_err
362 // will be set to one.
363wire ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value of
364 // ilu_log_err_ihb_pe_p.
365wire pec_int_en_pec_hw_read; // This signal provides the current value of
366 // pec_int_en_pec.
367wire pec_int_en_pec_ilu_hw_read; // This signal provides the current value of
368 // pec_int_en_pec_ilu.
369wire pec_int_en_pec_ue_hw_read; // This signal provides the current value of
370 // pec_int_en_pec_ue.
371wire pec_int_en_pec_ce_hw_read; // This signal provides the current value of
372 // pec_int_en_pec_ce.
373wire pec_int_en_pec_oe_hw_read; // This signal provides the current value of
374 // pec_int_en_pec_oe.
375wire [0:0] pec_en_err_ilu_ext_read_data; // Ext read data (decode)
376wire [0:0] pec_en_err_ue_ext_read_data; // Ext read data (decode)
377wire [0:0] pec_en_err_ce_ext_read_data; // Ext read data (decode)
378wire [0:0] pec_en_err_oe_ext_read_data; // Ext read data (decode)
379wire ilu_diagnos_enpll1_hw_read; // This signal provides the current value of
380 // ilu_diagnos_enpll1.
381wire ilu_diagnos_enpll0_hw_read; // This signal provides the current value of
382 // ilu_diagnos_enpll0.
383wire ilu_diagnos_entx7_hw_read; // This signal provides the current value of
384 // ilu_diagnos_entx7.
385wire ilu_diagnos_entx6_hw_read; // This signal provides the current value of
386 // ilu_diagnos_entx6.
387wire ilu_diagnos_entx5_hw_read; // This signal provides the current value of
388 // ilu_diagnos_entx5.
389wire ilu_diagnos_entx4_hw_read; // This signal provides the current value of
390 // ilu_diagnos_entx4.
391wire ilu_diagnos_entx3_hw_read; // This signal provides the current value of
392 // ilu_diagnos_entx3.
393wire ilu_diagnos_entx2_hw_read; // This signal provides the current value of
394 // ilu_diagnos_entx2.
395wire ilu_diagnos_entx1_hw_read; // This signal provides the current value of
396 // ilu_diagnos_entx1.
397wire ilu_diagnos_entx0_hw_read; // This signal provides the current value of
398 // ilu_diagnos_entx0.
399wire ilu_diagnos_enrx7_hw_read; // This signal provides the current value of
400 // ilu_diagnos_enrx7.
401wire ilu_diagnos_enrx6_hw_read; // This signal provides the current value of
402 // ilu_diagnos_enrx6.
403wire ilu_diagnos_enrx5_hw_read; // This signal provides the current value of
404 // ilu_diagnos_enrx5.
405wire ilu_diagnos_enrx4_hw_read; // This signal provides the current value of
406 // ilu_diagnos_enrx4.
407wire ilu_diagnos_enrx3_hw_read; // This signal provides the current value of
408 // ilu_diagnos_enrx3.
409wire ilu_diagnos_enrx2_hw_read; // This signal provides the current value of
410 // ilu_diagnos_enrx2.
411wire ilu_diagnos_enrx1_hw_read; // This signal provides the current value of
412 // ilu_diagnos_enrx1.
413wire ilu_diagnos_enrx0_hw_read; // This signal provides the current value of
414 // ilu_diagnos_enrx0.
415wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read;
416 // This signal provides the current value of ilu_diagnos_edi_par.
417wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read;
418 // This signal provides the current value of ilu_diagnos_ehi_par.
419wire ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for
420 // ilu_diagnos_edi_trig. When set ilu_diagnos
421 // will be set to zero.
422wire ilu_diagnos_edi_trig_hw_read; // This signal provides the current value of
423 // ilu_diagnos_edi_trig.
424wire ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for
425 // ilu_diagnos_ehi_trig. When set ilu_diagnos
426 // will be set to zero.
427wire ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value of
428 // ilu_diagnos_ehi_trig.
429wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC] ilu_diagnos_rate_scale_hw_read;
430 // This signal provides the current value of ilu_diagnos_rate_scale.
431
432//====================================================
433// Logic
434//====================================================
435wire daemon_transaction_in_progress;
436wire daemon_csrbus_mapped;
437wire daemon_csrbus_valid;
438// vlint flag_dangling_net_within_module off
439// vlint flag_net_has_no_load off
440wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp;
441wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data;
442// vlint flag_dangling_net_within_module on
443// vlint flag_net_has_no_load on
444wire daemon_csrbus_done;
445wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr;
446wire daemon_csrbus_wr_tmp;
447wire daemon_csrbus_wr;
448
449//summit modcovoff -bepgnv
450pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon (
451 .daemon_csrbus_valid (daemon_csrbus_valid),
452 .daemon_csrbus_mapped (daemon_csrbus_mapped),
453 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
454 .daemon_csrbus_done (daemon_csrbus_done),
455 .daemon_csrbus_addr (daemon_csrbus_addr),
456 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
457 .daemon_transaction_in_progress (daemon_transaction_in_progress),
458// synopsys translate_off
459 .clk(clk),
460 .csrbus_read_data (csrbus_read_data),
461 .rst_l (rst_l),
462// synopsys translate_on
463 .csrbus_valid (csrbus_valid),
464 .csrbus_mapped (csrbus_mapped),
465 .csrbus_wr_data (csrbus_wr_data),
466 .csrbus_done (csrbus_done),
467 .csrbus_addr (csrbus_addr),
468 .csrbus_wr (csrbus_wr)
469 );
470//summit modcovon -bepgnv
471
472//====================================================================
473// Address decode
474//====================================================================
475wire ilu_log_en_select_pulse;
476wire ilu_int_en_select_pulse;
477wire ilu_en_err_select;
478wire ilu_log_err_select_pulse;
479wire pec_int_en_select_pulse;
480wire pec_en_err_select;
481wire ilu_diagnos_select_pulse;
482wire ilu_log_err_rw1c_alias;
483wire ilu_log_err_rw1s_alias;
484
485dmu_ilu_cib_addr_decode dmu_ilu_cib_addr_decode
486 (
487 .clk (clk),
488 .rst_l (rst_l),
489 .daemon_csrbus_valid (daemon_csrbus_valid),
490 .daemon_csrbus_addr (daemon_csrbus_addr),
491 .csrbus_src_bus (csrbus_src_bus),
492 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
493 .daemon_csrbus_wr_out (daemon_csrbus_wr),
494 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
495 .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data),
496 .daemon_csrbus_mapped (daemon_csrbus_mapped),
497 .csrbus_acc_vio (csrbus_acc_vio),
498 .daemon_transaction_in_progress (daemon_transaction_in_progress),
499 .instance_id (instance_id),
500 .daemon_csrbus_done (daemon_csrbus_done),
501 .ilu_log_en_select_pulse (ilu_log_en_select_pulse),
502 .ilu_int_en_select_pulse (ilu_int_en_select_pulse),
503 .ilu_en_err_select (ilu_en_err_select),
504 .ilu_log_err_select_pulse (ilu_log_err_select_pulse),
505 .ilu_log_err_rw1c_alias (ilu_log_err_rw1c_alias),
506 .ilu_log_err_rw1s_alias (ilu_log_err_rw1s_alias),
507 .pec_int_en_select_pulse (pec_int_en_select_pulse),
508 .pec_en_err_select (pec_en_err_select),
509 .ilu_diagnos_select_pulse (ilu_diagnos_select_pulse)
510 );
511
512//====================================================================
513// OUTPUT: csrbus_read_data (pipelining)
514//====================================================================
515//----- connecting wires
516wire stage_mux_only_rst_l;
517wire stage_mux_only_por_l;
518wire stage_mux_only_ilu_log_err_rw1c_alias;
519wire stage_mux_only_ilu_log_err_rw1s_alias;
520wire stage_mux_only_daemon_csrbus_wr;
521wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data;
522
523//----- Stage: 1 / Grp: default_grp (7 inputs / 2 outputs)
524wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out;
525wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_1_out;
526wire default_grp_ilu_log_en_select_pulse;
527wire default_grp_ilu_int_en_select_pulse;
528wire default_grp_ilu_en_err_select;
529wire default_grp_ilu_log_err_select_pulse;
530wire default_grp_pec_int_en_select_pulse;
531wire default_grp_pec_en_err_select;
532wire default_grp_ilu_diagnos_select_pulse;
533
534dmu_ilu_cib_default_grp dmu_ilu_cib_default_grp
535 (
536 .clk (clk),
537 .ilu_log_en_spare3_hw_read (ilu_log_en_spare3_hw_read),
538 .ilu_log_en_spare2_hw_read (ilu_log_en_spare2_hw_read),
539 .ilu_log_en_spare1_hw_read (ilu_log_en_spare1_hw_read),
540 .ilu_log_en_ihb_pe_hw_read (ilu_log_en_ihb_pe_hw_read),
541 .ilu_log_en_select_pulse (default_grp_ilu_log_en_select_pulse),
542 .ilu_int_en_spare3_s_hw_read (ilu_int_en_spare3_s_hw_read),
543 .ilu_int_en_spare2_s_hw_read (ilu_int_en_spare2_s_hw_read),
544 .ilu_int_en_spare1_s_hw_read (ilu_int_en_spare1_s_hw_read),
545 .ilu_int_en_ihb_pe_s_hw_read (ilu_int_en_ihb_pe_s_hw_read),
546 .ilu_int_en_spare3_p_hw_read (ilu_int_en_spare3_p_hw_read),
547 .ilu_int_en_spare2_p_hw_read (ilu_int_en_spare2_p_hw_read),
548 .ilu_int_en_spare1_p_hw_read (ilu_int_en_spare1_p_hw_read),
549 .ilu_int_en_ihb_pe_p_hw_read (ilu_int_en_ihb_pe_p_hw_read),
550 .ilu_int_en_select_pulse (default_grp_ilu_int_en_select_pulse),
551 .ilu_en_err_select (default_grp_ilu_en_err_select),
552 .ilu_en_err_ext_read_data
553 (
554 {
555 24'b0,
556 ilu_en_err_spare3_s_ext_read_data,
557 ilu_en_err_spare2_s_ext_read_data,
558 ilu_en_err_spare1_s_ext_read_data,
559 ilu_en_err_ihb_pe_s_ext_read_data,
560 28'b0,
561 ilu_en_err_spare3_p_ext_read_data,
562 ilu_en_err_spare2_p_ext_read_data,
563 ilu_en_err_spare1_p_ext_read_data,
564 ilu_en_err_ihb_pe_p_ext_read_data,
565 4'b0
566 }),
567 .ilu_log_err_spare3_s_hw_set (ilu_log_err_spare3_s_hw_set),
568 .ilu_log_err_spare3_s_hw_read (ilu_log_err_spare3_s_hw_read),
569 .ilu_log_err_spare2_s_hw_set (ilu_log_err_spare2_s_hw_set),
570 .ilu_log_err_spare2_s_hw_read (ilu_log_err_spare2_s_hw_read),
571 .ilu_log_err_spare1_s_hw_set (ilu_log_err_spare1_s_hw_set),
572 .ilu_log_err_spare1_s_hw_read (ilu_log_err_spare1_s_hw_read),
573 .ilu_log_err_ihb_pe_s_hw_set (ilu_log_err_ihb_pe_s_hw_set),
574 .ilu_log_err_ihb_pe_s_hw_read (ilu_log_err_ihb_pe_s_hw_read),
575 .ilu_log_err_spare3_p_hw_set (ilu_log_err_spare3_p_hw_set),
576 .ilu_log_err_spare3_p_hw_read (ilu_log_err_spare3_p_hw_read),
577 .ilu_log_err_spare2_p_hw_set (ilu_log_err_spare2_p_hw_set),
578 .ilu_log_err_spare2_p_hw_read (ilu_log_err_spare2_p_hw_read),
579 .ilu_log_err_spare1_p_hw_set (ilu_log_err_spare1_p_hw_set),
580 .ilu_log_err_spare1_p_hw_read (ilu_log_err_spare1_p_hw_read),
581 .ilu_log_err_ihb_pe_p_hw_set (ilu_log_err_ihb_pe_p_hw_set),
582 .ilu_log_err_ihb_pe_p_hw_read (ilu_log_err_ihb_pe_p_hw_read),
583 .ilu_log_err_select_pulse (default_grp_ilu_log_err_select_pulse),
584 .pec_int_en_pec_hw_read (pec_int_en_pec_hw_read),
585 .pec_int_en_pec_ilu_hw_read (pec_int_en_pec_ilu_hw_read),
586 .pec_int_en_pec_ue_hw_read (pec_int_en_pec_ue_hw_read),
587 .pec_int_en_pec_ce_hw_read (pec_int_en_pec_ce_hw_read),
588 .pec_int_en_pec_oe_hw_read (pec_int_en_pec_oe_hw_read),
589 .pec_int_en_select_pulse (default_grp_pec_int_en_select_pulse),
590 .pec_en_err_select (default_grp_pec_en_err_select),
591 .pec_en_err_ext_read_data
592 (
593 {
594 60'b0,
595 pec_en_err_ilu_ext_read_data,
596 pec_en_err_ue_ext_read_data,
597 pec_en_err_ce_ext_read_data,
598 pec_en_err_oe_ext_read_data
599 }),
600 .ilu_diagnos_enpll1_hw_read (ilu_diagnos_enpll1_hw_read),
601 .ilu_diagnos_enpll0_hw_read (ilu_diagnos_enpll0_hw_read),
602 .ilu_diagnos_entx7_hw_read (ilu_diagnos_entx7_hw_read),
603 .ilu_diagnos_entx6_hw_read (ilu_diagnos_entx6_hw_read),
604 .ilu_diagnos_entx5_hw_read (ilu_diagnos_entx5_hw_read),
605 .ilu_diagnos_entx4_hw_read (ilu_diagnos_entx4_hw_read),
606 .ilu_diagnos_entx3_hw_read (ilu_diagnos_entx3_hw_read),
607 .ilu_diagnos_entx2_hw_read (ilu_diagnos_entx2_hw_read),
608 .ilu_diagnos_entx1_hw_read (ilu_diagnos_entx1_hw_read),
609 .ilu_diagnos_entx0_hw_read (ilu_diagnos_entx0_hw_read),
610 .ilu_diagnos_enrx7_hw_read (ilu_diagnos_enrx7_hw_read),
611 .ilu_diagnos_enrx6_hw_read (ilu_diagnos_enrx6_hw_read),
612 .ilu_diagnos_enrx5_hw_read (ilu_diagnos_enrx5_hw_read),
613 .ilu_diagnos_enrx4_hw_read (ilu_diagnos_enrx4_hw_read),
614 .ilu_diagnos_enrx3_hw_read (ilu_diagnos_enrx3_hw_read),
615 .ilu_diagnos_enrx2_hw_read (ilu_diagnos_enrx2_hw_read),
616 .ilu_diagnos_enrx1_hw_read (ilu_diagnos_enrx1_hw_read),
617 .ilu_diagnos_enrx0_hw_read (ilu_diagnos_enrx0_hw_read),
618 .ilu_diagnos_edi_par_hw_read (ilu_diagnos_edi_par_hw_read),
619 .ilu_diagnos_ehi_par_hw_read (ilu_diagnos_ehi_par_hw_read),
620 .ilu_diagnos_edi_trig_hw_clr (ilu_diagnos_edi_trig_hw_clr),
621 .ilu_diagnos_edi_trig_hw_read (ilu_diagnos_edi_trig_hw_read),
622 .ilu_diagnos_ehi_trig_hw_clr (ilu_diagnos_ehi_trig_hw_clr),
623 .ilu_diagnos_ehi_trig_hw_read (ilu_diagnos_ehi_trig_hw_read),
624 .ilu_diagnos_rate_scale_hw_read (ilu_diagnos_rate_scale_hw_read),
625 .ilu_diagnos_select_pulse (default_grp_ilu_diagnos_select_pulse),
626 .ilu_log_err_rw1c_alias (stage_mux_only_ilu_log_err_rw1c_alias),
627 .ilu_log_err_rw1s_alias (stage_mux_only_ilu_log_err_rw1s_alias),
628 .rst_l (stage_mux_only_rst_l),
629 .por_l (stage_mux_only_por_l),
630 .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr),
631 .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data),
632 .read_data_0_out (default_grp_read_data_0_out),
633 .read_data_1_out (default_grp_read_data_1_out)
634 );
635
636//----- Stage: 2 / Grp: stage_mux_only (2 inputs / 1 outputs) (Mux only)
637wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out;
638
639dmu_ilu_cib_stage_mux_only dmu_ilu_cib_stage_mux_only
640 (
641 .clk (clk),
642 .read_data_0 (default_grp_read_data_0_out),
643 .read_data_1 (default_grp_read_data_1_out),
644 .ilu_log_en_select_pulse (ilu_log_en_select_pulse),
645 .ilu_log_en_select_pulse_out (default_grp_ilu_log_en_select_pulse),
646 .ilu_int_en_select_pulse (ilu_int_en_select_pulse),
647 .ilu_int_en_select_pulse_out (default_grp_ilu_int_en_select_pulse),
648 .ilu_en_err_select (ilu_en_err_select),
649 .ilu_en_err_select_out (default_grp_ilu_en_err_select),
650 .ilu_log_err_select_pulse (ilu_log_err_select_pulse),
651 .ilu_log_err_select_pulse_out (default_grp_ilu_log_err_select_pulse),
652 .pec_int_en_select_pulse (pec_int_en_select_pulse),
653 .pec_int_en_select_pulse_out (default_grp_pec_int_en_select_pulse),
654 .pec_en_err_select (pec_en_err_select),
655 .pec_en_err_select_out (default_grp_pec_en_err_select),
656 .ilu_diagnos_select_pulse (ilu_diagnos_select_pulse),
657 .ilu_diagnos_select_pulse_out (default_grp_ilu_diagnos_select_pulse),
658 .ilu_log_err_rw1c_alias (ilu_log_err_rw1c_alias),
659 .ilu_log_err_rw1c_alias_out (stage_mux_only_ilu_log_err_rw1c_alias),
660 .ilu_log_err_rw1s_alias (ilu_log_err_rw1s_alias),
661 .ilu_log_err_rw1s_alias_out (stage_mux_only_ilu_log_err_rw1s_alias),
662 .daemon_csrbus_wr_in (daemon_csrbus_wr),
663 .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr),
664 .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data),
665 .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data),
666 .read_data_0_out (stage_mux_only_read_data_0_out),
667 .rst_l (rst_l),
668 .rst_l_out (stage_mux_only_rst_l),
669 .por_l (por_l),
670 .por_l_out (stage_mux_only_por_l)
671 );
672
673//----- OUTPUT: csrbus_read_data
674assign csrbus_read_data = stage_mux_only_read_data_0_out;
675
676endmodule // dmu_ilu_cib_csr
Full OpenSPARC design & verification tarball including full HDL.