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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_ilu_cib_csr_ilu_int_en_entry.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_ilu_cib_csr_ilu_int_en_entry.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
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13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
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23// choice is available it will apply instead, Sun elects to use only
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31// CA 95054 USA or visit www.sun.com if you need additional information or
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33//
34// ========== Copyright Header End ============================================
35module dmu_ilu_cib_csr_ilu_int_en_entry
36 (
37 // synopsys translate_off
38 omni_ld,
39 omni_data,
40 // synopsys translate_on
41 clk,
42 rst_l,
43 w_ld,
44 csrbus_wr_data,
45 ilu_int_en_csrbus_read_data
46 );
47
48//====================================================================
49// Polarity declarations
50//====================================================================
51// synopsys translate_off
52 input omni_ld; // Omni load
53// vlint flag_input_port_not_connected off
54 input [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH - 1:0] omni_data;
55 // Omni write data
56// synopsys translate_on
57// vlint flag_input_port_not_connected on
58input clk; // Clock signal
59input rst_l; // Reset signal
60input w_ld; // SW load
61// vlint flag_input_port_not_connected off
62input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
63// vlint flag_input_port_not_connected on
64output [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH-1:0] ilu_int_en_csrbus_read_data;
65 // SW read data
66
67//====================================================================
68// Type declarations
69//====================================================================
70// synopsys translate_off
71 wire omni_ld; // Omni load
72// vlint flag_dangling_net_within_module off
73// vlint flag_net_has_no_load off
74 wire [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH - 1:0] omni_data; // Omni write
75 // data
76// synopsys translate_on
77// vlint flag_dangling_net_within_module on
78// vlint flag_net_has_no_load on
79wire clk; // Clock signal
80wire rst_l; // Reset signal
81wire w_ld; // SW load
82// vlint flag_dangling_net_within_module off
83// vlint flag_net_has_no_load off
84wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
85// vlint flag_dangling_net_within_module on
86// vlint flag_net_has_no_load on
87wire [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH-1:0] ilu_int_en_csrbus_read_data;
88 // SW read data
89
90//====================================================================
91// Logic
92//====================================================================
93
94//----- Reset values
95// verilint 531 off
96wire [0:0] reset_spare3_s = 1'h0;
97wire [0:0] reset_spare2_s = 1'h0;
98wire [0:0] reset_spare1_s = 1'h0;
99wire [0:0] reset_ihb_pe_s = 1'h0;
100wire [0:0] reset_spare3_p = 1'h0;
101wire [0:0] reset_spare2_p = 1'h0;
102wire [0:0] reset_spare1_p = 1'h0;
103wire [0:0] reset_ihb_pe_p = 1'h0;
104// verilint 531 on
105
106//----- Active high reset wires
107wire rst_l_active_high = ~rst_l;
108
109//====================================================
110// Instantiation of flops
111//====================================================
112
113assign ilu_int_en_csrbus_read_data[0] = 1'b0; // bit 0
114assign ilu_int_en_csrbus_read_data[1] = 1'b0; // bit 1
115assign ilu_int_en_csrbus_read_data[2] = 1'b0; // bit 2
116assign ilu_int_en_csrbus_read_data[3] = 1'b0; // bit 3
117// bit 4
118csr_sw csr_sw_4
119 (
120 // synopsys translate_off
121 .omni_ld (omni_ld),
122 .omni_data (omni_data[4]),
123 .omni_rw_alias (1'b1),
124 .omni_rw1c_alias (1'b0),
125 .omni_rw1s_alias (1'b0),
126 // synopsys translate_on
127 .rst (rst_l_active_high),
128 .rst_val (reset_ihb_pe_p[0]),
129 .csr_ld (w_ld),
130 .csr_data (csrbus_wr_data[4]),
131 .rw_alias (1'b1),
132 .rw1c_alias (1'b0),
133 .rw1s_alias (1'b0),
134 .hw_ld (1'b0),
135 .hw_data (1'b0),
136 .cp (clk),
137 .q (ilu_int_en_csrbus_read_data[4])
138 );
139
140// bit 5
141csr_sw csr_sw_5
142 (
143 // synopsys translate_off
144 .omni_ld (omni_ld),
145 .omni_data (omni_data[5]),
146 .omni_rw_alias (1'b1),
147 .omni_rw1c_alias (1'b0),
148 .omni_rw1s_alias (1'b0),
149 // synopsys translate_on
150 .rst (rst_l_active_high),
151 .rst_val (reset_spare1_p[0]),
152 .csr_ld (w_ld),
153 .csr_data (csrbus_wr_data[5]),
154 .rw_alias (1'b1),
155 .rw1c_alias (1'b0),
156 .rw1s_alias (1'b0),
157 .hw_ld (1'b0),
158 .hw_data (1'b0),
159 .cp (clk),
160 .q (ilu_int_en_csrbus_read_data[5])
161 );
162
163// bit 6
164csr_sw csr_sw_6
165 (
166 // synopsys translate_off
167 .omni_ld (omni_ld),
168 .omni_data (omni_data[6]),
169 .omni_rw_alias (1'b1),
170 .omni_rw1c_alias (1'b0),
171 .omni_rw1s_alias (1'b0),
172 // synopsys translate_on
173 .rst (rst_l_active_high),
174 .rst_val (reset_spare2_p[0]),
175 .csr_ld (w_ld),
176 .csr_data (csrbus_wr_data[6]),
177 .rw_alias (1'b1),
178 .rw1c_alias (1'b0),
179 .rw1s_alias (1'b0),
180 .hw_ld (1'b0),
181 .hw_data (1'b0),
182 .cp (clk),
183 .q (ilu_int_en_csrbus_read_data[6])
184 );
185
186// bit 7
187csr_sw csr_sw_7
188 (
189 // synopsys translate_off
190 .omni_ld (omni_ld),
191 .omni_data (omni_data[7]),
192 .omni_rw_alias (1'b1),
193 .omni_rw1c_alias (1'b0),
194 .omni_rw1s_alias (1'b0),
195 // synopsys translate_on
196 .rst (rst_l_active_high),
197 .rst_val (reset_spare3_p[0]),
198 .csr_ld (w_ld),
199 .csr_data (csrbus_wr_data[7]),
200 .rw_alias (1'b1),
201 .rw1c_alias (1'b0),
202 .rw1s_alias (1'b0),
203 .hw_ld (1'b0),
204 .hw_data (1'b0),
205 .cp (clk),
206 .q (ilu_int_en_csrbus_read_data[7])
207 );
208
209assign ilu_int_en_csrbus_read_data[8] = 1'b0; // bit 8
210assign ilu_int_en_csrbus_read_data[9] = 1'b0; // bit 9
211assign ilu_int_en_csrbus_read_data[10] = 1'b0; // bit 10
212assign ilu_int_en_csrbus_read_data[11] = 1'b0; // bit 11
213assign ilu_int_en_csrbus_read_data[12] = 1'b0; // bit 12
214assign ilu_int_en_csrbus_read_data[13] = 1'b0; // bit 13
215assign ilu_int_en_csrbus_read_data[14] = 1'b0; // bit 14
216assign ilu_int_en_csrbus_read_data[15] = 1'b0; // bit 15
217assign ilu_int_en_csrbus_read_data[16] = 1'b0; // bit 16
218assign ilu_int_en_csrbus_read_data[17] = 1'b0; // bit 17
219assign ilu_int_en_csrbus_read_data[18] = 1'b0; // bit 18
220assign ilu_int_en_csrbus_read_data[19] = 1'b0; // bit 19
221assign ilu_int_en_csrbus_read_data[20] = 1'b0; // bit 20
222assign ilu_int_en_csrbus_read_data[21] = 1'b0; // bit 21
223assign ilu_int_en_csrbus_read_data[22] = 1'b0; // bit 22
224assign ilu_int_en_csrbus_read_data[23] = 1'b0; // bit 23
225assign ilu_int_en_csrbus_read_data[24] = 1'b0; // bit 24
226assign ilu_int_en_csrbus_read_data[25] = 1'b0; // bit 25
227assign ilu_int_en_csrbus_read_data[26] = 1'b0; // bit 26
228assign ilu_int_en_csrbus_read_data[27] = 1'b0; // bit 27
229assign ilu_int_en_csrbus_read_data[28] = 1'b0; // bit 28
230assign ilu_int_en_csrbus_read_data[29] = 1'b0; // bit 29
231assign ilu_int_en_csrbus_read_data[30] = 1'b0; // bit 30
232assign ilu_int_en_csrbus_read_data[31] = 1'b0; // bit 31
233assign ilu_int_en_csrbus_read_data[32] = 1'b0; // bit 32
234assign ilu_int_en_csrbus_read_data[33] = 1'b0; // bit 33
235assign ilu_int_en_csrbus_read_data[34] = 1'b0; // bit 34
236assign ilu_int_en_csrbus_read_data[35] = 1'b0; // bit 35
237// bit 36
238csr_sw csr_sw_36
239 (
240 // synopsys translate_off
241 .omni_ld (omni_ld),
242 .omni_data (omni_data[36]),
243 .omni_rw_alias (1'b1),
244 .omni_rw1c_alias (1'b0),
245 .omni_rw1s_alias (1'b0),
246 // synopsys translate_on
247 .rst (rst_l_active_high),
248 .rst_val (reset_ihb_pe_s[0]),
249 .csr_ld (w_ld),
250 .csr_data (csrbus_wr_data[36]),
251 .rw_alias (1'b1),
252 .rw1c_alias (1'b0),
253 .rw1s_alias (1'b0),
254 .hw_ld (1'b0),
255 .hw_data (1'b0),
256 .cp (clk),
257 .q (ilu_int_en_csrbus_read_data[36])
258 );
259
260// bit 37
261csr_sw csr_sw_37
262 (
263 // synopsys translate_off
264 .omni_ld (omni_ld),
265 .omni_data (omni_data[37]),
266 .omni_rw_alias (1'b1),
267 .omni_rw1c_alias (1'b0),
268 .omni_rw1s_alias (1'b0),
269 // synopsys translate_on
270 .rst (rst_l_active_high),
271 .rst_val (reset_spare1_s[0]),
272 .csr_ld (w_ld),
273 .csr_data (csrbus_wr_data[37]),
274 .rw_alias (1'b1),
275 .rw1c_alias (1'b0),
276 .rw1s_alias (1'b0),
277 .hw_ld (1'b0),
278 .hw_data (1'b0),
279 .cp (clk),
280 .q (ilu_int_en_csrbus_read_data[37])
281 );
282
283// bit 38
284csr_sw csr_sw_38
285 (
286 // synopsys translate_off
287 .omni_ld (omni_ld),
288 .omni_data (omni_data[38]),
289 .omni_rw_alias (1'b1),
290 .omni_rw1c_alias (1'b0),
291 .omni_rw1s_alias (1'b0),
292 // synopsys translate_on
293 .rst (rst_l_active_high),
294 .rst_val (reset_spare2_s[0]),
295 .csr_ld (w_ld),
296 .csr_data (csrbus_wr_data[38]),
297 .rw_alias (1'b1),
298 .rw1c_alias (1'b0),
299 .rw1s_alias (1'b0),
300 .hw_ld (1'b0),
301 .hw_data (1'b0),
302 .cp (clk),
303 .q (ilu_int_en_csrbus_read_data[38])
304 );
305
306// bit 39
307csr_sw csr_sw_39
308 (
309 // synopsys translate_off
310 .omni_ld (omni_ld),
311 .omni_data (omni_data[39]),
312 .omni_rw_alias (1'b1),
313 .omni_rw1c_alias (1'b0),
314 .omni_rw1s_alias (1'b0),
315 // synopsys translate_on
316 .rst (rst_l_active_high),
317 .rst_val (reset_spare3_s[0]),
318 .csr_ld (w_ld),
319 .csr_data (csrbus_wr_data[39]),
320 .rw_alias (1'b1),
321 .rw1c_alias (1'b0),
322 .rw1s_alias (1'b0),
323 .hw_ld (1'b0),
324 .hw_data (1'b0),
325 .cp (clk),
326 .q (ilu_int_en_csrbus_read_data[39])
327 );
328
329assign ilu_int_en_csrbus_read_data[40] = 1'b0; // bit 40
330assign ilu_int_en_csrbus_read_data[41] = 1'b0; // bit 41
331assign ilu_int_en_csrbus_read_data[42] = 1'b0; // bit 42
332assign ilu_int_en_csrbus_read_data[43] = 1'b0; // bit 43
333assign ilu_int_en_csrbus_read_data[44] = 1'b0; // bit 44
334assign ilu_int_en_csrbus_read_data[45] = 1'b0; // bit 45
335assign ilu_int_en_csrbus_read_data[46] = 1'b0; // bit 46
336assign ilu_int_en_csrbus_read_data[47] = 1'b0; // bit 47
337assign ilu_int_en_csrbus_read_data[48] = 1'b0; // bit 48
338assign ilu_int_en_csrbus_read_data[49] = 1'b0; // bit 49
339assign ilu_int_en_csrbus_read_data[50] = 1'b0; // bit 50
340assign ilu_int_en_csrbus_read_data[51] = 1'b0; // bit 51
341assign ilu_int_en_csrbus_read_data[52] = 1'b0; // bit 52
342assign ilu_int_en_csrbus_read_data[53] = 1'b0; // bit 53
343assign ilu_int_en_csrbus_read_data[54] = 1'b0; // bit 54
344assign ilu_int_en_csrbus_read_data[55] = 1'b0; // bit 55
345assign ilu_int_en_csrbus_read_data[56] = 1'b0; // bit 56
346assign ilu_int_en_csrbus_read_data[57] = 1'b0; // bit 57
347assign ilu_int_en_csrbus_read_data[58] = 1'b0; // bit 58
348assign ilu_int_en_csrbus_read_data[59] = 1'b0; // bit 59
349assign ilu_int_en_csrbus_read_data[60] = 1'b0; // bit 60
350assign ilu_int_en_csrbus_read_data[61] = 1'b0; // bit 61
351assign ilu_int_en_csrbus_read_data[62] = 1'b0; // bit 62
352assign ilu_int_en_csrbus_read_data[63] = 1'b0; // bit 63
353
354endmodule // dmu_ilu_cib_csr_ilu_int_en_entry
Full OpenSPARC design & verification tarball including full HDL.