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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_stage_mux_only.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_cib_stage_mux_only | |
36 | ( | |
37 | clk, | |
38 | read_data_0, | |
39 | read_data_1, | |
40 | ilu_log_en_select_pulse, | |
41 | ilu_log_en_select_pulse_out, | |
42 | ilu_int_en_select_pulse, | |
43 | ilu_int_en_select_pulse_out, | |
44 | ilu_en_err_select, | |
45 | ilu_en_err_select_out, | |
46 | ilu_log_err_select_pulse, | |
47 | ilu_log_err_select_pulse_out, | |
48 | pec_int_en_select_pulse, | |
49 | pec_int_en_select_pulse_out, | |
50 | pec_en_err_select, | |
51 | pec_en_err_select_out, | |
52 | ilu_diagnos_select_pulse, | |
53 | ilu_diagnos_select_pulse_out, | |
54 | ilu_log_err_rw1c_alias, | |
55 | ilu_log_err_rw1c_alias_out, | |
56 | ilu_log_err_rw1s_alias, | |
57 | ilu_log_err_rw1s_alias_out, | |
58 | daemon_csrbus_wr_in, | |
59 | daemon_csrbus_wr_out, | |
60 | daemon_csrbus_wr_data_in, | |
61 | daemon_csrbus_wr_data_out, | |
62 | read_data_0_out, | |
63 | rst_l, | |
64 | rst_l_out, | |
65 | por_l, | |
66 | por_l_out | |
67 | ); | |
68 | ||
69 | //==================================================== | |
70 | // Polarity declarations | |
71 | //==================================================== | |
72 | input clk; // Clock signal | |
73 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
74 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data | |
75 | input ilu_log_en_select_pulse; // select | |
76 | output ilu_log_en_select_pulse_out; // select | |
77 | input ilu_int_en_select_pulse; // select | |
78 | output ilu_int_en_select_pulse_out; // select | |
79 | input ilu_en_err_select; // select | |
80 | output ilu_en_err_select_out; // select | |
81 | input ilu_log_err_select_pulse; // select | |
82 | output ilu_log_err_select_pulse_out; // select | |
83 | input pec_int_en_select_pulse; // select | |
84 | output pec_int_en_select_pulse_out; // select | |
85 | input pec_en_err_select; // select | |
86 | output pec_en_err_select_out; // select | |
87 | input ilu_diagnos_select_pulse; // select | |
88 | output ilu_diagnos_select_pulse_out; // select | |
89 | input ilu_log_err_rw1c_alias; // SW load | |
90 | output ilu_log_err_rw1c_alias_out; // alias | |
91 | input ilu_log_err_rw1s_alias; // SW load | |
92 | output ilu_log_err_rw1s_alias_out; // alias | |
93 | input daemon_csrbus_wr_in; // csrbus_wr | |
94 | output daemon_csrbus_wr_out; // csrbus_wr | |
95 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
96 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write | |
97 | // data | |
98 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
99 | input rst_l; // HW reset | |
100 | output rst_l_out; // HW reset | |
101 | input por_l; // HW reset | |
102 | output por_l_out; // HW reset | |
103 | ||
104 | //==================================================== | |
105 | // Type declarations | |
106 | //==================================================== | |
107 | wire clk; // Clock signal | |
108 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
109 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data | |
110 | wire ilu_log_en_select_pulse; // select | |
111 | wire ilu_log_en_select_pulse_out; // select | |
112 | wire ilu_int_en_select_pulse; // select | |
113 | wire ilu_int_en_select_pulse_out; // select | |
114 | wire ilu_en_err_select; // select | |
115 | wire ilu_en_err_select_out; // select | |
116 | wire ilu_log_err_select_pulse; // select | |
117 | wire ilu_log_err_select_pulse_out; // select | |
118 | wire pec_int_en_select_pulse; // select | |
119 | wire pec_int_en_select_pulse_out; // select | |
120 | wire pec_en_err_select; // select | |
121 | wire pec_en_err_select_out; // select | |
122 | wire ilu_diagnos_select_pulse; // select | |
123 | wire ilu_diagnos_select_pulse_out; // select | |
124 | wire ilu_log_err_rw1c_alias; // SW load | |
125 | wire ilu_log_err_rw1c_alias_out; // alias | |
126 | wire ilu_log_err_rw1s_alias; // SW load | |
127 | wire ilu_log_err_rw1s_alias_out; // alias | |
128 | wire daemon_csrbus_wr_in; // csrbus_wr | |
129 | wire daemon_csrbus_wr_out; // csrbus_wr | |
130 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
131 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data | |
132 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
133 | wire rst_l; // HW reset | |
134 | wire rst_l_out; // HW reset | |
135 | wire por_l; // HW reset | |
136 | wire por_l_out; // HW reset | |
137 | ||
138 | ||
139 | //==================================================== | |
140 | // Assignments only | |
141 | //==================================================== | |
142 | assign ilu_log_en_select_pulse_out = ilu_log_en_select_pulse; | |
143 | assign ilu_int_en_select_pulse_out = ilu_int_en_select_pulse; | |
144 | assign ilu_en_err_select_out = ilu_en_err_select; | |
145 | assign ilu_log_err_select_pulse_out = ilu_log_err_select_pulse; | |
146 | assign pec_int_en_select_pulse_out = pec_int_en_select_pulse; | |
147 | assign pec_en_err_select_out = pec_en_err_select; | |
148 | assign ilu_diagnos_select_pulse_out = ilu_diagnos_select_pulse; | |
149 | assign ilu_log_err_rw1c_alias_out = ilu_log_err_rw1c_alias; | |
150 | assign ilu_log_err_rw1s_alias_out = ilu_log_err_rw1s_alias; | |
151 | assign rst_l_out = rst_l; | |
152 | assign por_l_out = por_l; | |
153 | assign daemon_csrbus_wr_out = daemon_csrbus_wr_in; | |
154 | assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in; | |
155 | ||
156 | ||
157 | //===================================================== | |
158 | // OUTPUT: read_data_out | |
159 | //===================================================== | |
160 | dmu_ilu_cib_csrpipe_5 dmu_ilu_cib_csrpipe_5_inst_1 | |
161 | ( | |
162 | .clk (clk), | |
163 | .rst_l (rst_l), | |
164 | .reg_in (1'b0), | |
165 | .reg_out (1'b0), | |
166 | .data0 (read_data_0), | |
167 | .sel0 (1'b1), | |
168 | .data1 (read_data_1), | |
169 | .sel1 (1'b1), | |
170 | .data2 (64'b0), | |
171 | .sel2 (1'b1), | |
172 | .data3 (64'b0), | |
173 | .sel3 (1'b1), | |
174 | .data4 (64'b0), | |
175 | .sel4 (1'b1), | |
176 | .out (read_data_0_out) | |
177 | ); | |
178 | ||
179 | endmodule // dmu_ilu_cib_stage_mux_only |