[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_ilu_eil_bufmgr.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_ilu_eil_bufmgr.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
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// ========== Copyright Header End ============================================
module dmu_ilu_eil_bufmgr (
				clk,
				rst_l,
				
				d2p_ehb_addr,
				
				d2p_ech_wptr,
				d2p_erh_wptr,
				p2d_ech_rptr,
				p2d_erh_rptr,
				
				p2d_ecd_rptr,
				p2d_erd_rptr,
				
				cib2eil_drain,
                                cib2eil_pec_drain,
				
				rcd_is_cpl,
				rcd_is_cpl_reg,
				edb_wptr,
				
				n_d2p_ehb_we,
				edb_wptr_inc,
				
				ehb_full,
				ecd_full,
				erd_full,
				edb_full_adv,
				
				// debug signals 
				erh_full,
				ech_full,
				erd_full_adv,
				ecd_full_adv,
				il2cl_gr_16 );
  
  // synopsys sync_set_reset "rst_l"

  // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

  //------------------------------------------------------------------------
  //  Clock and Reset Signals
  //------------------------------------------------------------------------
  input           clk;	             // input clock
  input 	  rst_l;	     // input reset
  
  //------------------------------------------------------------------------
  // EHB interface
  //------------------------------------------------------------------------ 
  output [5:0] 	  d2p_ehb_addr;      // EHB write pointer

  //------------------------------------------------------------------------
  // EHB interface
  //------------------------------------------------------------------------ 
  output  	  il2cl_gr_16;      // for stall

  //------------------------------------------------------------------------
  // EHB management pointers
  //------------------------------------------------------------------------  
  output [5:0] 	  d2p_ech_wptr;      // gray-coded cpl-buffer in EHB write pointer
  input [5:0] 	  p2d_ech_rptr;      // gray-coded cpl-buffer in EHB read pointer
  output [5:0] 	  d2p_erh_wptr;      // gray-coded req-buffer in EHB write pointer
  input [5:0] 	  p2d_erh_rptr;      // gray-coded req-buffer in EHB read pointer

  //------------------------------------------------------------------------
  // EDB management pointers
  //------------------------------------------------------------------------
  input [`FIRE_P2D_ECD_RPTR_WDTH-1:0]  p2d_ecd_rptr; // gray-coded EDB DMA Cpl buf rd pointer
  input [`FIRE_P2D_ERD_RPTR_WDTH-1:0]  p2d_erd_rptr; // gray-coded EDB PIO Wr buf rd pointer

  //------------------------------------------------------------------------
  // special handling
  //------------------------------------------------------------------------ 
  input           cib2eil_drain;            // combined drain signal
  input           cib2eil_pec_drain;        // caused by p2d_drain


  //------------------------------------------------------------------------
  // internal interface
  //------------------------------------------------------------------------ 
  input 	  n_d2p_ehb_we;     // EHB write stroke,         from xfrfsm.v
  input 	  edb_wptr_inc;     // increase EDB buffer wptr, from datafsm
  output [7:0]	  edb_wptr;         // to be injected to datapath, to datafsm
  input 	  rcd_is_cpl;       // 1- DMA cpl; 0- PIO req,   from rcdbldr.v
  input 	  rcd_is_cpl_reg;   // 1- DMA cpl; 0- PIO req,   from rcdbldr.v
  output 	  ehb_full;         // EHB full based on rcd type, to xfrfsm.v
  output 	  ecd_full;         // EDB/ECD full to datafsm.v
  output 	  erd_full;         // EDB/ERD full to datafsm.v
  output 	  edb_full_adv;
  
  //---------------------------------------------------------------------
  //  debug signals
  //---------------------------------------------------------------------
  output 	  erh_full;
  output 	  ech_full;
  output 	  erd_full_adv;
  output 	  ecd_full_adv;
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
  //------------------------------------------------------------------------
  // EDB management
  // -----------------------------------------------------------------------
  reg [7:0] 	  ecd_wptr;  // EDB cpl buffer wptr, [7] - roll over
  reg [7:0] 	  erd_wptr;  // EDB req buffer wptr, [7] - roll over
  
  //------------------------------------------------------------------------
  // EHB management
  // -----------------------------------------------------------------------
  reg [5:0] 	  d2p_ehb_addr;
  reg [5:0] 	  d2p_erh_wptr;         // gray-coded flop
  reg [5:0] 	  d2p_ech_wptr;         // gray-coded flop
  reg [5:0] 	  erh_wptr;             // binary pointer
  reg [5:0] 	  ech_wptr;             // binary pointer
  reg [5:0] 	  erh_rptr;             // binary pointer
  reg [5:0] 	  ech_rptr;             // binary pointer
  reg [7:0] 	  erd_rptr;             // binary pointer
  reg [7:0] 	  ecd_rptr;             // binary pointer

  // for advanced edb fullness check
  reg [7:0] 	  erd_wptr_adv;
  reg [7:0] 	  ecd_wptr_adv;

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~

  wire 		  ech_full;
  wire 		  erh_full;

  // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    
  wire [5:0] 	  n_d2p_erh_wptr;     // gray-coded
  wire [5:0] 	  n_d2p_ech_wptr;     // gray-coded
  wire [5:0] 	  n_d2p_ehb_addr;     // binary write pointer to EHB
  
  wire [5:0] 	  gray_erh_rptr;      // output from sync-flop
  wire [5:0] 	  gray_ech_rptr;      // output from sync-flop
  wire [5:0] 	  n_erh_rptr;         // binary pointer
  wire [5:0] 	  n_ech_rptr;         // binary pointer

  wire [7:0] 	  gray_erd_rptr;      // output from sync-flop
  wire [7:0] 	  gray_ecd_rptr;      // output from sync-flop
  wire [7:0] 	  n_erd_rptr;         // binary pointer
  wire [7:0] 	  n_ecd_rptr;         // binary pointer

  wire 		  ld_ech_wptr;
  wire 		  ld_erh_wptr;

  wire 		  ld_ecd_wptr;
  wire 		  ld_erd_wptr;

  // for advanced edb fullness check
  wire 		  erd_full_adv;
  wire 		  ecd_full_adv;
	 
  // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<


  // >>>>>>>>>>>>>>>>>>>>>>>>> Function Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<
   
  // converts gray-coded to binary-coded (6-bit wide)
  function [5:0] gray2bin6;
    input [5:0] gray;
    integer i;
    reg temp;
    begin
      temp = 0;
      for (i=5; i>=0; i=i-1)
        begin	
	  temp = temp ^ gray[i];
          gray2bin6[i] = temp;
        end
    end
  endfunction // gray2bin6

  // converts gray-coded to binary-coded (8-bit wide)
  function [7:0] gray2bin8;
    input [7:0] gray;
    integer i;
    reg temp;
    begin
      temp = 0;
      for (i=7; i>=0; i=i-1)
        begin	
	  temp = temp ^ gray[i];
          gray2bin8[i] = temp;
        end
    end
  endfunction // gray2bin8
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
  
  // 0in known_driven -var ld_ech_wptr
  // 0in known_driven -var ld_erh_wptr
  // 0in known_driven -var ld_ecd_wptr
  // 0in known_driven -var ld_erd_wptr
     
  //------------------------------------------------------------------------
  // EHB management
  //------------------------------------------------------------------------

  // convert binary to gray-coded
  assign n_d2p_erh_wptr = (erh_wptr >> 1) ^ erh_wptr;   
  assign n_d2p_ech_wptr = (ech_wptr >> 1) ^ ech_wptr;

  // write pointer to EHB
  assign n_d2p_ehb_addr = rcd_is_cpl ? {1'b0, ech_wptr[4:0]} : 
                                       {1'b1, erh_wptr[4:0]};

  // convert gray-coded to binary
  assign n_erh_rptr = gray2bin6(gray_erh_rptr);
  assign n_ech_rptr = gray2bin6(gray_ech_rptr);

//BPn2 12-16-05  check for 16 or less entries in ehb and stall crm arb 
reg		gr_16;
  // create some constants which are easy to change with eco
reg	[4:0]	fifteen,sixteen;
  always @ (posedge clk)
	if(~rst_l) begin
      fifteen <= {5'b01111};
      sixteen <= {5'b10000};
    end
    else begin
      fifteen <= {5'b01111};
      sixteen <= {5'b10000};
    end
wire	il2cl_gr_16 = gr_16 & ~(cib2eil_drain | cib2eil_pec_drain) ;
always @(erh_wptr or erh_rptr or sixteen or fifteen ) begin
	gr_16 = 1'b0;
	
	case({erh_wptr[5],erh_rptr[5]})
	2'b00:	if ( (erh_wptr[4:0] - erh_rptr[4:0]) <= sixteen )	//
		gr_16 = 1'b0;
		else 
		gr_16 = 1'b1;

	2'b01:	if ( ( (5'b11111 - erh_rptr[4:0]) + erh_wptr[4:0]) <= fifteen )
		gr_16 = 1'b0;
		else 
		gr_16 = 1'b1;

	2'b10:	if ( ( (5'b11111 - erh_rptr[4:0]) + erh_wptr[4:0]) <= fifteen )
		gr_16 = 1'b0;
		else 
		gr_16 = 1'b1;


	2'b11:	if ( (erh_wptr[4:0] - erh_rptr[4:0]) <= sixteen )
		gr_16 = 1'b0;
		else 
		gr_16 = 1'b1;

	endcase
end


  // EHB fullness
  assign erh_full = (erh_wptr[4:0] == erh_rptr[4:0]) & (erh_wptr[5] ^ erh_rptr[5]);
  assign ech_full = (ech_wptr[4:0] == ech_rptr[4:0]) & (ech_wptr[5] ^ ech_rptr[5]);
  assign ehb_full = (rcd_is_cpl ? ech_full : erh_full) & (~cib2eil_drain);

  // load signals
  assign ld_ech_wptr = n_d2p_ehb_we & rcd_is_cpl;
  assign ld_erh_wptr = n_d2p_ehb_we & !rcd_is_cpl;
  
  // EHB pointers
  always @ (posedge clk)
	if(~rst_l) begin
      erh_rptr <= {6{1'b0}};
      ech_rptr <= {6{1'b0}};
    end
    else begin
      erh_rptr <= n_erh_rptr;
      ech_rptr <= n_ech_rptr;
    end
  
  always @ (posedge clk)
    if ((!rst_l) | cib2eil_pec_drain) begin
      erh_wptr <= 6'b0;
      ech_wptr <= 6'b0;
    end
    else begin
      if (ld_ech_wptr) begin 
	ech_wptr <= ech_wptr + 1'b1;
      end
      else if (ld_erh_wptr) begin
	erh_wptr <= erh_wptr + 1'b1;
      end
    end

  // bug fix P544 
  always @ (posedge clk) 
	if(~rst_l) begin
    d2p_ech_wptr <= {6{1'b0}};
    d2p_erh_wptr <= {6{1'b0}};
    d2p_ehb_addr <= {6{1'b0}};
	end
	else begin
    d2p_ech_wptr <= n_d2p_ech_wptr;
    d2p_erh_wptr <= n_d2p_erh_wptr;
    d2p_ehb_addr <= n_d2p_ehb_addr;
  end
     
  //------------------------------------------------------------------------
  // EDB management
  //------------------------------------------------------------------------

  // write pointer to EDB
  assign edb_wptr = rcd_is_cpl_reg ? {1'b0, ecd_wptr[6:0]} : 
                                 {1'b1, erd_wptr[6:0]};

  // convert gray-coded to binary
  assign n_erd_rptr = gray2bin8(gray_erd_rptr);
  assign n_ecd_rptr = gray2bin8(gray_ecd_rptr);

  // EDB fullness
  assign erd_full_adv = (erd_wptr_adv[6:0] == erd_rptr[6:0]) & 
			  (erd_wptr_adv[7] ^ erd_rptr[7]);
  assign ecd_full_adv = (ecd_wptr_adv[6:0] == ecd_rptr[6:0]) & 
			  (ecd_wptr_adv[7] ^ ecd_rptr[7]);
  assign edb_full_adv = rcd_is_cpl ? ecd_full_adv : erd_full_adv;
	 
  assign erd_full = (erd_wptr[6:0] == erd_rptr[6:0]) & 
		      (erd_wptr[7] ^ erd_rptr[7]);
  assign ecd_full = (ecd_wptr[6:0] == ecd_rptr[6:0]) & 
		      (ecd_wptr[7] ^ ecd_rptr[7]);

  // load signals
  assign ld_ecd_wptr = edb_wptr_inc & rcd_is_cpl_reg;
  assign ld_erd_wptr = edb_wptr_inc & !rcd_is_cpl_reg;
  
  // EDB pointers
  always @ (posedge clk)
	if(~rst_l) begin
      erd_rptr <= {8{1'b0}};
      ecd_rptr <= {8{1'b0}};
    end
    else begin
      erd_rptr <= n_erd_rptr;
      ecd_rptr <= n_ecd_rptr;
    end
  
  always @ (posedge clk)
    if ((!rst_l) | cib2eil_pec_drain) begin
      erd_wptr <= 8'b0;
      ecd_wptr <= 8'b0;
      erd_wptr_adv <= 8'b1;
      ecd_wptr_adv <= 8'b1;
    end
    else begin
      if (ld_ecd_wptr) begin 
	ecd_wptr <= ecd_wptr + 1'b1;
	ecd_wptr_adv <= ecd_wptr_adv + 1'b1;
      end
      else if (ld_erd_wptr) begin 
	erd_wptr <= erd_wptr + 1'b1;
	erd_wptr_adv <= erd_wptr_adv + 1'b1;
      end
    end
   
			   
  // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

  // sync-flop instantiations for p2d_erh_rptr
//  pcie_common_sync_flop #(6) erh_sync_flop(
//                                           .clk(clk),
//                                           .din(p2d_erh_rptr),
//                                           .dout(gray_erh_rptr)); 
  cl_a1_clksyncff_4x erh_sync_flop_5 ( .d(p2d_erh_rptr[5]), .si(1'b0), .q( gray_erh_rptr[5]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erh_sync_flop_4 ( .d(p2d_erh_rptr[4]), .si(1'b0), .q( gray_erh_rptr[4]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erh_sync_flop_3 ( .d(p2d_erh_rptr[3]), .si(1'b0), .q( gray_erh_rptr[3]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erh_sync_flop_2 ( .d(p2d_erh_rptr[2]), .si(1'b0), .q( gray_erh_rptr[2]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erh_sync_flop_1 ( .d(p2d_erh_rptr[1]), .si(1'b0), .q( gray_erh_rptr[1]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erh_sync_flop_0 ( .d(p2d_erh_rptr[0]), .si(1'b0), .q( gray_erh_rptr[0]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );

  // sync-flop instantiations for p2d_ech_rptr
//  pcie_common_sync_flop #(6) ech_sync_flop(
//                                           .clk(clk),
//                                           .din(p2d_ech_rptr),
//                                           .dout(gray_ech_rptr));
  cl_a1_clksyncff_4x ech_sync_flop_5 ( .d(p2d_ech_rptr[5]), .si(1'b0), .q( gray_ech_rptr[5]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ech_sync_flop_4 ( .d(p2d_ech_rptr[4]), .si(1'b0), .q( gray_ech_rptr[4]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ech_sync_flop_3 ( .d(p2d_ech_rptr[3]), .si(1'b0), .q( gray_ech_rptr[3]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ech_sync_flop_2 ( .d(p2d_ech_rptr[2]), .si(1'b0), .q( gray_ech_rptr[2]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ech_sync_flop_1 ( .d(p2d_ech_rptr[1]), .si(1'b0), .q( gray_ech_rptr[1]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ech_sync_flop_0 ( .d(p2d_ech_rptr[0]), .si(1'b0), .q( gray_ech_rptr[0]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );

  // sync-flop instantiations for p2d_erd_rptr
//  pcie_common_sync_flop #(8) erd_sync_flop(
//                                           .clk(clk),
//                                           .din(p2d_erd_rptr),
//                                           .dout(gray_erd_rptr)); 
  cl_a1_clksyncff_4x erd_sync_flop_7 ( .d(p2d_erd_rptr[7]), .si(1'b0), .q( gray_erd_rptr[7]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_6 ( .d(p2d_erd_rptr[6]), .si(1'b0), .q( gray_erd_rptr[6]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_5 ( .d(p2d_erd_rptr[5]), .si(1'b0), .q( gray_erd_rptr[5]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_4 ( .d(p2d_erd_rptr[4]), .si(1'b0), .q( gray_erd_rptr[4]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_3 ( .d(p2d_erd_rptr[3]), .si(1'b0), .q( gray_erd_rptr[3]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_2 ( .d(p2d_erd_rptr[2]), .si(1'b0), .q( gray_erd_rptr[2]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_1 ( .d(p2d_erd_rptr[1]), .si(1'b0), .q( gray_erd_rptr[1]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x erd_sync_flop_0 ( .d(p2d_erd_rptr[0]), .si(1'b0), .q( gray_erd_rptr[0]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );

  // sync-flop instantiations for p2d_ecd_rptr
//  pcie_common_sync_flop #(8) ecd_sync_flop(
//                                           .clk(clk),
//                                           .din(p2d_ecd_rptr),
//                                           .dout(gray_ecd_rptr));
  cl_a1_clksyncff_4x ecd_sync_flop_7 ( .d(p2d_ecd_rptr[7]), .si(1'b0), .q( gray_ecd_rptr[7]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_6 ( .d(p2d_ecd_rptr[6]), .si(1'b0), .q( gray_ecd_rptr[6]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_5 ( .d(p2d_ecd_rptr[5]), .si(1'b0), .q( gray_ecd_rptr[5]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_4 ( .d(p2d_ecd_rptr[4]), .si(1'b0), .q( gray_ecd_rptr[4]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_3 ( .d(p2d_ecd_rptr[3]), .si(1'b0), .q( gray_ecd_rptr[3]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_2 ( .d(p2d_ecd_rptr[2]), .si(1'b0), .q( gray_ecd_rptr[2]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_1 ( .d(p2d_ecd_rptr[1]), .si(1'b0), .q( gray_ecd_rptr[1]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
  cl_a1_clksyncff_4x ecd_sync_flop_0 ( .d(p2d_ecd_rptr[0]), .si(1'b0), .q( gray_ecd_rptr[0]), .so(),
        .l1clk(clk), .siclk(1'b0), .soclk(1'b0) );


endmodule // dmu_ilu_eil_bufmgr
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_ilu_eil_bufmgr.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
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	34	// ========== Copyright Header End ============================================
	35	module dmu_ilu_eil_bufmgr (
	36	clk,
	37	rst_l,
	38
	39	d2p_ehb_addr,
	40
	41	d2p_ech_wptr,
	42	d2p_erh_wptr,
	43	p2d_ech_rptr,
	44	p2d_erh_rptr,
	45
	46	p2d_ecd_rptr,
	47	p2d_erd_rptr,
	48
	49	cib2eil_drain,
	50	cib2eil_pec_drain,
	51
	52	rcd_is_cpl,
	53	rcd_is_cpl_reg,
	54	edb_wptr,
	55
	56	n_d2p_ehb_we,
	57	edb_wptr_inc,
	58
	59	ehb_full,
	60	ecd_full,
	61	erd_full,
	62	edb_full_adv,
	63
	64	// debug signals
65	erh_full,
66	ech_full,
67	erd_full_adv,
68	ecd_full_adv,
69	il2cl_gr_16 );
70
71	// synopsys sync_set_reset "rst_l"
72
73	// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
74
75	//------------------------------------------------------------------------
76	// Clock and Reset Signals
77	//------------------------------------------------------------------------
78	input clk; // input clock
79	input rst_l; // input reset
80
81	//------------------------------------------------------------------------
82	// EHB interface
83	//------------------------------------------------------------------------
84	output [5:0] d2p_ehb_addr; // EHB write pointer
85
86	//------------------------------------------------------------------------
87	// EHB interface
88	//------------------------------------------------------------------------
89	output il2cl_gr_16; // for stall
90
91	//------------------------------------------------------------------------
92	// EHB management pointers
93	//------------------------------------------------------------------------
94	output [5:0] d2p_ech_wptr; // gray-coded cpl-buffer in EHB write pointer
95	input [5:0] p2d_ech_rptr; // gray-coded cpl-buffer in EHB read pointer
96	output [5:0] d2p_erh_wptr; // gray-coded req-buffer in EHB write pointer
97	input [5:0] p2d_erh_rptr; // gray-coded req-buffer in EHB read pointer
98
99	//------------------------------------------------------------------------
100	// EDB management pointers
101	//------------------------------------------------------------------------
102	input [`FIRE_P2D_ECD_RPTR_WDTH-1:0] p2d_ecd_rptr; // gray-coded EDB DMA Cpl buf rd pointer
103	input [`FIRE_P2D_ERD_RPTR_WDTH-1:0] p2d_erd_rptr; // gray-coded EDB PIO Wr buf rd pointer
104
105	//------------------------------------------------------------------------
106	// special handling
107	//------------------------------------------------------------------------
108	input cib2eil_drain; // combined drain signal
109	input cib2eil_pec_drain; // caused by p2d_drain
110
111
112	//------------------------------------------------------------------------
113	// internal interface
114	//------------------------------------------------------------------------
115	input n_d2p_ehb_we; // EHB write stroke, from xfrfsm.v
116	input edb_wptr_inc; // increase EDB buffer wptr, from datafsm
117	output [7:0] edb_wptr; // to be injected to datapath, to datafsm
118	input rcd_is_cpl; // 1- DMA cpl; 0- PIO req, from rcdbldr.v
119	input rcd_is_cpl_reg; // 1- DMA cpl; 0- PIO req, from rcdbldr.v
120	output ehb_full; // EHB full based on rcd type, to xfrfsm.v
121	output ecd_full; // EDB/ECD full to datafsm.v
122	output erd_full; // EDB/ERD full to datafsm.v
123	output edb_full_adv;
124
125	//---------------------------------------------------------------------
126	// debug signals
127	//---------------------------------------------------------------------
128	output erh_full;
129	output ech_full;
130	output erd_full_adv;
131	output ecd_full_adv;
132
133	// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
134
135	// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
136
137	//------------------------------------------------------------------------
138	// EDB management
139	// -----------------------------------------------------------------------
140	reg [7:0] ecd_wptr; // EDB cpl buffer wptr, [7] - roll over
141	reg [7:0] erd_wptr; // EDB req buffer wptr, [7] - roll over
142
143	//------------------------------------------------------------------------
144	// EHB management
145	// -----------------------------------------------------------------------
146	reg [5:0] d2p_ehb_addr;
147	reg [5:0] d2p_erh_wptr; // gray-coded flop
148	reg [5:0] d2p_ech_wptr; // gray-coded flop
149	reg [5:0] erh_wptr; // binary pointer
150	reg [5:0] ech_wptr; // binary pointer
151	reg [5:0] erh_rptr; // binary pointer
152	reg [5:0] ech_rptr; // binary pointer
153	reg [7:0] erd_rptr; // binary pointer
154	reg [7:0] ecd_rptr; // binary pointer
155
156	// for advanced edb fullness check
157	reg [7:0] erd_wptr_adv;
158	reg [7:0] ecd_wptr_adv;
159
160	// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~
161
162	wire ech_full;
163	wire erh_full;
164
165	// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
166
167	wire [5:0] n_d2p_erh_wptr; // gray-coded
168	wire [5:0] n_d2p_ech_wptr; // gray-coded
169	wire [5:0] n_d2p_ehb_addr; // binary write pointer to EHB
170
171	wire [5:0] gray_erh_rptr; // output from sync-flop
172	wire [5:0] gray_ech_rptr; // output from sync-flop
173	wire [5:0] n_erh_rptr; // binary pointer
174	wire [5:0] n_ech_rptr; // binary pointer
175
176	wire [7:0] gray_erd_rptr; // output from sync-flop
177	wire [7:0] gray_ecd_rptr; // output from sync-flop
178	wire [7:0] n_erd_rptr; // binary pointer
179	wire [7:0] n_ecd_rptr; // binary pointer
180
181	wire ld_ech_wptr;
182	wire ld_erh_wptr;
183
184	wire ld_ecd_wptr;
185	wire ld_erd_wptr;
186
187	// for advanced edb fullness check
188	wire erd_full_adv;
189	wire ecd_full_adv;
190
191	// >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
192
193
194	// >>>>>>>>>>>>>>>>>>>>>>>>> Function Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<
195
196	// converts gray-coded to binary-coded (6-bit wide)
197	function [5:0] gray2bin6;
198	input [5:0] gray;
199	integer i;
200	reg temp;
201	begin
202	temp = 0;
203	for (i=5; i>=0; i=i-1)
204	begin
205	temp = temp ^ gray[i];
206	gray2bin6[i] = temp;
207	end
208	end
209	endfunction // gray2bin6
210
211	// converts gray-coded to binary-coded (8-bit wide)
212	function [7:0] gray2bin8;
213	input [7:0] gray;
214	integer i;
215	reg temp;
216	begin
217	temp = 0;
218	for (i=7; i>=0; i=i-1)
219	begin
220	temp = temp ^ gray[i];
221	gray2bin8[i] = temp;
222	end
223	end
224	endfunction // gray2bin8
225
226	// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
227
228	// 0in known_driven -var ld_ech_wptr
229	// 0in known_driven -var ld_erh_wptr
230	// 0in known_driven -var ld_ecd_wptr
231	// 0in known_driven -var ld_erd_wptr
232
233	//------------------------------------------------------------------------
234	// EHB management
235	//------------------------------------------------------------------------
236
237	// convert binary to gray-coded
238	assign n_d2p_erh_wptr = (erh_wptr >> 1) ^ erh_wptr;
239	assign n_d2p_ech_wptr = (ech_wptr >> 1) ^ ech_wptr;
240
241	// write pointer to EHB
242	assign n_d2p_ehb_addr = rcd_is_cpl ? {1'b0, ech_wptr[4:0]} :
243	{1'b1, erh_wptr[4:0]};
244
245	// convert gray-coded to binary
246	assign n_erh_rptr = gray2bin6(gray_erh_rptr);
247	assign n_ech_rptr = gray2bin6(gray_ech_rptr);
248
249	//BPn2 12-16-05 check for 16 or less entries in ehb and stall crm arb
250	reg gr_16;
251	// create some constants which are easy to change with eco
252	reg [4:0] fifteen,sixteen;
253	always @ (posedge clk)
254	if(~rst_l) begin
255	fifteen <= {5'b01111};
256	sixteen <= {5'b10000};
257	end
258	else begin
259	fifteen <= {5'b01111};
260	sixteen <= {5'b10000};
261	end
262	wire il2cl_gr_16 = gr_16 & ~(cib2eil_drain \| cib2eil_pec_drain) ;
263	always @(erh_wptr or erh_rptr or sixteen or fifteen ) begin
264	gr_16 = 1'b0;
265
266	case({erh_wptr[5],erh_rptr[5]})
267	2'b00: if ( (erh_wptr[4:0] - erh_rptr[4:0]) <= sixteen ) //
268	gr_16 = 1'b0;
269	else
270	gr_16 = 1'b1;
271
272	2'b01: if ( ( (5'b11111 - erh_rptr[4:0]) + erh_wptr[4:0]) <= fifteen )
273	gr_16 = 1'b0;
274	else
275	gr_16 = 1'b1;
276
277	2'b10: if ( ( (5'b11111 - erh_rptr[4:0]) + erh_wptr[4:0]) <= fifteen )
278	gr_16 = 1'b0;
279	else
280	gr_16 = 1'b1;
281
282
283	2'b11: if ( (erh_wptr[4:0] - erh_rptr[4:0]) <= sixteen )
284	gr_16 = 1'b0;
285	else
286	gr_16 = 1'b1;
287
288	endcase
289	end
290
291
292
293
294	// EHB fullness
295	assign erh_full = (erh_wptr[4:0] == erh_rptr[4:0]) & (erh_wptr[5] ^ erh_rptr[5]);
296	assign ech_full = (ech_wptr[4:0] == ech_rptr[4:0]) & (ech_wptr[5] ^ ech_rptr[5]);
297	assign ehb_full = (rcd_is_cpl ? ech_full : erh_full) & (~cib2eil_drain);
298
299	// load signals
300	assign ld_ech_wptr = n_d2p_ehb_we & rcd_is_cpl;
301	assign ld_erh_wptr = n_d2p_ehb_we & !rcd_is_cpl;
302
303	// EHB pointers
304	always @ (posedge clk)
305	if(~rst_l) begin
306	erh_rptr <= {6{1'b0}};
307	ech_rptr <= {6{1'b0}};
308	end
309	else begin
310	erh_rptr <= n_erh_rptr;
311	ech_rptr <= n_ech_rptr;
312	end
313
314	always @ (posedge clk)
315	if ((!rst_l) \| cib2eil_pec_drain) begin
316	erh_wptr <= 6'b0;
317	ech_wptr <= 6'b0;
318	end
319	else begin
320	if (ld_ech_wptr) begin
321	ech_wptr <= ech_wptr + 1'b1;
322	end
323	else if (ld_erh_wptr) begin
324	erh_wptr <= erh_wptr + 1'b1;
325	end
326	end
327
328	// bug fix P544
329	always @ (posedge clk)
330	if(~rst_l) begin
331	d2p_ech_wptr <= {6{1'b0}};
332	d2p_erh_wptr <= {6{1'b0}};
333	d2p_ehb_addr <= {6{1'b0}};
334	end
335	else begin
336	d2p_ech_wptr <= n_d2p_ech_wptr;
337	d2p_erh_wptr <= n_d2p_erh_wptr;
338	d2p_ehb_addr <= n_d2p_ehb_addr;
339	end
340
341	//------------------------------------------------------------------------
342	// EDB management
343	//------------------------------------------------------------------------
344
345	// write pointer to EDB
346	assign edb_wptr = rcd_is_cpl_reg ? {1'b0, ecd_wptr[6:0]} :
347	{1'b1, erd_wptr[6:0]};
348
349	// convert gray-coded to binary
350	assign n_erd_rptr = gray2bin8(gray_erd_rptr);
351	assign n_ecd_rptr = gray2bin8(gray_ecd_rptr);
352
353	// EDB fullness
354	assign erd_full_adv = (erd_wptr_adv[6:0] == erd_rptr[6:0]) &
355	(erd_wptr_adv[7] ^ erd_rptr[7]);
356	assign ecd_full_adv = (ecd_wptr_adv[6:0] == ecd_rptr[6:0]) &
357	(ecd_wptr_adv[7] ^ ecd_rptr[7]);
358	assign edb_full_adv = rcd_is_cpl ? ecd_full_adv : erd_full_adv;
359
360	assign erd_full = (erd_wptr[6:0] == erd_rptr[6:0]) &
361	(erd_wptr[7] ^ erd_rptr[7]);
362	assign ecd_full = (ecd_wptr[6:0] == ecd_rptr[6:0]) &
363	(ecd_wptr[7] ^ ecd_rptr[7]);
364
365	// load signals
366	assign ld_ecd_wptr = edb_wptr_inc & rcd_is_cpl_reg;
367	assign ld_erd_wptr = edb_wptr_inc & !rcd_is_cpl_reg;
368
369	// EDB pointers
370	always @ (posedge clk)
371	if(~rst_l) begin
372	erd_rptr <= {8{1'b0}};
373	ecd_rptr <= {8{1'b0}};
374	end
375	else begin
376	erd_rptr <= n_erd_rptr;
377	ecd_rptr <= n_ecd_rptr;
378	end
379
380	always @ (posedge clk)
381	if ((!rst_l) \| cib2eil_pec_drain) begin
382	erd_wptr <= 8'b0;
383	ecd_wptr <= 8'b0;
384	erd_wptr_adv <= 8'b1;
385	ecd_wptr_adv <= 8'b1;
386	end
387	else begin
388	if (ld_ecd_wptr) begin
389	ecd_wptr <= ecd_wptr + 1'b1;
390	ecd_wptr_adv <= ecd_wptr_adv + 1'b1;
391	end
392	else if (ld_erd_wptr) begin
393	erd_wptr <= erd_wptr + 1'b1;
394	erd_wptr_adv <= erd_wptr_adv + 1'b1;
395	end
396	end
397
398
399	// >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
400
401	// sync-flop instantiations for p2d_erh_rptr
402	// pcie_common_sync_flop #(6) erh_sync_flop(
403	// .clk(clk),
404	// .din(p2d_erh_rptr),
405	// .dout(gray_erh_rptr));
406	cl_a1_clksyncff_4x erh_sync_flop_5 ( .d(p2d_erh_rptr[5]), .si(1'b0), .q( gray_erh_rptr[5]), .so(),
407	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
408	cl_a1_clksyncff_4x erh_sync_flop_4 ( .d(p2d_erh_rptr[4]), .si(1'b0), .q( gray_erh_rptr[4]), .so(),
409	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
410	cl_a1_clksyncff_4x erh_sync_flop_3 ( .d(p2d_erh_rptr[3]), .si(1'b0), .q( gray_erh_rptr[3]), .so(),
411	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
412	cl_a1_clksyncff_4x erh_sync_flop_2 ( .d(p2d_erh_rptr[2]), .si(1'b0), .q( gray_erh_rptr[2]), .so(),
413	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
414	cl_a1_clksyncff_4x erh_sync_flop_1 ( .d(p2d_erh_rptr[1]), .si(1'b0), .q( gray_erh_rptr[1]), .so(),
415	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
416	cl_a1_clksyncff_4x erh_sync_flop_0 ( .d(p2d_erh_rptr[0]), .si(1'b0), .q( gray_erh_rptr[0]), .so(),
417	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
418
419	// sync-flop instantiations for p2d_ech_rptr
420	// pcie_common_sync_flop #(6) ech_sync_flop(
421	// .clk(clk),
422	// .din(p2d_ech_rptr),
423	// .dout(gray_ech_rptr));
424	cl_a1_clksyncff_4x ech_sync_flop_5 ( .d(p2d_ech_rptr[5]), .si(1'b0), .q( gray_ech_rptr[5]), .so(),
425	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
426	cl_a1_clksyncff_4x ech_sync_flop_4 ( .d(p2d_ech_rptr[4]), .si(1'b0), .q( gray_ech_rptr[4]), .so(),
427	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
428	cl_a1_clksyncff_4x ech_sync_flop_3 ( .d(p2d_ech_rptr[3]), .si(1'b0), .q( gray_ech_rptr[3]), .so(),
429	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
430	cl_a1_clksyncff_4x ech_sync_flop_2 ( .d(p2d_ech_rptr[2]), .si(1'b0), .q( gray_ech_rptr[2]), .so(),
431	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
432	cl_a1_clksyncff_4x ech_sync_flop_1 ( .d(p2d_ech_rptr[1]), .si(1'b0), .q( gray_ech_rptr[1]), .so(),
433	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
434	cl_a1_clksyncff_4x ech_sync_flop_0 ( .d(p2d_ech_rptr[0]), .si(1'b0), .q( gray_ech_rptr[0]), .so(),
435	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
436
437	// sync-flop instantiations for p2d_erd_rptr
438	// pcie_common_sync_flop #(8) erd_sync_flop(
439	// .clk(clk),
440	// .din(p2d_erd_rptr),
441	// .dout(gray_erd_rptr));
442	cl_a1_clksyncff_4x erd_sync_flop_7 ( .d(p2d_erd_rptr[7]), .si(1'b0), .q( gray_erd_rptr[7]), .so(),
443	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
444	cl_a1_clksyncff_4x erd_sync_flop_6 ( .d(p2d_erd_rptr[6]), .si(1'b0), .q( gray_erd_rptr[6]), .so(),
445	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
446	cl_a1_clksyncff_4x erd_sync_flop_5 ( .d(p2d_erd_rptr[5]), .si(1'b0), .q( gray_erd_rptr[5]), .so(),
447	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
448	cl_a1_clksyncff_4x erd_sync_flop_4 ( .d(p2d_erd_rptr[4]), .si(1'b0), .q( gray_erd_rptr[4]), .so(),
449	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
450	cl_a1_clksyncff_4x erd_sync_flop_3 ( .d(p2d_erd_rptr[3]), .si(1'b0), .q( gray_erd_rptr[3]), .so(),
451	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
452	cl_a1_clksyncff_4x erd_sync_flop_2 ( .d(p2d_erd_rptr[2]), .si(1'b0), .q( gray_erd_rptr[2]), .so(),
453	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
454	cl_a1_clksyncff_4x erd_sync_flop_1 ( .d(p2d_erd_rptr[1]), .si(1'b0), .q( gray_erd_rptr[1]), .so(),
455	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
456	cl_a1_clksyncff_4x erd_sync_flop_0 ( .d(p2d_erd_rptr[0]), .si(1'b0), .q( gray_erd_rptr[0]), .so(),
457	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
458
459	// sync-flop instantiations for p2d_ecd_rptr
460	// pcie_common_sync_flop #(8) ecd_sync_flop(
461	// .clk(clk),
462	// .din(p2d_ecd_rptr),
463	// .dout(gray_ecd_rptr));
464	cl_a1_clksyncff_4x ecd_sync_flop_7 ( .d(p2d_ecd_rptr[7]), .si(1'b0), .q( gray_ecd_rptr[7]), .so(),
465	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
466	cl_a1_clksyncff_4x ecd_sync_flop_6 ( .d(p2d_ecd_rptr[6]), .si(1'b0), .q( gray_ecd_rptr[6]), .so(),
467	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
468	cl_a1_clksyncff_4x ecd_sync_flop_5 ( .d(p2d_ecd_rptr[5]), .si(1'b0), .q( gray_ecd_rptr[5]), .so(),
469	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
470	cl_a1_clksyncff_4x ecd_sync_flop_4 ( .d(p2d_ecd_rptr[4]), .si(1'b0), .q( gray_ecd_rptr[4]), .so(),
471	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
472	cl_a1_clksyncff_4x ecd_sync_flop_3 ( .d(p2d_ecd_rptr[3]), .si(1'b0), .q( gray_ecd_rptr[3]), .so(),
473	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
474	cl_a1_clksyncff_4x ecd_sync_flop_2 ( .d(p2d_ecd_rptr[2]), .si(1'b0), .q( gray_ecd_rptr[2]), .so(),
475	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
476	cl_a1_clksyncff_4x ecd_sync_flop_1 ( .d(p2d_ecd_rptr[1]), .si(1'b0), .q( gray_ecd_rptr[1]), .so(),
477	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
478	cl_a1_clksyncff_4x ecd_sync_flop_0 ( .d(p2d_ecd_rptr[0]), .si(1'b0), .q( gray_ecd_rptr[0]), .so(),
479	.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
480
481
482	endmodule // dmu_ilu_eil_bufmgr