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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_dms.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_dms ( | |
36 | ||
37 | clk, | |
38 | rst_l, | |
39 | ||
40 | // Inputs from RDS | |
41 | ||
42 | rds2dms_data_sel, | |
43 | rds2dms_data, | |
44 | rds2dms_d_ptr, | |
45 | ||
46 | // Outputs to the DIU | |
47 | ||
48 | ||
49 | im2di_wr, | |
50 | im2di_addr, | |
51 | im2di_data, | |
52 | im2di_dpar, | |
53 | im2di_bmask | |
54 | ||
55 | ||
56 | ); | |
57 | ||
58 | ||
59 | //############################################################################ | |
60 | // PORT DECLARATIONS | |
61 | //############################################################################ | |
62 | ||
63 | //------------------------------------------------------------------------ | |
64 | // Clock and Reset Signals | |
65 | //------------------------------------------------------------------------ | |
66 | input clk; | |
67 | input rst_l; | |
68 | ||
69 | ||
70 | //------------------------------------------------------------------------ | |
71 | // Inputs from RDS Sub-block Signals | |
72 | //------------------------------------------------------------------------ | |
73 | input rds2dms_data_sel; | |
74 | input [127:0] rds2dms_data; | |
75 | input [3:0] rds2dms_d_ptr; | |
76 | ||
77 | ||
78 | ||
79 | //------------------------------------------------------------------------ | |
80 | // Outputs to DIU Block Signals | |
81 | //------------------------------------------------------------------------ | |
82 | ||
83 | output im2di_wr; | |
84 | output [`FIRE_DLC_IRD_ADDR_WDTH-1:0] im2di_addr; | |
85 | output [`FIRE_DLC_IRD_DATA_WDTH-1:0] im2di_data; | |
86 | output [`FIRE_DLC_IRD_DPAR_WDTH-1:0] im2di_dpar; | |
87 | output [`FIRE_DLC_IRD_BMASK_WDTH-1:0] im2di_bmask; | |
88 | ||
89 | ||
90 | ||
91 | ||
92 | //############################################################################ | |
93 | // PARAMETERS | |
94 | //############################################################################ | |
95 | ||
96 | //############################################################################ | |
97 | // SIGNAL DECLARATIONS | |
98 | //############################################################################ | |
99 | ||
100 | ||
101 | //************************************************** | |
102 | // Wire | |
103 | //************************************************** | |
104 | ||
105 | wire bmask_dpar; | |
106 | wire quad_0_dpar; | |
107 | wire quad_1_dpar; | |
108 | wire quad_2_dpar; | |
109 | wire quad_3_dpar; | |
110 | ||
111 | wire [`FIRE_DLC_IRD_DPAR_WDTH-1:0] rds2dms_dpar_del; | |
112 | ||
113 | //************************************************** | |
114 | // Registers that Are Not Flops | |
115 | //************************************************** | |
116 | wire [`FIRE_DLC_IRD_BMASK_WDTH-1:0] im2di_bmask; | |
117 | ||
118 | //************************************************** | |
119 | // Registers that Are Flops | |
120 | //************************************************** | |
121 | reg rds2dms_data_sel_del; | |
122 | reg [127:0] rds2dms_data_del; | |
123 | reg [3:0] rds2dms_d_ptr_del; | |
124 | ||
125 | reg im2di_wr; | |
126 | reg [`FIRE_DLC_IRD_ADDR_WDTH-1:0] im2di_addr; | |
127 | reg [`FIRE_DLC_IRD_DATA_WDTH-1:0] im2di_data; | |
128 | reg [`FIRE_DLC_IRD_DPAR_WDTH-1:0] im2di_dpar; | |
129 | ||
130 | //############################################################################ | |
131 | // ZERO IN CHECKERS | |
132 | //############################################################################ | |
133 | ||
134 | ||
135 | ||
136 | //############################################################################ | |
137 | // COMBINATIONAL LOGIC | |
138 | //############################################################################ | |
139 | ||
140 | //---------------------------------------------- | |
141 | // Outputs Bmask | |
142 | // | |
143 | // - Since the 16 bytes of data is always | |
144 | // valid can just hard wire to 1 | |
145 | // | |
146 | // - Also the 1 parity bit can also be | |
147 | // hard wireed to 1 for odd parity | |
148 | //---------------------------------------------- | |
149 | ||
150 | assign im2di_bmask = 16'hffff; | |
151 | assign bmask_dpar = 1'b1; | |
152 | ||
153 | ||
154 | //---------------------------------------------- | |
155 | // Outputs Data Parity | |
156 | // | |
157 | // - calculate 1 bit of parity for every 32 | |
158 | // bits of data | |
159 | // | |
160 | // - Do this off of the delayed data | |
161 | // | |
162 | // - Assign output next value | |
163 | // - {data3--0, bmask} | |
164 | //---------------------------------------------- | |
165 | ||
166 | assign quad_3_dpar = !(^rds2dms_data_del[127:96]); | |
167 | assign quad_2_dpar = !(^rds2dms_data_del[95:64]); | |
168 | assign quad_1_dpar = !(^rds2dms_data_del[63:32]); | |
169 | assign quad_0_dpar = !(^rds2dms_data_del[31:0]); | |
170 | ||
171 | assign rds2dms_dpar_del = {quad_3_dpar, quad_2_dpar, quad_1_dpar, quad_0_dpar, bmask_dpar}; | |
172 | ||
173 | ||
174 | //############################################################################ | |
175 | // SEQUENTIAL LOGIC | |
176 | //############################################################################ | |
177 | ||
178 | //----------------------------------------------------------------------------- | |
179 | // Delay the Data Record from the RDS to match pipe delay | |
180 | // | |
181 | //----------------------------------------------------------------------------- | |
182 | always @ (posedge clk) | |
183 | if (!rst_l) | |
184 | begin // At reset reset all of them to zero. | |
185 | rds2dms_data_del <= 128'h0; | |
186 | rds2dms_data_sel_del <= 1'h0; | |
187 | rds2dms_d_ptr_del <= 4'h0; | |
188 | end | |
189 | else | |
190 | begin | |
191 | rds2dms_data_del <= rds2dms_data; | |
192 | rds2dms_data_sel_del <= rds2dms_data_sel; | |
193 | rds2dms_d_ptr_del <= rds2dms_d_ptr; | |
194 | end | |
195 | ||
196 | ||
197 | //----------------------------------------------------------------------------- | |
198 | // Flop the Outputs to the DIU Block | |
199 | // | |
200 | //----------------------------------------------------------------------------- | |
201 | always @ (posedge clk) | |
202 | if (!rst_l) | |
203 | begin // At reset reset all of them to zero. | |
204 | im2di_wr <= 1'b0; | |
205 | im2di_addr <= {`FIRE_DLC_IRD_ADDR_WDTH{1'h0}}; | |
206 | im2di_data <= {`FIRE_DLC_IRD_DATA_WDTH{1'h0}}; | |
207 | im2di_dpar <= {`FIRE_DLC_IRD_DPAR_WDTH{1'h0}}; | |
208 | end | |
209 | else | |
210 | begin | |
211 | im2di_wr <= rds2dms_data_sel_del; | |
212 | im2di_addr <= rds2dms_d_ptr_del; | |
213 | im2di_data <= rds2dms_data_del; | |
214 | im2di_dpar <= rds2dms_dpar_del; | |
215 | end | |
216 | ||
217 | endmodule |