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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_eqs_addr_decode.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_eqs_addr_decode.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_eqs_addr_decode
36 (
37 clk,
38 rst_l,
39 daemon_csrbus_valid,
40 daemon_csrbus_addr,
41 csrbus_src_bus,
42 daemon_csrbus_wr,
43 daemon_csrbus_wr_out,
44 daemon_csrbus_wr_data,
45 daemon_csrbus_wr_data_out,
46 daemon_csrbus_mapped,
47 csrbus_acc_vio,
48 daemon_transaction_in_progress,
49 instance_id,
50 daemon_csrbus_done,
51 eq_base_address_select_pulse,
52 eq_ctrl_set_select_0,
53 eq_ctrl_set_select_1,
54 eq_ctrl_set_select_2,
55 eq_ctrl_set_select_3,
56 eq_ctrl_set_select_4,
57 eq_ctrl_set_select_5,
58 eq_ctrl_set_select_6,
59 eq_ctrl_set_select_7,
60 eq_ctrl_set_select_8,
61 eq_ctrl_set_select_9,
62 eq_ctrl_set_select_10,
63 eq_ctrl_set_select_11,
64 eq_ctrl_set_select_12,
65 eq_ctrl_set_select_13,
66 eq_ctrl_set_select_14,
67 eq_ctrl_set_select_15,
68 eq_ctrl_set_select_16,
69 eq_ctrl_set_select_17,
70 eq_ctrl_set_select_18,
71 eq_ctrl_set_select_19,
72 eq_ctrl_set_select_20,
73 eq_ctrl_set_select_21,
74 eq_ctrl_set_select_22,
75 eq_ctrl_set_select_23,
76 eq_ctrl_set_select_24,
77 eq_ctrl_set_select_25,
78 eq_ctrl_set_select_26,
79 eq_ctrl_set_select_27,
80 eq_ctrl_set_select_28,
81 eq_ctrl_set_select_29,
82 eq_ctrl_set_select_30,
83 eq_ctrl_set_select_31,
84 eq_ctrl_set_select_32,
85 eq_ctrl_set_select_33,
86 eq_ctrl_set_select_34,
87 eq_ctrl_set_select_35,
88 eq_ctrl_clr_select_0,
89 eq_ctrl_clr_select_1,
90 eq_ctrl_clr_select_2,
91 eq_ctrl_clr_select_3,
92 eq_ctrl_clr_select_4,
93 eq_ctrl_clr_select_5,
94 eq_ctrl_clr_select_6,
95 eq_ctrl_clr_select_7,
96 eq_ctrl_clr_select_8,
97 eq_ctrl_clr_select_9,
98 eq_ctrl_clr_select_10,
99 eq_ctrl_clr_select_11,
100 eq_ctrl_clr_select_12,
101 eq_ctrl_clr_select_13,
102 eq_ctrl_clr_select_14,
103 eq_ctrl_clr_select_15,
104 eq_ctrl_clr_select_16,
105 eq_ctrl_clr_select_17,
106 eq_ctrl_clr_select_18,
107 eq_ctrl_clr_select_19,
108 eq_ctrl_clr_select_20,
109 eq_ctrl_clr_select_21,
110 eq_ctrl_clr_select_22,
111 eq_ctrl_clr_select_23,
112 eq_ctrl_clr_select_24,
113 eq_ctrl_clr_select_25,
114 eq_ctrl_clr_select_26,
115 eq_ctrl_clr_select_27,
116 eq_ctrl_clr_select_28,
117 eq_ctrl_clr_select_29,
118 eq_ctrl_clr_select_30,
119 eq_ctrl_clr_select_31,
120 eq_ctrl_clr_select_32,
121 eq_ctrl_clr_select_33,
122 eq_ctrl_clr_select_34,
123 eq_ctrl_clr_select_35,
124 eq_state_select_0,
125 eq_state_select_1,
126 eq_state_select_2,
127 eq_state_select_3,
128 eq_state_select_4,
129 eq_state_select_5,
130 eq_state_select_6,
131 eq_state_select_7,
132 eq_state_select_8,
133 eq_state_select_9,
134 eq_state_select_10,
135 eq_state_select_11,
136 eq_state_select_12,
137 eq_state_select_13,
138 eq_state_select_14,
139 eq_state_select_15,
140 eq_state_select_16,
141 eq_state_select_17,
142 eq_state_select_18,
143 eq_state_select_19,
144 eq_state_select_20,
145 eq_state_select_21,
146 eq_state_select_22,
147 eq_state_select_23,
148 eq_state_select_24,
149 eq_state_select_25,
150 eq_state_select_26,
151 eq_state_select_27,
152 eq_state_select_28,
153 eq_state_select_29,
154 eq_state_select_30,
155 eq_state_select_31,
156 eq_state_select_32,
157 eq_state_select_33,
158 eq_state_select_34,
159 eq_state_select_35,
160 eq_tail_select_pulse_0,
161 eq_tail_select_pulse_1,
162 eq_tail_select_pulse_2,
163 eq_tail_select_pulse_3,
164 eq_tail_select_pulse_4,
165 eq_tail_select_pulse_5,
166 eq_tail_select_pulse_6,
167 eq_tail_select_pulse_7,
168 eq_tail_select_pulse_8,
169 eq_tail_select_pulse_9,
170 eq_tail_select_pulse_10,
171 eq_tail_select_pulse_11,
172 eq_tail_select_pulse_12,
173 eq_tail_select_pulse_13,
174 eq_tail_select_pulse_14,
175 eq_tail_select_pulse_15,
176 eq_tail_select_pulse_16,
177 eq_tail_select_pulse_17,
178 eq_tail_select_pulse_18,
179 eq_tail_select_pulse_19,
180 eq_tail_select_pulse_20,
181 eq_tail_select_pulse_21,
182 eq_tail_select_pulse_22,
183 eq_tail_select_pulse_23,
184 eq_tail_select_pulse_24,
185 eq_tail_select_pulse_25,
186 eq_tail_select_pulse_26,
187 eq_tail_select_pulse_27,
188 eq_tail_select_pulse_28,
189 eq_tail_select_pulse_29,
190 eq_tail_select_pulse_30,
191 eq_tail_select_pulse_31,
192 eq_tail_select_pulse_32,
193 eq_tail_select_pulse_33,
194 eq_tail_select_pulse_34,
195 eq_tail_select_pulse_35,
196 eq_head_select_pulse_0,
197 eq_head_select_pulse_1,
198 eq_head_select_pulse_2,
199 eq_head_select_pulse_3,
200 eq_head_select_pulse_4,
201 eq_head_select_pulse_5,
202 eq_head_select_pulse_6,
203 eq_head_select_pulse_7,
204 eq_head_select_pulse_8,
205 eq_head_select_pulse_9,
206 eq_head_select_pulse_10,
207 eq_head_select_pulse_11,
208 eq_head_select_pulse_12,
209 eq_head_select_pulse_13,
210 eq_head_select_pulse_14,
211 eq_head_select_pulse_15,
212 eq_head_select_pulse_16,
213 eq_head_select_pulse_17,
214 eq_head_select_pulse_18,
215 eq_head_select_pulse_19,
216 eq_head_select_pulse_20,
217 eq_head_select_pulse_21,
218 eq_head_select_pulse_22,
219 eq_head_select_pulse_23,
220 eq_head_select_pulse_24,
221 eq_head_select_pulse_25,
222 eq_head_select_pulse_26,
223 eq_head_select_pulse_27,
224 eq_head_select_pulse_28,
225 eq_head_select_pulse_29,
226 eq_head_select_pulse_30,
227 eq_head_select_pulse_31,
228 eq_head_select_pulse_32,
229 eq_head_select_pulse_33,
230 eq_head_select_pulse_34,
231 eq_head_select_pulse_35
232 );
233
234//====================================================================
235// Polarity declarations
236//====================================================================
237input clk; // Clock signal
238input rst_l; // Reset
239input daemon_csrbus_valid; // Daemon_Valid
240input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
241input [1:0] csrbus_src_bus; // Source bus
242input daemon_csrbus_wr; // Read/Write signal
243output daemon_csrbus_wr_out; // Read/Write signal
244input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
245output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
246output daemon_csrbus_mapped; // mapped
247output csrbus_acc_vio; // acc_vio
248input daemon_transaction_in_progress; // daemon_transaction_in_progress
249input instance_id; // Instance ID
250output daemon_csrbus_done; // Operation is done
251output eq_base_address_select_pulse; // select signal
252output eq_ctrl_set_select_0; // select signal
253output eq_ctrl_set_select_1; // select signal
254output eq_ctrl_set_select_2; // select signal
255output eq_ctrl_set_select_3; // select signal
256output eq_ctrl_set_select_4; // select signal
257output eq_ctrl_set_select_5; // select signal
258output eq_ctrl_set_select_6; // select signal
259output eq_ctrl_set_select_7; // select signal
260output eq_ctrl_set_select_8; // select signal
261output eq_ctrl_set_select_9; // select signal
262output eq_ctrl_set_select_10; // select signal
263output eq_ctrl_set_select_11; // select signal
264output eq_ctrl_set_select_12; // select signal
265output eq_ctrl_set_select_13; // select signal
266output eq_ctrl_set_select_14; // select signal
267output eq_ctrl_set_select_15; // select signal
268output eq_ctrl_set_select_16; // select signal
269output eq_ctrl_set_select_17; // select signal
270output eq_ctrl_set_select_18; // select signal
271output eq_ctrl_set_select_19; // select signal
272output eq_ctrl_set_select_20; // select signal
273output eq_ctrl_set_select_21; // select signal
274output eq_ctrl_set_select_22; // select signal
275output eq_ctrl_set_select_23; // select signal
276output eq_ctrl_set_select_24; // select signal
277output eq_ctrl_set_select_25; // select signal
278output eq_ctrl_set_select_26; // select signal
279output eq_ctrl_set_select_27; // select signal
280output eq_ctrl_set_select_28; // select signal
281output eq_ctrl_set_select_29; // select signal
282output eq_ctrl_set_select_30; // select signal
283output eq_ctrl_set_select_31; // select signal
284output eq_ctrl_set_select_32; // select signal
285output eq_ctrl_set_select_33; // select signal
286output eq_ctrl_set_select_34; // select signal
287output eq_ctrl_set_select_35; // select signal
288output eq_ctrl_clr_select_0; // select signal
289output eq_ctrl_clr_select_1; // select signal
290output eq_ctrl_clr_select_2; // select signal
291output eq_ctrl_clr_select_3; // select signal
292output eq_ctrl_clr_select_4; // select signal
293output eq_ctrl_clr_select_5; // select signal
294output eq_ctrl_clr_select_6; // select signal
295output eq_ctrl_clr_select_7; // select signal
296output eq_ctrl_clr_select_8; // select signal
297output eq_ctrl_clr_select_9; // select signal
298output eq_ctrl_clr_select_10; // select signal
299output eq_ctrl_clr_select_11; // select signal
300output eq_ctrl_clr_select_12; // select signal
301output eq_ctrl_clr_select_13; // select signal
302output eq_ctrl_clr_select_14; // select signal
303output eq_ctrl_clr_select_15; // select signal
304output eq_ctrl_clr_select_16; // select signal
305output eq_ctrl_clr_select_17; // select signal
306output eq_ctrl_clr_select_18; // select signal
307output eq_ctrl_clr_select_19; // select signal
308output eq_ctrl_clr_select_20; // select signal
309output eq_ctrl_clr_select_21; // select signal
310output eq_ctrl_clr_select_22; // select signal
311output eq_ctrl_clr_select_23; // select signal
312output eq_ctrl_clr_select_24; // select signal
313output eq_ctrl_clr_select_25; // select signal
314output eq_ctrl_clr_select_26; // select signal
315output eq_ctrl_clr_select_27; // select signal
316output eq_ctrl_clr_select_28; // select signal
317output eq_ctrl_clr_select_29; // select signal
318output eq_ctrl_clr_select_30; // select signal
319output eq_ctrl_clr_select_31; // select signal
320output eq_ctrl_clr_select_32; // select signal
321output eq_ctrl_clr_select_33; // select signal
322output eq_ctrl_clr_select_34; // select signal
323output eq_ctrl_clr_select_35; // select signal
324output eq_state_select_0; // select signal
325output eq_state_select_1; // select signal
326output eq_state_select_2; // select signal
327output eq_state_select_3; // select signal
328output eq_state_select_4; // select signal
329output eq_state_select_5; // select signal
330output eq_state_select_6; // select signal
331output eq_state_select_7; // select signal
332output eq_state_select_8; // select signal
333output eq_state_select_9; // select signal
334output eq_state_select_10; // select signal
335output eq_state_select_11; // select signal
336output eq_state_select_12; // select signal
337output eq_state_select_13; // select signal
338output eq_state_select_14; // select signal
339output eq_state_select_15; // select signal
340output eq_state_select_16; // select signal
341output eq_state_select_17; // select signal
342output eq_state_select_18; // select signal
343output eq_state_select_19; // select signal
344output eq_state_select_20; // select signal
345output eq_state_select_21; // select signal
346output eq_state_select_22; // select signal
347output eq_state_select_23; // select signal
348output eq_state_select_24; // select signal
349output eq_state_select_25; // select signal
350output eq_state_select_26; // select signal
351output eq_state_select_27; // select signal
352output eq_state_select_28; // select signal
353output eq_state_select_29; // select signal
354output eq_state_select_30; // select signal
355output eq_state_select_31; // select signal
356output eq_state_select_32; // select signal
357output eq_state_select_33; // select signal
358output eq_state_select_34; // select signal
359output eq_state_select_35; // select signal
360output eq_tail_select_pulse_0; // select signal
361output eq_tail_select_pulse_1; // select signal
362output eq_tail_select_pulse_2; // select signal
363output eq_tail_select_pulse_3; // select signal
364output eq_tail_select_pulse_4; // select signal
365output eq_tail_select_pulse_5; // select signal
366output eq_tail_select_pulse_6; // select signal
367output eq_tail_select_pulse_7; // select signal
368output eq_tail_select_pulse_8; // select signal
369output eq_tail_select_pulse_9; // select signal
370output eq_tail_select_pulse_10; // select signal
371output eq_tail_select_pulse_11; // select signal
372output eq_tail_select_pulse_12; // select signal
373output eq_tail_select_pulse_13; // select signal
374output eq_tail_select_pulse_14; // select signal
375output eq_tail_select_pulse_15; // select signal
376output eq_tail_select_pulse_16; // select signal
377output eq_tail_select_pulse_17; // select signal
378output eq_tail_select_pulse_18; // select signal
379output eq_tail_select_pulse_19; // select signal
380output eq_tail_select_pulse_20; // select signal
381output eq_tail_select_pulse_21; // select signal
382output eq_tail_select_pulse_22; // select signal
383output eq_tail_select_pulse_23; // select signal
384output eq_tail_select_pulse_24; // select signal
385output eq_tail_select_pulse_25; // select signal
386output eq_tail_select_pulse_26; // select signal
387output eq_tail_select_pulse_27; // select signal
388output eq_tail_select_pulse_28; // select signal
389output eq_tail_select_pulse_29; // select signal
390output eq_tail_select_pulse_30; // select signal
391output eq_tail_select_pulse_31; // select signal
392output eq_tail_select_pulse_32; // select signal
393output eq_tail_select_pulse_33; // select signal
394output eq_tail_select_pulse_34; // select signal
395output eq_tail_select_pulse_35; // select signal
396output eq_head_select_pulse_0; // select signal
397output eq_head_select_pulse_1; // select signal
398output eq_head_select_pulse_2; // select signal
399output eq_head_select_pulse_3; // select signal
400output eq_head_select_pulse_4; // select signal
401output eq_head_select_pulse_5; // select signal
402output eq_head_select_pulse_6; // select signal
403output eq_head_select_pulse_7; // select signal
404output eq_head_select_pulse_8; // select signal
405output eq_head_select_pulse_9; // select signal
406output eq_head_select_pulse_10; // select signal
407output eq_head_select_pulse_11; // select signal
408output eq_head_select_pulse_12; // select signal
409output eq_head_select_pulse_13; // select signal
410output eq_head_select_pulse_14; // select signal
411output eq_head_select_pulse_15; // select signal
412output eq_head_select_pulse_16; // select signal
413output eq_head_select_pulse_17; // select signal
414output eq_head_select_pulse_18; // select signal
415output eq_head_select_pulse_19; // select signal
416output eq_head_select_pulse_20; // select signal
417output eq_head_select_pulse_21; // select signal
418output eq_head_select_pulse_22; // select signal
419output eq_head_select_pulse_23; // select signal
420output eq_head_select_pulse_24; // select signal
421output eq_head_select_pulse_25; // select signal
422output eq_head_select_pulse_26; // select signal
423output eq_head_select_pulse_27; // select signal
424output eq_head_select_pulse_28; // select signal
425output eq_head_select_pulse_29; // select signal
426output eq_head_select_pulse_30; // select signal
427output eq_head_select_pulse_31; // select signal
428output eq_head_select_pulse_32; // select signal
429output eq_head_select_pulse_33; // select signal
430output eq_head_select_pulse_34; // select signal
431output eq_head_select_pulse_35; // select signal
432
433//====================================================================
434// Type declarations
435//====================================================================
436wire clk; // Clock signal
437wire rst_l; // Reset
438wire daemon_csrbus_valid; // Daemon_Valid
439wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
440wire [1:0] csrbus_src_bus; // Source bus
441wire daemon_csrbus_wr; // Read/Write signal
442reg daemon_csrbus_wr_out; // Read/Write signal
443wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
444reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
445wire daemon_csrbus_mapped; // mapped
446wire csrbus_acc_vio; // acc_vio
447wire daemon_transaction_in_progress; // daemon_transaction_in_progress
448wire instance_id; // Instance ID
449wire daemon_csrbus_done; // Operation is done
450reg eq_base_address_select_pulse; // select signal
451reg eq_ctrl_set_select_0; // select signal
452reg eq_ctrl_set_select_1; // select signal
453reg eq_ctrl_set_select_2; // select signal
454reg eq_ctrl_set_select_3; // select signal
455reg eq_ctrl_set_select_4; // select signal
456reg eq_ctrl_set_select_5; // select signal
457reg eq_ctrl_set_select_6; // select signal
458reg eq_ctrl_set_select_7; // select signal
459reg eq_ctrl_set_select_8; // select signal
460reg eq_ctrl_set_select_9; // select signal
461reg eq_ctrl_set_select_10; // select signal
462reg eq_ctrl_set_select_11; // select signal
463reg eq_ctrl_set_select_12; // select signal
464reg eq_ctrl_set_select_13; // select signal
465reg eq_ctrl_set_select_14; // select signal
466reg eq_ctrl_set_select_15; // select signal
467reg eq_ctrl_set_select_16; // select signal
468reg eq_ctrl_set_select_17; // select signal
469reg eq_ctrl_set_select_18; // select signal
470reg eq_ctrl_set_select_19; // select signal
471reg eq_ctrl_set_select_20; // select signal
472reg eq_ctrl_set_select_21; // select signal
473reg eq_ctrl_set_select_22; // select signal
474reg eq_ctrl_set_select_23; // select signal
475reg eq_ctrl_set_select_24; // select signal
476reg eq_ctrl_set_select_25; // select signal
477reg eq_ctrl_set_select_26; // select signal
478reg eq_ctrl_set_select_27; // select signal
479reg eq_ctrl_set_select_28; // select signal
480reg eq_ctrl_set_select_29; // select signal
481reg eq_ctrl_set_select_30; // select signal
482reg eq_ctrl_set_select_31; // select signal
483reg eq_ctrl_set_select_32; // select signal
484reg eq_ctrl_set_select_33; // select signal
485reg eq_ctrl_set_select_34; // select signal
486reg eq_ctrl_set_select_35; // select signal
487reg eq_ctrl_clr_select_0; // select signal
488reg eq_ctrl_clr_select_1; // select signal
489reg eq_ctrl_clr_select_2; // select signal
490reg eq_ctrl_clr_select_3; // select signal
491reg eq_ctrl_clr_select_4; // select signal
492reg eq_ctrl_clr_select_5; // select signal
493reg eq_ctrl_clr_select_6; // select signal
494reg eq_ctrl_clr_select_7; // select signal
495reg eq_ctrl_clr_select_8; // select signal
496reg eq_ctrl_clr_select_9; // select signal
497reg eq_ctrl_clr_select_10; // select signal
498reg eq_ctrl_clr_select_11; // select signal
499reg eq_ctrl_clr_select_12; // select signal
500reg eq_ctrl_clr_select_13; // select signal
501reg eq_ctrl_clr_select_14; // select signal
502reg eq_ctrl_clr_select_15; // select signal
503reg eq_ctrl_clr_select_16; // select signal
504reg eq_ctrl_clr_select_17; // select signal
505reg eq_ctrl_clr_select_18; // select signal
506reg eq_ctrl_clr_select_19; // select signal
507reg eq_ctrl_clr_select_20; // select signal
508reg eq_ctrl_clr_select_21; // select signal
509reg eq_ctrl_clr_select_22; // select signal
510reg eq_ctrl_clr_select_23; // select signal
511reg eq_ctrl_clr_select_24; // select signal
512reg eq_ctrl_clr_select_25; // select signal
513reg eq_ctrl_clr_select_26; // select signal
514reg eq_ctrl_clr_select_27; // select signal
515reg eq_ctrl_clr_select_28; // select signal
516reg eq_ctrl_clr_select_29; // select signal
517reg eq_ctrl_clr_select_30; // select signal
518reg eq_ctrl_clr_select_31; // select signal
519reg eq_ctrl_clr_select_32; // select signal
520reg eq_ctrl_clr_select_33; // select signal
521reg eq_ctrl_clr_select_34; // select signal
522reg eq_ctrl_clr_select_35; // select signal
523reg eq_state_select_0; // select signal
524reg eq_state_select_1; // select signal
525reg eq_state_select_2; // select signal
526reg eq_state_select_3; // select signal
527reg eq_state_select_4; // select signal
528reg eq_state_select_5; // select signal
529reg eq_state_select_6; // select signal
530reg eq_state_select_7; // select signal
531reg eq_state_select_8; // select signal
532reg eq_state_select_9; // select signal
533reg eq_state_select_10; // select signal
534reg eq_state_select_11; // select signal
535reg eq_state_select_12; // select signal
536reg eq_state_select_13; // select signal
537reg eq_state_select_14; // select signal
538reg eq_state_select_15; // select signal
539reg eq_state_select_16; // select signal
540reg eq_state_select_17; // select signal
541reg eq_state_select_18; // select signal
542reg eq_state_select_19; // select signal
543reg eq_state_select_20; // select signal
544reg eq_state_select_21; // select signal
545reg eq_state_select_22; // select signal
546reg eq_state_select_23; // select signal
547reg eq_state_select_24; // select signal
548reg eq_state_select_25; // select signal
549reg eq_state_select_26; // select signal
550reg eq_state_select_27; // select signal
551reg eq_state_select_28; // select signal
552reg eq_state_select_29; // select signal
553reg eq_state_select_30; // select signal
554reg eq_state_select_31; // select signal
555reg eq_state_select_32; // select signal
556reg eq_state_select_33; // select signal
557reg eq_state_select_34; // select signal
558reg eq_state_select_35; // select signal
559reg eq_tail_select_pulse_0; // select signal
560reg eq_tail_select_pulse_1; // select signal
561reg eq_tail_select_pulse_2; // select signal
562reg eq_tail_select_pulse_3; // select signal
563reg eq_tail_select_pulse_4; // select signal
564reg eq_tail_select_pulse_5; // select signal
565reg eq_tail_select_pulse_6; // select signal
566reg eq_tail_select_pulse_7; // select signal
567reg eq_tail_select_pulse_8; // select signal
568reg eq_tail_select_pulse_9; // select signal
569reg eq_tail_select_pulse_10; // select signal
570reg eq_tail_select_pulse_11; // select signal
571reg eq_tail_select_pulse_12; // select signal
572reg eq_tail_select_pulse_13; // select signal
573reg eq_tail_select_pulse_14; // select signal
574reg eq_tail_select_pulse_15; // select signal
575reg eq_tail_select_pulse_16; // select signal
576reg eq_tail_select_pulse_17; // select signal
577reg eq_tail_select_pulse_18; // select signal
578reg eq_tail_select_pulse_19; // select signal
579reg eq_tail_select_pulse_20; // select signal
580reg eq_tail_select_pulse_21; // select signal
581reg eq_tail_select_pulse_22; // select signal
582reg eq_tail_select_pulse_23; // select signal
583reg eq_tail_select_pulse_24; // select signal
584reg eq_tail_select_pulse_25; // select signal
585reg eq_tail_select_pulse_26; // select signal
586reg eq_tail_select_pulse_27; // select signal
587reg eq_tail_select_pulse_28; // select signal
588reg eq_tail_select_pulse_29; // select signal
589reg eq_tail_select_pulse_30; // select signal
590reg eq_tail_select_pulse_31; // select signal
591reg eq_tail_select_pulse_32; // select signal
592reg eq_tail_select_pulse_33; // select signal
593reg eq_tail_select_pulse_34; // select signal
594reg eq_tail_select_pulse_35; // select signal
595reg eq_head_select_pulse_0; // select signal
596reg eq_head_select_pulse_1; // select signal
597reg eq_head_select_pulse_2; // select signal
598reg eq_head_select_pulse_3; // select signal
599reg eq_head_select_pulse_4; // select signal
600reg eq_head_select_pulse_5; // select signal
601reg eq_head_select_pulse_6; // select signal
602reg eq_head_select_pulse_7; // select signal
603reg eq_head_select_pulse_8; // select signal
604reg eq_head_select_pulse_9; // select signal
605reg eq_head_select_pulse_10; // select signal
606reg eq_head_select_pulse_11; // select signal
607reg eq_head_select_pulse_12; // select signal
608reg eq_head_select_pulse_13; // select signal
609reg eq_head_select_pulse_14; // select signal
610reg eq_head_select_pulse_15; // select signal
611reg eq_head_select_pulse_16; // select signal
612reg eq_head_select_pulse_17; // select signal
613reg eq_head_select_pulse_18; // select signal
614reg eq_head_select_pulse_19; // select signal
615reg eq_head_select_pulse_20; // select signal
616reg eq_head_select_pulse_21; // select signal
617reg eq_head_select_pulse_22; // select signal
618reg eq_head_select_pulse_23; // select signal
619reg eq_head_select_pulse_24; // select signal
620reg eq_head_select_pulse_25; // select signal
621reg eq_head_select_pulse_26; // select signal
622reg eq_head_select_pulse_27; // select signal
623reg eq_head_select_pulse_28; // select signal
624reg eq_head_select_pulse_29; // select signal
625reg eq_head_select_pulse_30; // select signal
626reg eq_head_select_pulse_31; // select signal
627reg eq_head_select_pulse_32; // select signal
628reg eq_head_select_pulse_33; // select signal
629reg eq_head_select_pulse_34; // select signal
630reg eq_head_select_pulse_35; // select signal
631
632
633//====================================================================
634// Clocked valid
635//====================================================================
636reg clocked_valid;
637reg clocked_valid_pulse;
638always @(posedge clk)
639 begin
640 if(~rst_l)
641 begin
642 clocked_valid <= 1'b0;
643 clocked_valid_pulse <= 1'b0;
644 end
645 else
646 begin
647 clocked_valid <= daemon_csrbus_valid;
648 clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid;
649 end
650 end
651
652//====================================================================
653// Address Decode
654//====================================================================
655reg eq_base_address_addr_decoded;
656reg eq_ctrl_set_addr_decoded;
657reg eq_ctrl_clr_addr_decoded;
658reg eq_state_addr_decoded;
659reg eq_tail_addr_decoded;
660reg eq_head_addr_decoded;
661
662always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id)
663 begin
664 if (~daemon_csrbus_valid)
665 begin
666 eq_base_address_addr_decoded = 1'b0;
667 eq_ctrl_set_addr_decoded = 1'b0;
668 eq_ctrl_clr_addr_decoded = 1'b0;
669 eq_state_addr_decoded = 1'b0;
670 eq_tail_addr_decoded = 1'b0;
671 eq_head_addr_decoded = 1'b0;
672 end
673 else
674 case (instance_id)
675
676 `FIRE_DLC_IMU_EQS_INSTANCE_ID_VALUE_A:
677 begin
678 eq_base_address_addr_decoded =
679 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_HW_ADDR;
680 eq_ctrl_set_addr_decoded =
681 {6'b0,daemon_csrbus_addr[26:6]} ==
682 `FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_HW_ADDR >>
683 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH;
684 eq_ctrl_clr_addr_decoded =
685 {6'b0,daemon_csrbus_addr[26:6]} ==
686 `FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_HW_ADDR >>
687 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH;
688 eq_state_addr_decoded =
689 {6'b0,daemon_csrbus_addr[26:6]} ==
690 `FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_HW_ADDR >>
691 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH;
692 eq_tail_addr_decoded =
693 {6'b0,daemon_csrbus_addr[26:6]} ==
694 `FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_HW_ADDR >>
695 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH;
696 eq_head_addr_decoded =
697 {6'b0,daemon_csrbus_addr[26:6]} ==
698 `FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_HW_ADDR >>
699 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH;
700 end
701
702 `FIRE_DLC_IMU_EQS_INSTANCE_ID_VALUE_B:
703 begin
704 eq_base_address_addr_decoded =
705 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_EQS_CSR_B_EQ_BASE_ADDRESS_HW_ADDR;
706 eq_ctrl_set_addr_decoded =
707 {6'b0,daemon_csrbus_addr[26:6]} ==
708 `FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_SET_HW_ADDR >>
709 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH;
710 eq_ctrl_clr_addr_decoded =
711 {6'b0,daemon_csrbus_addr[26:6]} ==
712 `FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_CLR_HW_ADDR >>
713 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH;
714 eq_state_addr_decoded =
715 {6'b0,daemon_csrbus_addr[26:6]} ==
716 `FIRE_DLC_IMU_EQS_CSR_B_EQ_STATE_HW_ADDR >>
717 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH;
718 eq_tail_addr_decoded =
719 {6'b0,daemon_csrbus_addr[26:6]} ==
720 `FIRE_DLC_IMU_EQS_CSR_B_EQ_TAIL_HW_ADDR >>
721 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH;
722 eq_head_addr_decoded =
723 {6'b0,daemon_csrbus_addr[26:6]} ==
724 `FIRE_DLC_IMU_EQS_CSR_B_EQ_HEAD_HW_ADDR >>
725 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH;
726 end
727
728 default:
729 begin
730 eq_base_address_addr_decoded = 1'b0;
731 eq_ctrl_set_addr_decoded = 1'b0;
732 eq_ctrl_clr_addr_decoded = 1'b0;
733 eq_state_addr_decoded = 1'b0;
734 eq_tail_addr_decoded = 1'b0;
735 eq_head_addr_decoded = 1'b0;
736// vlint flag_system_call off
737 // synopsys translate_off
738 if(daemon_csrbus_valid)
739 begin // axis tbcall_region
740`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_imu_eqs_csr is bad"); `endif
741 end // end of tbcall_region
742 // synopsys translate_on
743// vlint flag_system_call on
744 end
745 endcase
746 end
747
748//====================================================================
749// Register violations
750//====================================================================
751//----- reg_acc_vio: eq_base_address
752reg eq_base_address_acc_vio;
753always @(csrbus_src_bus or daemon_csrbus_wr or
754 eq_base_address_addr_decoded or
755 daemon_transaction_in_progress)
756 begin
757 if (daemon_transaction_in_progress | ~eq_base_address_addr_decoded)
758 eq_base_address_acc_vio = 1'b0;
759 else
760 case ({csrbus_src_bus, daemon_csrbus_wr})
761 // reads
762 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
763 eq_base_address_acc_vio = 1'b0;
764 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
765 eq_base_address_acc_vio = 1'b0;
766 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
767 eq_base_address_acc_vio = 1'b0;
768 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
769 eq_base_address_acc_vio = 1'b0;
770 // writes
771 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
772 eq_base_address_acc_vio = 1'b0;
773 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
774 eq_base_address_acc_vio = 1'b0;
775 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
776 eq_base_address_acc_vio = 1'b0;
777 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
778 eq_base_address_acc_vio = 1'b0;
779
780 default:
781 begin
782 eq_base_address_acc_vio = 1'b0;
783 begin // axis tbcall_region
784 // vlint flag_system_call off
785 // synopsys translate_off
786`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_eqs_csr_a_eq_base_address"); `endif
787 // synopsys translate_on
788 // vlint flag_system_call on
789 end // end of tbcall_region
790 end
791 endcase
792 end
793//----- reg_acc_vio: eq_ctrl_set
794reg eq_ctrl_set_acc_vio;
795always @(csrbus_src_bus or daemon_csrbus_wr or
796 eq_ctrl_set_addr_decoded or
797 daemon_transaction_in_progress)
798 begin
799 if (daemon_transaction_in_progress | ~eq_ctrl_set_addr_decoded)
800 eq_ctrl_set_acc_vio = 1'b0;
801 else
802 case ({csrbus_src_bus, daemon_csrbus_wr})
803 // reads
804 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
805 eq_ctrl_set_acc_vio = 1'b0;
806 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
807 eq_ctrl_set_acc_vio = 1'b0;
808 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
809 eq_ctrl_set_acc_vio = 1'b0;
810 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
811 eq_ctrl_set_acc_vio = 1'b0;
812 // writes
813 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
814 eq_ctrl_set_acc_vio = 1'b0;
815 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
816 eq_ctrl_set_acc_vio = 1'b0;
817 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
818 eq_ctrl_set_acc_vio = 1'b0;
819 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
820 eq_ctrl_set_acc_vio = 1'b0;
821
822 default:
823 begin
824 eq_ctrl_set_acc_vio = 1'b0;
825 begin // axis tbcall_region
826 // vlint flag_system_call off
827 // synopsys translate_off
828`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_eqs_csr_a_eq_ctrl_set"); `endif
829 // synopsys translate_on
830 // vlint flag_system_call on
831 end // end of tbcall_region
832 end
833 endcase
834 end
835//----- reg_acc_vio: eq_ctrl_clr
836reg eq_ctrl_clr_acc_vio;
837always @(csrbus_src_bus or daemon_csrbus_wr or
838 eq_ctrl_clr_addr_decoded or
839 daemon_transaction_in_progress)
840 begin
841 if (daemon_transaction_in_progress | ~eq_ctrl_clr_addr_decoded)
842 eq_ctrl_clr_acc_vio = 1'b0;
843 else
844 case ({csrbus_src_bus, daemon_csrbus_wr})
845 // reads
846 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
847 eq_ctrl_clr_acc_vio = 1'b0;
848 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
849 eq_ctrl_clr_acc_vio = 1'b0;
850 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
851 eq_ctrl_clr_acc_vio = 1'b0;
852 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
853 eq_ctrl_clr_acc_vio = 1'b0;
854 // writes
855 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
856 eq_ctrl_clr_acc_vio = 1'b0;
857 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
858 eq_ctrl_clr_acc_vio = 1'b0;
859 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
860 eq_ctrl_clr_acc_vio = 1'b0;
861 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
862 eq_ctrl_clr_acc_vio = 1'b0;
863
864 default:
865 begin
866 eq_ctrl_clr_acc_vio = 1'b0;
867 begin // axis tbcall_region
868 // vlint flag_system_call off
869 // synopsys translate_off
870`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_eqs_csr_a_eq_ctrl_clr"); `endif
871 // synopsys translate_on
872 // vlint flag_system_call on
873 end // end of tbcall_region
874 end
875 endcase
876 end
877//----- reg_acc_vio: eq_state
878reg eq_state_acc_vio;
879always @(csrbus_src_bus or daemon_csrbus_wr or
880 eq_state_addr_decoded or
881 daemon_transaction_in_progress)
882 begin
883 if (daemon_transaction_in_progress | ~eq_state_addr_decoded)
884 eq_state_acc_vio = 1'b0;
885 else
886 case ({csrbus_src_bus, daemon_csrbus_wr})
887 // reads
888 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
889 eq_state_acc_vio = 1'b0;
890 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
891 eq_state_acc_vio = 1'b0;
892 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
893 eq_state_acc_vio = 1'b0;
894 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
895 eq_state_acc_vio = 1'b0;
896 // writes
897 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
898 eq_state_acc_vio = 1'b0;
899 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
900 eq_state_acc_vio = 1'b0;
901 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
902 eq_state_acc_vio = 1'b0;
903 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
904 eq_state_acc_vio = 1'b0;
905
906 default:
907 begin
908 eq_state_acc_vio = 1'b0;
909 begin // axis tbcall_region
910 // vlint flag_system_call off
911 // synopsys translate_off
912`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_eqs_csr_a_eq_state"); `endif
913 // synopsys translate_on
914 // vlint flag_system_call on
915 end // end of tbcall_region
916 end
917 endcase
918 end
919//----- reg_acc_vio: eq_tail
920reg eq_tail_acc_vio;
921always @(csrbus_src_bus or daemon_csrbus_wr or
922 eq_tail_addr_decoded or
923 daemon_transaction_in_progress)
924 begin
925 if (daemon_transaction_in_progress | ~eq_tail_addr_decoded)
926 eq_tail_acc_vio = 1'b0;
927 else
928 case ({csrbus_src_bus, daemon_csrbus_wr})
929 // reads
930 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
931 eq_tail_acc_vio = 1'b0;
932 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
933 eq_tail_acc_vio = 1'b0;
934 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
935 eq_tail_acc_vio = 1'b0;
936 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
937 eq_tail_acc_vio = 1'b0;
938 // writes
939 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
940 eq_tail_acc_vio = 1'b0;
941 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
942 eq_tail_acc_vio = 1'b0;
943 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
944 eq_tail_acc_vio = 1'b0;
945 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
946 eq_tail_acc_vio = 1'b0;
947
948 default:
949 begin
950 eq_tail_acc_vio = 1'b0;
951 begin // axis tbcall_region
952 // vlint flag_system_call off
953 // synopsys translate_off
954`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_eqs_csr_a_eq_tail"); `endif
955 // synopsys translate_on
956 // vlint flag_system_call on
957 end // end of tbcall_region
958 end
959 endcase
960 end
961//----- reg_acc_vio: eq_head
962reg eq_head_acc_vio;
963always @(csrbus_src_bus or daemon_csrbus_wr or
964 eq_head_addr_decoded or
965 daemon_transaction_in_progress)
966 begin
967 if (daemon_transaction_in_progress | ~eq_head_addr_decoded)
968 eq_head_acc_vio = 1'b0;
969 else
970 case ({csrbus_src_bus, daemon_csrbus_wr})
971 // reads
972 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
973 eq_head_acc_vio = 1'b0;
974 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
975 eq_head_acc_vio = 1'b0;
976 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
977 eq_head_acc_vio = 1'b0;
978 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
979 eq_head_acc_vio = 1'b0;
980 // writes
981 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
982 eq_head_acc_vio = 1'b0;
983 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
984 eq_head_acc_vio = 1'b0;
985 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
986 eq_head_acc_vio = 1'b0;
987 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
988 eq_head_acc_vio = 1'b0;
989
990 default:
991 begin
992 eq_head_acc_vio = 1'b0;
993 begin // axis tbcall_region
994 // vlint flag_system_call off
995 // synopsys translate_off
996`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_eqs_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_eqs_csr_a_eq_head"); `endif
997 // synopsys translate_on
998 // vlint flag_system_call on
999 end // end of tbcall_region
1000 end
1001 endcase
1002 end
1003
1004//====================================================================
1005// Status: daemon_csrbus_mapped / csrbus_acc_vio
1006//====================================================================
1007//----- OUTPUT: daemon_csrbus_mapped
1008assign daemon_csrbus_mapped = clocked_valid_pulse &
1009 (
1010 eq_base_address_addr_decoded |
1011 eq_ctrl_set_addr_decoded |
1012 eq_ctrl_clr_addr_decoded |
1013 eq_state_addr_decoded |
1014 eq_tail_addr_decoded |
1015 eq_head_addr_decoded
1016 );
1017
1018
1019// daemon_csrbus_mapped gets asserted after fixed number of cycles
1020// after daemon_csrbus_valid become high
1021/* 0in assert_together -name mapped_after_valid
1022 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1))
1023 -follower $0in_rising_edge(daemon_csrbus_mapped)
1024 -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid")
1025 -module dmu_imu_eqs_addr_decode
1026 -clock clk
1027 -active $0in_rising_edge(daemon_csrbus_mapped)
1028*/
1029
1030// daemon_csrbus_mapped is a pulse
1031/* 0in assert_timer -name daemon_csrbus_mapped_pulse
1032 -var daemon_csrbus_mapped -max 1
1033 -message "daemon_csrbus_mapped pulse length is not 1"
1034 -module dmu_imu_eqs_addr_decode
1035 -clock clk
1036*/
1037//----- OUTPUT: csrbus_acc_vio
1038assign csrbus_acc_vio = clocked_valid_pulse &
1039 eq_base_address_acc_vio |
1040 eq_ctrl_set_acc_vio |
1041 eq_ctrl_clr_acc_vio |
1042 eq_state_acc_vio |
1043 eq_tail_acc_vio |
1044 eq_head_acc_vio;
1045
1046//====================================================================
1047// Select
1048//====================================================================
1049always @(posedge clk)
1050 begin
1051 if(~rst_l)
1052 begin
1053 eq_base_address_select_pulse <= 1'b0;
1054 eq_ctrl_set_select_0 <= 1'b0;
1055 eq_ctrl_set_select_1 <= 1'b0;
1056 eq_ctrl_set_select_2 <= 1'b0;
1057 eq_ctrl_set_select_3 <= 1'b0;
1058 eq_ctrl_set_select_4 <= 1'b0;
1059 eq_ctrl_set_select_5 <= 1'b0;
1060 eq_ctrl_set_select_6 <= 1'b0;
1061 eq_ctrl_set_select_7 <= 1'b0;
1062 eq_ctrl_set_select_8 <= 1'b0;
1063 eq_ctrl_set_select_9 <= 1'b0;
1064 eq_ctrl_set_select_10 <= 1'b0;
1065 eq_ctrl_set_select_11 <= 1'b0;
1066 eq_ctrl_set_select_12 <= 1'b0;
1067 eq_ctrl_set_select_13 <= 1'b0;
1068 eq_ctrl_set_select_14 <= 1'b0;
1069 eq_ctrl_set_select_15 <= 1'b0;
1070 eq_ctrl_set_select_16 <= 1'b0;
1071 eq_ctrl_set_select_17 <= 1'b0;
1072 eq_ctrl_set_select_18 <= 1'b0;
1073 eq_ctrl_set_select_19 <= 1'b0;
1074 eq_ctrl_set_select_20 <= 1'b0;
1075 eq_ctrl_set_select_21 <= 1'b0;
1076 eq_ctrl_set_select_22 <= 1'b0;
1077 eq_ctrl_set_select_23 <= 1'b0;
1078 eq_ctrl_set_select_24 <= 1'b0;
1079 eq_ctrl_set_select_25 <= 1'b0;
1080 eq_ctrl_set_select_26 <= 1'b0;
1081 eq_ctrl_set_select_27 <= 1'b0;
1082 eq_ctrl_set_select_28 <= 1'b0;
1083 eq_ctrl_set_select_29 <= 1'b0;
1084 eq_ctrl_set_select_30 <= 1'b0;
1085 eq_ctrl_set_select_31 <= 1'b0;
1086 eq_ctrl_set_select_32 <= 1'b0;
1087 eq_ctrl_set_select_33 <= 1'b0;
1088 eq_ctrl_set_select_34 <= 1'b0;
1089 eq_ctrl_set_select_35 <= 1'b0;
1090 eq_ctrl_clr_select_0 <= 1'b0;
1091 eq_ctrl_clr_select_1 <= 1'b0;
1092 eq_ctrl_clr_select_2 <= 1'b0;
1093 eq_ctrl_clr_select_3 <= 1'b0;
1094 eq_ctrl_clr_select_4 <= 1'b0;
1095 eq_ctrl_clr_select_5 <= 1'b0;
1096 eq_ctrl_clr_select_6 <= 1'b0;
1097 eq_ctrl_clr_select_7 <= 1'b0;
1098 eq_ctrl_clr_select_8 <= 1'b0;
1099 eq_ctrl_clr_select_9 <= 1'b0;
1100 eq_ctrl_clr_select_10 <= 1'b0;
1101 eq_ctrl_clr_select_11 <= 1'b0;
1102 eq_ctrl_clr_select_12 <= 1'b0;
1103 eq_ctrl_clr_select_13 <= 1'b0;
1104 eq_ctrl_clr_select_14 <= 1'b0;
1105 eq_ctrl_clr_select_15 <= 1'b0;
1106 eq_ctrl_clr_select_16 <= 1'b0;
1107 eq_ctrl_clr_select_17 <= 1'b0;
1108 eq_ctrl_clr_select_18 <= 1'b0;
1109 eq_ctrl_clr_select_19 <= 1'b0;
1110 eq_ctrl_clr_select_20 <= 1'b0;
1111 eq_ctrl_clr_select_21 <= 1'b0;
1112 eq_ctrl_clr_select_22 <= 1'b0;
1113 eq_ctrl_clr_select_23 <= 1'b0;
1114 eq_ctrl_clr_select_24 <= 1'b0;
1115 eq_ctrl_clr_select_25 <= 1'b0;
1116 eq_ctrl_clr_select_26 <= 1'b0;
1117 eq_ctrl_clr_select_27 <= 1'b0;
1118 eq_ctrl_clr_select_28 <= 1'b0;
1119 eq_ctrl_clr_select_29 <= 1'b0;
1120 eq_ctrl_clr_select_30 <= 1'b0;
1121 eq_ctrl_clr_select_31 <= 1'b0;
1122 eq_ctrl_clr_select_32 <= 1'b0;
1123 eq_ctrl_clr_select_33 <= 1'b0;
1124 eq_ctrl_clr_select_34 <= 1'b0;
1125 eq_ctrl_clr_select_35 <= 1'b0;
1126 eq_state_select_0 <= 1'b0;
1127 eq_state_select_1 <= 1'b0;
1128 eq_state_select_2 <= 1'b0;
1129 eq_state_select_3 <= 1'b0;
1130 eq_state_select_4 <= 1'b0;
1131 eq_state_select_5 <= 1'b0;
1132 eq_state_select_6 <= 1'b0;
1133 eq_state_select_7 <= 1'b0;
1134 eq_state_select_8 <= 1'b0;
1135 eq_state_select_9 <= 1'b0;
1136 eq_state_select_10 <= 1'b0;
1137 eq_state_select_11 <= 1'b0;
1138 eq_state_select_12 <= 1'b0;
1139 eq_state_select_13 <= 1'b0;
1140 eq_state_select_14 <= 1'b0;
1141 eq_state_select_15 <= 1'b0;
1142 eq_state_select_16 <= 1'b0;
1143 eq_state_select_17 <= 1'b0;
1144 eq_state_select_18 <= 1'b0;
1145 eq_state_select_19 <= 1'b0;
1146 eq_state_select_20 <= 1'b0;
1147 eq_state_select_21 <= 1'b0;
1148 eq_state_select_22 <= 1'b0;
1149 eq_state_select_23 <= 1'b0;
1150 eq_state_select_24 <= 1'b0;
1151 eq_state_select_25 <= 1'b0;
1152 eq_state_select_26 <= 1'b0;
1153 eq_state_select_27 <= 1'b0;
1154 eq_state_select_28 <= 1'b0;
1155 eq_state_select_29 <= 1'b0;
1156 eq_state_select_30 <= 1'b0;
1157 eq_state_select_31 <= 1'b0;
1158 eq_state_select_32 <= 1'b0;
1159 eq_state_select_33 <= 1'b0;
1160 eq_state_select_34 <= 1'b0;
1161 eq_state_select_35 <= 1'b0;
1162 eq_tail_select_pulse_0 <= 1'b0;
1163 eq_tail_select_pulse_1 <= 1'b0;
1164 eq_tail_select_pulse_2 <= 1'b0;
1165 eq_tail_select_pulse_3 <= 1'b0;
1166 eq_tail_select_pulse_4 <= 1'b0;
1167 eq_tail_select_pulse_5 <= 1'b0;
1168 eq_tail_select_pulse_6 <= 1'b0;
1169 eq_tail_select_pulse_7 <= 1'b0;
1170 eq_tail_select_pulse_8 <= 1'b0;
1171 eq_tail_select_pulse_9 <= 1'b0;
1172 eq_tail_select_pulse_10 <= 1'b0;
1173 eq_tail_select_pulse_11 <= 1'b0;
1174 eq_tail_select_pulse_12 <= 1'b0;
1175 eq_tail_select_pulse_13 <= 1'b0;
1176 eq_tail_select_pulse_14 <= 1'b0;
1177 eq_tail_select_pulse_15 <= 1'b0;
1178 eq_tail_select_pulse_16 <= 1'b0;
1179 eq_tail_select_pulse_17 <= 1'b0;
1180 eq_tail_select_pulse_18 <= 1'b0;
1181 eq_tail_select_pulse_19 <= 1'b0;
1182 eq_tail_select_pulse_20 <= 1'b0;
1183 eq_tail_select_pulse_21 <= 1'b0;
1184 eq_tail_select_pulse_22 <= 1'b0;
1185 eq_tail_select_pulse_23 <= 1'b0;
1186 eq_tail_select_pulse_24 <= 1'b0;
1187 eq_tail_select_pulse_25 <= 1'b0;
1188 eq_tail_select_pulse_26 <= 1'b0;
1189 eq_tail_select_pulse_27 <= 1'b0;
1190 eq_tail_select_pulse_28 <= 1'b0;
1191 eq_tail_select_pulse_29 <= 1'b0;
1192 eq_tail_select_pulse_30 <= 1'b0;
1193 eq_tail_select_pulse_31 <= 1'b0;
1194 eq_tail_select_pulse_32 <= 1'b0;
1195 eq_tail_select_pulse_33 <= 1'b0;
1196 eq_tail_select_pulse_34 <= 1'b0;
1197 eq_tail_select_pulse_35 <= 1'b0;
1198 eq_head_select_pulse_0 <= 1'b0;
1199 eq_head_select_pulse_1 <= 1'b0;
1200 eq_head_select_pulse_2 <= 1'b0;
1201 eq_head_select_pulse_3 <= 1'b0;
1202 eq_head_select_pulse_4 <= 1'b0;
1203 eq_head_select_pulse_5 <= 1'b0;
1204 eq_head_select_pulse_6 <= 1'b0;
1205 eq_head_select_pulse_7 <= 1'b0;
1206 eq_head_select_pulse_8 <= 1'b0;
1207 eq_head_select_pulse_9 <= 1'b0;
1208 eq_head_select_pulse_10 <= 1'b0;
1209 eq_head_select_pulse_11 <= 1'b0;
1210 eq_head_select_pulse_12 <= 1'b0;
1211 eq_head_select_pulse_13 <= 1'b0;
1212 eq_head_select_pulse_14 <= 1'b0;
1213 eq_head_select_pulse_15 <= 1'b0;
1214 eq_head_select_pulse_16 <= 1'b0;
1215 eq_head_select_pulse_17 <= 1'b0;
1216 eq_head_select_pulse_18 <= 1'b0;
1217 eq_head_select_pulse_19 <= 1'b0;
1218 eq_head_select_pulse_20 <= 1'b0;
1219 eq_head_select_pulse_21 <= 1'b0;
1220 eq_head_select_pulse_22 <= 1'b0;
1221 eq_head_select_pulse_23 <= 1'b0;
1222 eq_head_select_pulse_24 <= 1'b0;
1223 eq_head_select_pulse_25 <= 1'b0;
1224 eq_head_select_pulse_26 <= 1'b0;
1225 eq_head_select_pulse_27 <= 1'b0;
1226 eq_head_select_pulse_28 <= 1'b0;
1227 eq_head_select_pulse_29 <= 1'b0;
1228 eq_head_select_pulse_30 <= 1'b0;
1229 eq_head_select_pulse_31 <= 1'b0;
1230 eq_head_select_pulse_32 <= 1'b0;
1231 eq_head_select_pulse_33 <= 1'b0;
1232 eq_head_select_pulse_34 <= 1'b0;
1233 eq_head_select_pulse_35 <= 1'b0;
1234 end
1235 else
1236 begin
1237 eq_base_address_select_pulse <=
1238 ~eq_base_address_acc_vio &
1239 clocked_valid_pulse &
1240 eq_base_address_addr_decoded;
1241
1242 eq_ctrl_set_select_0 <=
1243 (
1244 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1245 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd0
1246 ) &
1247 ~eq_ctrl_set_acc_vio &
1248 eq_ctrl_set_addr_decoded;
1249
1250 eq_ctrl_set_select_1 <=
1251 (
1252 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1253 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd1
1254 ) &
1255 ~eq_ctrl_set_acc_vio &
1256 eq_ctrl_set_addr_decoded;
1257
1258 eq_ctrl_set_select_2 <=
1259 (
1260 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1261 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd2
1262 ) &
1263 ~eq_ctrl_set_acc_vio &
1264 eq_ctrl_set_addr_decoded;
1265
1266 eq_ctrl_set_select_3 <=
1267 (
1268 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1269 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd3
1270 ) &
1271 ~eq_ctrl_set_acc_vio &
1272 eq_ctrl_set_addr_decoded;
1273
1274 eq_ctrl_set_select_4 <=
1275 (
1276 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1277 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd4
1278 ) &
1279 ~eq_ctrl_set_acc_vio &
1280 eq_ctrl_set_addr_decoded;
1281
1282 eq_ctrl_set_select_5 <=
1283 (
1284 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1285 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd5
1286 ) &
1287 ~eq_ctrl_set_acc_vio &
1288 eq_ctrl_set_addr_decoded;
1289
1290 eq_ctrl_set_select_6 <=
1291 (
1292 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1293 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd6
1294 ) &
1295 ~eq_ctrl_set_acc_vio &
1296 eq_ctrl_set_addr_decoded;
1297
1298 eq_ctrl_set_select_7 <=
1299 (
1300 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1301 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd7
1302 ) &
1303 ~eq_ctrl_set_acc_vio &
1304 eq_ctrl_set_addr_decoded;
1305
1306 eq_ctrl_set_select_8 <=
1307 (
1308 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1309 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd8
1310 ) &
1311 ~eq_ctrl_set_acc_vio &
1312 eq_ctrl_set_addr_decoded;
1313
1314 eq_ctrl_set_select_9 <=
1315 (
1316 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1317 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd9
1318 ) &
1319 ~eq_ctrl_set_acc_vio &
1320 eq_ctrl_set_addr_decoded;
1321
1322 eq_ctrl_set_select_10 <=
1323 (
1324 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1325 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd10
1326 ) &
1327 ~eq_ctrl_set_acc_vio &
1328 eq_ctrl_set_addr_decoded;
1329
1330 eq_ctrl_set_select_11 <=
1331 (
1332 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1333 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd11
1334 ) &
1335 ~eq_ctrl_set_acc_vio &
1336 eq_ctrl_set_addr_decoded;
1337
1338 eq_ctrl_set_select_12 <=
1339 (
1340 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1341 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd12
1342 ) &
1343 ~eq_ctrl_set_acc_vio &
1344 eq_ctrl_set_addr_decoded;
1345
1346 eq_ctrl_set_select_13 <=
1347 (
1348 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1349 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd13
1350 ) &
1351 ~eq_ctrl_set_acc_vio &
1352 eq_ctrl_set_addr_decoded;
1353
1354 eq_ctrl_set_select_14 <=
1355 (
1356 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1357 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd14
1358 ) &
1359 ~eq_ctrl_set_acc_vio &
1360 eq_ctrl_set_addr_decoded;
1361
1362 eq_ctrl_set_select_15 <=
1363 (
1364 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1365 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd15
1366 ) &
1367 ~eq_ctrl_set_acc_vio &
1368 eq_ctrl_set_addr_decoded;
1369
1370 eq_ctrl_set_select_16 <=
1371 (
1372 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1373 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd16
1374 ) &
1375 ~eq_ctrl_set_acc_vio &
1376 eq_ctrl_set_addr_decoded;
1377
1378 eq_ctrl_set_select_17 <=
1379 (
1380 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1381 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd17
1382 ) &
1383 ~eq_ctrl_set_acc_vio &
1384 eq_ctrl_set_addr_decoded;
1385
1386 eq_ctrl_set_select_18 <=
1387 (
1388 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1389 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd18
1390 ) &
1391 ~eq_ctrl_set_acc_vio &
1392 eq_ctrl_set_addr_decoded;
1393
1394 eq_ctrl_set_select_19 <=
1395 (
1396 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1397 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd19
1398 ) &
1399 ~eq_ctrl_set_acc_vio &
1400 eq_ctrl_set_addr_decoded;
1401
1402 eq_ctrl_set_select_20 <=
1403 (
1404 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1405 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd20
1406 ) &
1407 ~eq_ctrl_set_acc_vio &
1408 eq_ctrl_set_addr_decoded;
1409
1410 eq_ctrl_set_select_21 <=
1411 (
1412 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1413 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd21
1414 ) &
1415 ~eq_ctrl_set_acc_vio &
1416 eq_ctrl_set_addr_decoded;
1417
1418 eq_ctrl_set_select_22 <=
1419 (
1420 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1421 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd22
1422 ) &
1423 ~eq_ctrl_set_acc_vio &
1424 eq_ctrl_set_addr_decoded;
1425
1426 eq_ctrl_set_select_23 <=
1427 (
1428 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1429 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd23
1430 ) &
1431 ~eq_ctrl_set_acc_vio &
1432 eq_ctrl_set_addr_decoded;
1433
1434 eq_ctrl_set_select_24 <=
1435 (
1436 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1437 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd24
1438 ) &
1439 ~eq_ctrl_set_acc_vio &
1440 eq_ctrl_set_addr_decoded;
1441
1442 eq_ctrl_set_select_25 <=
1443 (
1444 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1445 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd25
1446 ) &
1447 ~eq_ctrl_set_acc_vio &
1448 eq_ctrl_set_addr_decoded;
1449
1450 eq_ctrl_set_select_26 <=
1451 (
1452 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1453 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd26
1454 ) &
1455 ~eq_ctrl_set_acc_vio &
1456 eq_ctrl_set_addr_decoded;
1457
1458 eq_ctrl_set_select_27 <=
1459 (
1460 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1461 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd27
1462 ) &
1463 ~eq_ctrl_set_acc_vio &
1464 eq_ctrl_set_addr_decoded;
1465
1466 eq_ctrl_set_select_28 <=
1467 (
1468 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1469 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd28
1470 ) &
1471 ~eq_ctrl_set_acc_vio &
1472 eq_ctrl_set_addr_decoded;
1473
1474 eq_ctrl_set_select_29 <=
1475 (
1476 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1477 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd29
1478 ) &
1479 ~eq_ctrl_set_acc_vio &
1480 eq_ctrl_set_addr_decoded;
1481
1482 eq_ctrl_set_select_30 <=
1483 (
1484 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1485 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd30
1486 ) &
1487 ~eq_ctrl_set_acc_vio &
1488 eq_ctrl_set_addr_decoded;
1489
1490 eq_ctrl_set_select_31 <=
1491 (
1492 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1493 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd31
1494 ) &
1495 ~eq_ctrl_set_acc_vio &
1496 eq_ctrl_set_addr_decoded;
1497
1498 eq_ctrl_set_select_32 <=
1499 (
1500 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1501 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd32
1502 ) &
1503 ~eq_ctrl_set_acc_vio &
1504 eq_ctrl_set_addr_decoded;
1505
1506 eq_ctrl_set_select_33 <=
1507 (
1508 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1509 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd33
1510 ) &
1511 ~eq_ctrl_set_acc_vio &
1512 eq_ctrl_set_addr_decoded;
1513
1514 eq_ctrl_set_select_34 <=
1515 (
1516 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1517 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd34
1518 ) &
1519 ~eq_ctrl_set_acc_vio &
1520 eq_ctrl_set_addr_decoded;
1521
1522 eq_ctrl_set_select_35 <=
1523 (
1524 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH-1:0] ==
1525 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH'd35
1526 ) &
1527 ~eq_ctrl_set_acc_vio &
1528 eq_ctrl_set_addr_decoded;
1529
1530 eq_ctrl_clr_select_0 <=
1531 (
1532 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1533 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd0
1534 ) &
1535 ~eq_ctrl_clr_acc_vio &
1536 eq_ctrl_clr_addr_decoded;
1537
1538 eq_ctrl_clr_select_1 <=
1539 (
1540 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1541 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd1
1542 ) &
1543 ~eq_ctrl_clr_acc_vio &
1544 eq_ctrl_clr_addr_decoded;
1545
1546 eq_ctrl_clr_select_2 <=
1547 (
1548 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1549 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd2
1550 ) &
1551 ~eq_ctrl_clr_acc_vio &
1552 eq_ctrl_clr_addr_decoded;
1553
1554 eq_ctrl_clr_select_3 <=
1555 (
1556 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1557 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd3
1558 ) &
1559 ~eq_ctrl_clr_acc_vio &
1560 eq_ctrl_clr_addr_decoded;
1561
1562 eq_ctrl_clr_select_4 <=
1563 (
1564 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1565 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd4
1566 ) &
1567 ~eq_ctrl_clr_acc_vio &
1568 eq_ctrl_clr_addr_decoded;
1569
1570 eq_ctrl_clr_select_5 <=
1571 (
1572 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1573 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd5
1574 ) &
1575 ~eq_ctrl_clr_acc_vio &
1576 eq_ctrl_clr_addr_decoded;
1577
1578 eq_ctrl_clr_select_6 <=
1579 (
1580 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1581 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd6
1582 ) &
1583 ~eq_ctrl_clr_acc_vio &
1584 eq_ctrl_clr_addr_decoded;
1585
1586 eq_ctrl_clr_select_7 <=
1587 (
1588 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1589 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd7
1590 ) &
1591 ~eq_ctrl_clr_acc_vio &
1592 eq_ctrl_clr_addr_decoded;
1593
1594 eq_ctrl_clr_select_8 <=
1595 (
1596 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1597 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd8
1598 ) &
1599 ~eq_ctrl_clr_acc_vio &
1600 eq_ctrl_clr_addr_decoded;
1601
1602 eq_ctrl_clr_select_9 <=
1603 (
1604 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1605 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd9
1606 ) &
1607 ~eq_ctrl_clr_acc_vio &
1608 eq_ctrl_clr_addr_decoded;
1609
1610 eq_ctrl_clr_select_10 <=
1611 (
1612 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1613 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd10
1614 ) &
1615 ~eq_ctrl_clr_acc_vio &
1616 eq_ctrl_clr_addr_decoded;
1617
1618 eq_ctrl_clr_select_11 <=
1619 (
1620 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1621 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd11
1622 ) &
1623 ~eq_ctrl_clr_acc_vio &
1624 eq_ctrl_clr_addr_decoded;
1625
1626 eq_ctrl_clr_select_12 <=
1627 (
1628 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1629 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd12
1630 ) &
1631 ~eq_ctrl_clr_acc_vio &
1632 eq_ctrl_clr_addr_decoded;
1633
1634 eq_ctrl_clr_select_13 <=
1635 (
1636 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1637 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd13
1638 ) &
1639 ~eq_ctrl_clr_acc_vio &
1640 eq_ctrl_clr_addr_decoded;
1641
1642 eq_ctrl_clr_select_14 <=
1643 (
1644 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1645 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd14
1646 ) &
1647 ~eq_ctrl_clr_acc_vio &
1648 eq_ctrl_clr_addr_decoded;
1649
1650 eq_ctrl_clr_select_15 <=
1651 (
1652 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1653 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd15
1654 ) &
1655 ~eq_ctrl_clr_acc_vio &
1656 eq_ctrl_clr_addr_decoded;
1657
1658 eq_ctrl_clr_select_16 <=
1659 (
1660 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1661 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd16
1662 ) &
1663 ~eq_ctrl_clr_acc_vio &
1664 eq_ctrl_clr_addr_decoded;
1665
1666 eq_ctrl_clr_select_17 <=
1667 (
1668 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1669 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd17
1670 ) &
1671 ~eq_ctrl_clr_acc_vio &
1672 eq_ctrl_clr_addr_decoded;
1673
1674 eq_ctrl_clr_select_18 <=
1675 (
1676 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1677 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd18
1678 ) &
1679 ~eq_ctrl_clr_acc_vio &
1680 eq_ctrl_clr_addr_decoded;
1681
1682 eq_ctrl_clr_select_19 <=
1683 (
1684 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1685 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd19
1686 ) &
1687 ~eq_ctrl_clr_acc_vio &
1688 eq_ctrl_clr_addr_decoded;
1689
1690 eq_ctrl_clr_select_20 <=
1691 (
1692 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1693 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd20
1694 ) &
1695 ~eq_ctrl_clr_acc_vio &
1696 eq_ctrl_clr_addr_decoded;
1697
1698 eq_ctrl_clr_select_21 <=
1699 (
1700 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1701 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd21
1702 ) &
1703 ~eq_ctrl_clr_acc_vio &
1704 eq_ctrl_clr_addr_decoded;
1705
1706 eq_ctrl_clr_select_22 <=
1707 (
1708 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1709 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd22
1710 ) &
1711 ~eq_ctrl_clr_acc_vio &
1712 eq_ctrl_clr_addr_decoded;
1713
1714 eq_ctrl_clr_select_23 <=
1715 (
1716 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1717 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd23
1718 ) &
1719 ~eq_ctrl_clr_acc_vio &
1720 eq_ctrl_clr_addr_decoded;
1721
1722 eq_ctrl_clr_select_24 <=
1723 (
1724 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1725 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd24
1726 ) &
1727 ~eq_ctrl_clr_acc_vio &
1728 eq_ctrl_clr_addr_decoded;
1729
1730 eq_ctrl_clr_select_25 <=
1731 (
1732 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1733 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd25
1734 ) &
1735 ~eq_ctrl_clr_acc_vio &
1736 eq_ctrl_clr_addr_decoded;
1737
1738 eq_ctrl_clr_select_26 <=
1739 (
1740 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1741 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd26
1742 ) &
1743 ~eq_ctrl_clr_acc_vio &
1744 eq_ctrl_clr_addr_decoded;
1745
1746 eq_ctrl_clr_select_27 <=
1747 (
1748 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1749 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd27
1750 ) &
1751 ~eq_ctrl_clr_acc_vio &
1752 eq_ctrl_clr_addr_decoded;
1753
1754 eq_ctrl_clr_select_28 <=
1755 (
1756 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1757 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd28
1758 ) &
1759 ~eq_ctrl_clr_acc_vio &
1760 eq_ctrl_clr_addr_decoded;
1761
1762 eq_ctrl_clr_select_29 <=
1763 (
1764 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1765 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd29
1766 ) &
1767 ~eq_ctrl_clr_acc_vio &
1768 eq_ctrl_clr_addr_decoded;
1769
1770 eq_ctrl_clr_select_30 <=
1771 (
1772 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1773 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd30
1774 ) &
1775 ~eq_ctrl_clr_acc_vio &
1776 eq_ctrl_clr_addr_decoded;
1777
1778 eq_ctrl_clr_select_31 <=
1779 (
1780 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1781 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd31
1782 ) &
1783 ~eq_ctrl_clr_acc_vio &
1784 eq_ctrl_clr_addr_decoded;
1785
1786 eq_ctrl_clr_select_32 <=
1787 (
1788 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1789 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd32
1790 ) &
1791 ~eq_ctrl_clr_acc_vio &
1792 eq_ctrl_clr_addr_decoded;
1793
1794 eq_ctrl_clr_select_33 <=
1795 (
1796 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1797 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd33
1798 ) &
1799 ~eq_ctrl_clr_acc_vio &
1800 eq_ctrl_clr_addr_decoded;
1801
1802 eq_ctrl_clr_select_34 <=
1803 (
1804 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1805 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd34
1806 ) &
1807 ~eq_ctrl_clr_acc_vio &
1808 eq_ctrl_clr_addr_decoded;
1809
1810 eq_ctrl_clr_select_35 <=
1811 (
1812 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH-1:0] ==
1813 `FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH'd35
1814 ) &
1815 ~eq_ctrl_clr_acc_vio &
1816 eq_ctrl_clr_addr_decoded;
1817
1818 eq_state_select_0 <=
1819 (
1820 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1821 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd0
1822 ) &
1823 ~eq_state_acc_vio &
1824 eq_state_addr_decoded;
1825
1826 eq_state_select_1 <=
1827 (
1828 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1829 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd1
1830 ) &
1831 ~eq_state_acc_vio &
1832 eq_state_addr_decoded;
1833
1834 eq_state_select_2 <=
1835 (
1836 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1837 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd2
1838 ) &
1839 ~eq_state_acc_vio &
1840 eq_state_addr_decoded;
1841
1842 eq_state_select_3 <=
1843 (
1844 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1845 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd3
1846 ) &
1847 ~eq_state_acc_vio &
1848 eq_state_addr_decoded;
1849
1850 eq_state_select_4 <=
1851 (
1852 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1853 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd4
1854 ) &
1855 ~eq_state_acc_vio &
1856 eq_state_addr_decoded;
1857
1858 eq_state_select_5 <=
1859 (
1860 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1861 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd5
1862 ) &
1863 ~eq_state_acc_vio &
1864 eq_state_addr_decoded;
1865
1866 eq_state_select_6 <=
1867 (
1868 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1869 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd6
1870 ) &
1871 ~eq_state_acc_vio &
1872 eq_state_addr_decoded;
1873
1874 eq_state_select_7 <=
1875 (
1876 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1877 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd7
1878 ) &
1879 ~eq_state_acc_vio &
1880 eq_state_addr_decoded;
1881
1882 eq_state_select_8 <=
1883 (
1884 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1885 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd8
1886 ) &
1887 ~eq_state_acc_vio &
1888 eq_state_addr_decoded;
1889
1890 eq_state_select_9 <=
1891 (
1892 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1893 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd9
1894 ) &
1895 ~eq_state_acc_vio &
1896 eq_state_addr_decoded;
1897
1898 eq_state_select_10 <=
1899 (
1900 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1901 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd10
1902 ) &
1903 ~eq_state_acc_vio &
1904 eq_state_addr_decoded;
1905
1906 eq_state_select_11 <=
1907 (
1908 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1909 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd11
1910 ) &
1911 ~eq_state_acc_vio &
1912 eq_state_addr_decoded;
1913
1914 eq_state_select_12 <=
1915 (
1916 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1917 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd12
1918 ) &
1919 ~eq_state_acc_vio &
1920 eq_state_addr_decoded;
1921
1922 eq_state_select_13 <=
1923 (
1924 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1925 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd13
1926 ) &
1927 ~eq_state_acc_vio &
1928 eq_state_addr_decoded;
1929
1930 eq_state_select_14 <=
1931 (
1932 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1933 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd14
1934 ) &
1935 ~eq_state_acc_vio &
1936 eq_state_addr_decoded;
1937
1938 eq_state_select_15 <=
1939 (
1940 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1941 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd15
1942 ) &
1943 ~eq_state_acc_vio &
1944 eq_state_addr_decoded;
1945
1946 eq_state_select_16 <=
1947 (
1948 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1949 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd16
1950 ) &
1951 ~eq_state_acc_vio &
1952 eq_state_addr_decoded;
1953
1954 eq_state_select_17 <=
1955 (
1956 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1957 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd17
1958 ) &
1959 ~eq_state_acc_vio &
1960 eq_state_addr_decoded;
1961
1962 eq_state_select_18 <=
1963 (
1964 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1965 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd18
1966 ) &
1967 ~eq_state_acc_vio &
1968 eq_state_addr_decoded;
1969
1970 eq_state_select_19 <=
1971 (
1972 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1973 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd19
1974 ) &
1975 ~eq_state_acc_vio &
1976 eq_state_addr_decoded;
1977
1978 eq_state_select_20 <=
1979 (
1980 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1981 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd20
1982 ) &
1983 ~eq_state_acc_vio &
1984 eq_state_addr_decoded;
1985
1986 eq_state_select_21 <=
1987 (
1988 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1989 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd21
1990 ) &
1991 ~eq_state_acc_vio &
1992 eq_state_addr_decoded;
1993
1994 eq_state_select_22 <=
1995 (
1996 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
1997 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd22
1998 ) &
1999 ~eq_state_acc_vio &
2000 eq_state_addr_decoded;
2001
2002 eq_state_select_23 <=
2003 (
2004 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2005 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd23
2006 ) &
2007 ~eq_state_acc_vio &
2008 eq_state_addr_decoded;
2009
2010 eq_state_select_24 <=
2011 (
2012 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2013 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd24
2014 ) &
2015 ~eq_state_acc_vio &
2016 eq_state_addr_decoded;
2017
2018 eq_state_select_25 <=
2019 (
2020 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2021 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd25
2022 ) &
2023 ~eq_state_acc_vio &
2024 eq_state_addr_decoded;
2025
2026 eq_state_select_26 <=
2027 (
2028 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2029 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd26
2030 ) &
2031 ~eq_state_acc_vio &
2032 eq_state_addr_decoded;
2033
2034 eq_state_select_27 <=
2035 (
2036 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2037 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd27
2038 ) &
2039 ~eq_state_acc_vio &
2040 eq_state_addr_decoded;
2041
2042 eq_state_select_28 <=
2043 (
2044 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2045 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd28
2046 ) &
2047 ~eq_state_acc_vio &
2048 eq_state_addr_decoded;
2049
2050 eq_state_select_29 <=
2051 (
2052 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2053 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd29
2054 ) &
2055 ~eq_state_acc_vio &
2056 eq_state_addr_decoded;
2057
2058 eq_state_select_30 <=
2059 (
2060 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2061 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd30
2062 ) &
2063 ~eq_state_acc_vio &
2064 eq_state_addr_decoded;
2065
2066 eq_state_select_31 <=
2067 (
2068 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2069 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd31
2070 ) &
2071 ~eq_state_acc_vio &
2072 eq_state_addr_decoded;
2073
2074 eq_state_select_32 <=
2075 (
2076 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2077 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd32
2078 ) &
2079 ~eq_state_acc_vio &
2080 eq_state_addr_decoded;
2081
2082 eq_state_select_33 <=
2083 (
2084 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2085 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd33
2086 ) &
2087 ~eq_state_acc_vio &
2088 eq_state_addr_decoded;
2089
2090 eq_state_select_34 <=
2091 (
2092 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2093 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd34
2094 ) &
2095 ~eq_state_acc_vio &
2096 eq_state_addr_decoded;
2097
2098 eq_state_select_35 <=
2099 (
2100 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH-1:0] ==
2101 `FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH'd35
2102 ) &
2103 ~eq_state_acc_vio &
2104 eq_state_addr_decoded;
2105
2106 eq_tail_select_pulse_0 <=
2107 (
2108 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2109 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd0
2110 ) &
2111 ~eq_tail_acc_vio &
2112 clocked_valid_pulse &
2113 eq_tail_addr_decoded;
2114
2115 eq_tail_select_pulse_1 <=
2116 (
2117 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2118 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd1
2119 ) &
2120 ~eq_tail_acc_vio &
2121 clocked_valid_pulse &
2122 eq_tail_addr_decoded;
2123
2124 eq_tail_select_pulse_2 <=
2125 (
2126 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2127 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd2
2128 ) &
2129 ~eq_tail_acc_vio &
2130 clocked_valid_pulse &
2131 eq_tail_addr_decoded;
2132
2133 eq_tail_select_pulse_3 <=
2134 (
2135 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2136 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd3
2137 ) &
2138 ~eq_tail_acc_vio &
2139 clocked_valid_pulse &
2140 eq_tail_addr_decoded;
2141
2142 eq_tail_select_pulse_4 <=
2143 (
2144 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2145 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd4
2146 ) &
2147 ~eq_tail_acc_vio &
2148 clocked_valid_pulse &
2149 eq_tail_addr_decoded;
2150
2151 eq_tail_select_pulse_5 <=
2152 (
2153 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2154 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd5
2155 ) &
2156 ~eq_tail_acc_vio &
2157 clocked_valid_pulse &
2158 eq_tail_addr_decoded;
2159
2160 eq_tail_select_pulse_6 <=
2161 (
2162 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2163 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd6
2164 ) &
2165 ~eq_tail_acc_vio &
2166 clocked_valid_pulse &
2167 eq_tail_addr_decoded;
2168
2169 eq_tail_select_pulse_7 <=
2170 (
2171 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2172 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd7
2173 ) &
2174 ~eq_tail_acc_vio &
2175 clocked_valid_pulse &
2176 eq_tail_addr_decoded;
2177
2178 eq_tail_select_pulse_8 <=
2179 (
2180 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2181 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd8
2182 ) &
2183 ~eq_tail_acc_vio &
2184 clocked_valid_pulse &
2185 eq_tail_addr_decoded;
2186
2187 eq_tail_select_pulse_9 <=
2188 (
2189 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2190 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd9
2191 ) &
2192 ~eq_tail_acc_vio &
2193 clocked_valid_pulse &
2194 eq_tail_addr_decoded;
2195
2196 eq_tail_select_pulse_10 <=
2197 (
2198 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2199 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd10
2200 ) &
2201 ~eq_tail_acc_vio &
2202 clocked_valid_pulse &
2203 eq_tail_addr_decoded;
2204
2205 eq_tail_select_pulse_11 <=
2206 (
2207 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2208 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd11
2209 ) &
2210 ~eq_tail_acc_vio &
2211 clocked_valid_pulse &
2212 eq_tail_addr_decoded;
2213
2214 eq_tail_select_pulse_12 <=
2215 (
2216 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2217 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd12
2218 ) &
2219 ~eq_tail_acc_vio &
2220 clocked_valid_pulse &
2221 eq_tail_addr_decoded;
2222
2223 eq_tail_select_pulse_13 <=
2224 (
2225 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2226 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd13
2227 ) &
2228 ~eq_tail_acc_vio &
2229 clocked_valid_pulse &
2230 eq_tail_addr_decoded;
2231
2232 eq_tail_select_pulse_14 <=
2233 (
2234 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2235 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd14
2236 ) &
2237 ~eq_tail_acc_vio &
2238 clocked_valid_pulse &
2239 eq_tail_addr_decoded;
2240
2241 eq_tail_select_pulse_15 <=
2242 (
2243 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2244 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd15
2245 ) &
2246 ~eq_tail_acc_vio &
2247 clocked_valid_pulse &
2248 eq_tail_addr_decoded;
2249
2250 eq_tail_select_pulse_16 <=
2251 (
2252 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2253 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd16
2254 ) &
2255 ~eq_tail_acc_vio &
2256 clocked_valid_pulse &
2257 eq_tail_addr_decoded;
2258
2259 eq_tail_select_pulse_17 <=
2260 (
2261 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2262 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd17
2263 ) &
2264 ~eq_tail_acc_vio &
2265 clocked_valid_pulse &
2266 eq_tail_addr_decoded;
2267
2268 eq_tail_select_pulse_18 <=
2269 (
2270 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2271 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd18
2272 ) &
2273 ~eq_tail_acc_vio &
2274 clocked_valid_pulse &
2275 eq_tail_addr_decoded;
2276
2277 eq_tail_select_pulse_19 <=
2278 (
2279 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2280 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd19
2281 ) &
2282 ~eq_tail_acc_vio &
2283 clocked_valid_pulse &
2284 eq_tail_addr_decoded;
2285
2286 eq_tail_select_pulse_20 <=
2287 (
2288 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2289 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd20
2290 ) &
2291 ~eq_tail_acc_vio &
2292 clocked_valid_pulse &
2293 eq_tail_addr_decoded;
2294
2295 eq_tail_select_pulse_21 <=
2296 (
2297 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2298 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd21
2299 ) &
2300 ~eq_tail_acc_vio &
2301 clocked_valid_pulse &
2302 eq_tail_addr_decoded;
2303
2304 eq_tail_select_pulse_22 <=
2305 (
2306 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2307 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd22
2308 ) &
2309 ~eq_tail_acc_vio &
2310 clocked_valid_pulse &
2311 eq_tail_addr_decoded;
2312
2313 eq_tail_select_pulse_23 <=
2314 (
2315 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2316 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd23
2317 ) &
2318 ~eq_tail_acc_vio &
2319 clocked_valid_pulse &
2320 eq_tail_addr_decoded;
2321
2322 eq_tail_select_pulse_24 <=
2323 (
2324 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2325 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd24
2326 ) &
2327 ~eq_tail_acc_vio &
2328 clocked_valid_pulse &
2329 eq_tail_addr_decoded;
2330
2331 eq_tail_select_pulse_25 <=
2332 (
2333 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2334 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd25
2335 ) &
2336 ~eq_tail_acc_vio &
2337 clocked_valid_pulse &
2338 eq_tail_addr_decoded;
2339
2340 eq_tail_select_pulse_26 <=
2341 (
2342 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2343 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd26
2344 ) &
2345 ~eq_tail_acc_vio &
2346 clocked_valid_pulse &
2347 eq_tail_addr_decoded;
2348
2349 eq_tail_select_pulse_27 <=
2350 (
2351 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2352 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd27
2353 ) &
2354 ~eq_tail_acc_vio &
2355 clocked_valid_pulse &
2356 eq_tail_addr_decoded;
2357
2358 eq_tail_select_pulse_28 <=
2359 (
2360 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2361 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd28
2362 ) &
2363 ~eq_tail_acc_vio &
2364 clocked_valid_pulse &
2365 eq_tail_addr_decoded;
2366
2367 eq_tail_select_pulse_29 <=
2368 (
2369 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2370 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd29
2371 ) &
2372 ~eq_tail_acc_vio &
2373 clocked_valid_pulse &
2374 eq_tail_addr_decoded;
2375
2376 eq_tail_select_pulse_30 <=
2377 (
2378 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2379 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd30
2380 ) &
2381 ~eq_tail_acc_vio &
2382 clocked_valid_pulse &
2383 eq_tail_addr_decoded;
2384
2385 eq_tail_select_pulse_31 <=
2386 (
2387 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2388 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd31
2389 ) &
2390 ~eq_tail_acc_vio &
2391 clocked_valid_pulse &
2392 eq_tail_addr_decoded;
2393
2394 eq_tail_select_pulse_32 <=
2395 (
2396 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2397 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd32
2398 ) &
2399 ~eq_tail_acc_vio &
2400 clocked_valid_pulse &
2401 eq_tail_addr_decoded;
2402
2403 eq_tail_select_pulse_33 <=
2404 (
2405 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2406 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd33
2407 ) &
2408 ~eq_tail_acc_vio &
2409 clocked_valid_pulse &
2410 eq_tail_addr_decoded;
2411
2412 eq_tail_select_pulse_34 <=
2413 (
2414 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2415 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd34
2416 ) &
2417 ~eq_tail_acc_vio &
2418 clocked_valid_pulse &
2419 eq_tail_addr_decoded;
2420
2421 eq_tail_select_pulse_35 <=
2422 (
2423 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH-1:0] ==
2424 `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH'd35
2425 ) &
2426 ~eq_tail_acc_vio &
2427 clocked_valid_pulse &
2428 eq_tail_addr_decoded;
2429
2430 eq_head_select_pulse_0 <=
2431 (
2432 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2433 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd0
2434 ) &
2435 ~eq_head_acc_vio &
2436 clocked_valid_pulse &
2437 eq_head_addr_decoded;
2438
2439 eq_head_select_pulse_1 <=
2440 (
2441 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2442 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd1
2443 ) &
2444 ~eq_head_acc_vio &
2445 clocked_valid_pulse &
2446 eq_head_addr_decoded;
2447
2448 eq_head_select_pulse_2 <=
2449 (
2450 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2451 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd2
2452 ) &
2453 ~eq_head_acc_vio &
2454 clocked_valid_pulse &
2455 eq_head_addr_decoded;
2456
2457 eq_head_select_pulse_3 <=
2458 (
2459 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2460 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd3
2461 ) &
2462 ~eq_head_acc_vio &
2463 clocked_valid_pulse &
2464 eq_head_addr_decoded;
2465
2466 eq_head_select_pulse_4 <=
2467 (
2468 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2469 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd4
2470 ) &
2471 ~eq_head_acc_vio &
2472 clocked_valid_pulse &
2473 eq_head_addr_decoded;
2474
2475 eq_head_select_pulse_5 <=
2476 (
2477 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2478 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd5
2479 ) &
2480 ~eq_head_acc_vio &
2481 clocked_valid_pulse &
2482 eq_head_addr_decoded;
2483
2484 eq_head_select_pulse_6 <=
2485 (
2486 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2487 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd6
2488 ) &
2489 ~eq_head_acc_vio &
2490 clocked_valid_pulse &
2491 eq_head_addr_decoded;
2492
2493 eq_head_select_pulse_7 <=
2494 (
2495 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2496 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd7
2497 ) &
2498 ~eq_head_acc_vio &
2499 clocked_valid_pulse &
2500 eq_head_addr_decoded;
2501
2502 eq_head_select_pulse_8 <=
2503 (
2504 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2505 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd8
2506 ) &
2507 ~eq_head_acc_vio &
2508 clocked_valid_pulse &
2509 eq_head_addr_decoded;
2510
2511 eq_head_select_pulse_9 <=
2512 (
2513 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2514 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd9
2515 ) &
2516 ~eq_head_acc_vio &
2517 clocked_valid_pulse &
2518 eq_head_addr_decoded;
2519
2520 eq_head_select_pulse_10 <=
2521 (
2522 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2523 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd10
2524 ) &
2525 ~eq_head_acc_vio &
2526 clocked_valid_pulse &
2527 eq_head_addr_decoded;
2528
2529 eq_head_select_pulse_11 <=
2530 (
2531 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2532 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd11
2533 ) &
2534 ~eq_head_acc_vio &
2535 clocked_valid_pulse &
2536 eq_head_addr_decoded;
2537
2538 eq_head_select_pulse_12 <=
2539 (
2540 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2541 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd12
2542 ) &
2543 ~eq_head_acc_vio &
2544 clocked_valid_pulse &
2545 eq_head_addr_decoded;
2546
2547 eq_head_select_pulse_13 <=
2548 (
2549 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2550 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd13
2551 ) &
2552 ~eq_head_acc_vio &
2553 clocked_valid_pulse &
2554 eq_head_addr_decoded;
2555
2556 eq_head_select_pulse_14 <=
2557 (
2558 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2559 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd14
2560 ) &
2561 ~eq_head_acc_vio &
2562 clocked_valid_pulse &
2563 eq_head_addr_decoded;
2564
2565 eq_head_select_pulse_15 <=
2566 (
2567 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2568 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd15
2569 ) &
2570 ~eq_head_acc_vio &
2571 clocked_valid_pulse &
2572 eq_head_addr_decoded;
2573
2574 eq_head_select_pulse_16 <=
2575 (
2576 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2577 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd16
2578 ) &
2579 ~eq_head_acc_vio &
2580 clocked_valid_pulse &
2581 eq_head_addr_decoded;
2582
2583 eq_head_select_pulse_17 <=
2584 (
2585 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2586 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd17
2587 ) &
2588 ~eq_head_acc_vio &
2589 clocked_valid_pulse &
2590 eq_head_addr_decoded;
2591
2592 eq_head_select_pulse_18 <=
2593 (
2594 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2595 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd18
2596 ) &
2597 ~eq_head_acc_vio &
2598 clocked_valid_pulse &
2599 eq_head_addr_decoded;
2600
2601 eq_head_select_pulse_19 <=
2602 (
2603 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2604 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd19
2605 ) &
2606 ~eq_head_acc_vio &
2607 clocked_valid_pulse &
2608 eq_head_addr_decoded;
2609
2610 eq_head_select_pulse_20 <=
2611 (
2612 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2613 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd20
2614 ) &
2615 ~eq_head_acc_vio &
2616 clocked_valid_pulse &
2617 eq_head_addr_decoded;
2618
2619 eq_head_select_pulse_21 <=
2620 (
2621 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2622 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd21
2623 ) &
2624 ~eq_head_acc_vio &
2625 clocked_valid_pulse &
2626 eq_head_addr_decoded;
2627
2628 eq_head_select_pulse_22 <=
2629 (
2630 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2631 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd22
2632 ) &
2633 ~eq_head_acc_vio &
2634 clocked_valid_pulse &
2635 eq_head_addr_decoded;
2636
2637 eq_head_select_pulse_23 <=
2638 (
2639 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2640 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd23
2641 ) &
2642 ~eq_head_acc_vio &
2643 clocked_valid_pulse &
2644 eq_head_addr_decoded;
2645
2646 eq_head_select_pulse_24 <=
2647 (
2648 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2649 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd24
2650 ) &
2651 ~eq_head_acc_vio &
2652 clocked_valid_pulse &
2653 eq_head_addr_decoded;
2654
2655 eq_head_select_pulse_25 <=
2656 (
2657 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2658 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd25
2659 ) &
2660 ~eq_head_acc_vio &
2661 clocked_valid_pulse &
2662 eq_head_addr_decoded;
2663
2664 eq_head_select_pulse_26 <=
2665 (
2666 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2667 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd26
2668 ) &
2669 ~eq_head_acc_vio &
2670 clocked_valid_pulse &
2671 eq_head_addr_decoded;
2672
2673 eq_head_select_pulse_27 <=
2674 (
2675 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2676 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd27
2677 ) &
2678 ~eq_head_acc_vio &
2679 clocked_valid_pulse &
2680 eq_head_addr_decoded;
2681
2682 eq_head_select_pulse_28 <=
2683 (
2684 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2685 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd28
2686 ) &
2687 ~eq_head_acc_vio &
2688 clocked_valid_pulse &
2689 eq_head_addr_decoded;
2690
2691 eq_head_select_pulse_29 <=
2692 (
2693 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2694 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd29
2695 ) &
2696 ~eq_head_acc_vio &
2697 clocked_valid_pulse &
2698 eq_head_addr_decoded;
2699
2700 eq_head_select_pulse_30 <=
2701 (
2702 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2703 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd30
2704 ) &
2705 ~eq_head_acc_vio &
2706 clocked_valid_pulse &
2707 eq_head_addr_decoded;
2708
2709 eq_head_select_pulse_31 <=
2710 (
2711 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2712 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd31
2713 ) &
2714 ~eq_head_acc_vio &
2715 clocked_valid_pulse &
2716 eq_head_addr_decoded;
2717
2718 eq_head_select_pulse_32 <=
2719 (
2720 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2721 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd32
2722 ) &
2723 ~eq_head_acc_vio &
2724 clocked_valid_pulse &
2725 eq_head_addr_decoded;
2726
2727 eq_head_select_pulse_33 <=
2728 (
2729 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2730 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd33
2731 ) &
2732 ~eq_head_acc_vio &
2733 clocked_valid_pulse &
2734 eq_head_addr_decoded;
2735
2736 eq_head_select_pulse_34 <=
2737 (
2738 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2739 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd34
2740 ) &
2741 ~eq_head_acc_vio &
2742 clocked_valid_pulse &
2743 eq_head_addr_decoded;
2744
2745 eq_head_select_pulse_35 <=
2746 (
2747 daemon_csrbus_addr[`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH-1:0] ==
2748 `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH'd35
2749 ) &
2750 ~eq_head_acc_vio &
2751 clocked_valid_pulse &
2752 eq_head_addr_decoded;
2753
2754 end
2755 end
2756
2757//====================================================================
2758// daemon_csrbus_wr / daemon_csrbus_wr_data
2759//====================================================================
2760always @(posedge clk)
2761 begin
2762 if(~rst_l)
2763 begin
2764 daemon_csrbus_wr_out <= 1'b0;
2765 daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0;
2766 end
2767 else
2768 begin
2769 daemon_csrbus_wr_out <= daemon_csrbus_wr;
2770 daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data;
2771 end
2772 end
2773
2774//====================================================================
2775// Cycle Counter: Used for ExtReadTiming / ExtWriteTiming
2776//====================================================================
2777
2778//====================================================================
2779// OUTPUT: daemon_csrbus_done (pipelining)
2780//====================================================================
2781//----- DONE for internal/extern registers
2782reg stage_1_daemon_csrbus_done_internal_0;
2783reg stage_1_daemon_csrbus_done_internal_1;
2784reg stage_2_daemon_csrbus_done_internal_0;
2785
2786always @(posedge clk)
2787 begin
2788 if(~rst_l)
2789 begin
2790 stage_1_daemon_csrbus_done_internal_0 <= 1'b0;
2791 stage_1_daemon_csrbus_done_internal_1 <= 1'b0;
2792 end
2793 else
2794 begin
2795 stage_1_daemon_csrbus_done_internal_0 <=
2796 eq_base_address_select_pulse |
2797 eq_tail_select_pulse_0 |
2798 eq_tail_select_pulse_1 |
2799 eq_tail_select_pulse_2 |
2800 eq_tail_select_pulse_3 |
2801 eq_tail_select_pulse_4 |
2802 eq_tail_select_pulse_5 |
2803 eq_tail_select_pulse_6 |
2804 eq_tail_select_pulse_7 |
2805 eq_tail_select_pulse_8 |
2806 eq_tail_select_pulse_9 |
2807 eq_tail_select_pulse_10 |
2808 eq_tail_select_pulse_11 |
2809 eq_tail_select_pulse_12 |
2810 eq_tail_select_pulse_13 |
2811 eq_tail_select_pulse_14 |
2812 eq_tail_select_pulse_15 |
2813 eq_tail_select_pulse_16 |
2814 eq_tail_select_pulse_17 |
2815 eq_tail_select_pulse_18 |
2816 eq_tail_select_pulse_19 |
2817 eq_tail_select_pulse_20 |
2818 eq_tail_select_pulse_21 |
2819 eq_tail_select_pulse_22 |
2820 eq_tail_select_pulse_23 |
2821 eq_tail_select_pulse_24 |
2822 eq_tail_select_pulse_25 |
2823 eq_tail_select_pulse_26 |
2824 eq_tail_select_pulse_27 |
2825 eq_tail_select_pulse_28 |
2826 eq_tail_select_pulse_29 |
2827 eq_tail_select_pulse_30 |
2828 eq_tail_select_pulse_31 |
2829 eq_tail_select_pulse_32 |
2830 eq_tail_select_pulse_33 |
2831 eq_tail_select_pulse_34 |
2832 eq_tail_select_pulse_35 |
2833 eq_head_select_pulse_0 |
2834 eq_head_select_pulse_1 |
2835 eq_head_select_pulse_2 |
2836 eq_head_select_pulse_3 |
2837 eq_head_select_pulse_4 |
2838 eq_head_select_pulse_5 |
2839 eq_head_select_pulse_6 |
2840 eq_head_select_pulse_7 |
2841 eq_head_select_pulse_8 |
2842 eq_head_select_pulse_9 |
2843 eq_head_select_pulse_10 |
2844 eq_head_select_pulse_11 |
2845 eq_head_select_pulse_12 |
2846 eq_head_select_pulse_13 |
2847 eq_head_select_pulse_14 |
2848 eq_head_select_pulse_15 |
2849 eq_head_select_pulse_16 |
2850 eq_head_select_pulse_17 |
2851 eq_head_select_pulse_18 |
2852 eq_head_select_pulse_19 |
2853 eq_head_select_pulse_20 |
2854 eq_head_select_pulse_21 |
2855 eq_head_select_pulse_22 |
2856 eq_head_select_pulse_23 |
2857 eq_head_select_pulse_24 |
2858 eq_head_select_pulse_25 |
2859 eq_head_select_pulse_26 |
2860 eq_head_select_pulse_27 |
2861 eq_head_select_pulse_28 |
2862 eq_head_select_pulse_29 |
2863 eq_head_select_pulse_30 |
2864 eq_head_select_pulse_31 |
2865 eq_head_select_pulse_32 |
2866 eq_head_select_pulse_33 |
2867 eq_head_select_pulse_34 |
2868 eq_head_select_pulse_35 |
2869 eq_ctrl_set_select_0 & clocked_valid_pulse |
2870 eq_ctrl_set_select_1 & clocked_valid_pulse |
2871 eq_ctrl_set_select_2 & clocked_valid_pulse |
2872 eq_ctrl_set_select_3 & clocked_valid_pulse |
2873 eq_ctrl_set_select_4 & clocked_valid_pulse |
2874 eq_ctrl_set_select_5 & clocked_valid_pulse |
2875 eq_ctrl_set_select_6 & clocked_valid_pulse |
2876 eq_ctrl_set_select_7 & clocked_valid_pulse |
2877 eq_ctrl_set_select_8 & clocked_valid_pulse |
2878 eq_ctrl_set_select_9 & clocked_valid_pulse |
2879 eq_ctrl_set_select_10 & clocked_valid_pulse |
2880 eq_ctrl_set_select_11 & clocked_valid_pulse |
2881 eq_ctrl_set_select_12 & clocked_valid_pulse |
2882 eq_ctrl_set_select_13 & clocked_valid_pulse |
2883 eq_ctrl_set_select_14 & clocked_valid_pulse |
2884 eq_ctrl_set_select_15 & clocked_valid_pulse |
2885 eq_ctrl_set_select_16 & clocked_valid_pulse |
2886 eq_ctrl_set_select_17 & clocked_valid_pulse |
2887 eq_ctrl_set_select_18 & clocked_valid_pulse |
2888 eq_ctrl_set_select_19 & clocked_valid_pulse |
2889 eq_ctrl_set_select_20 & clocked_valid_pulse |
2890 eq_ctrl_set_select_21 & clocked_valid_pulse |
2891 eq_ctrl_set_select_22 & clocked_valid_pulse |
2892 eq_ctrl_set_select_23 & clocked_valid_pulse |
2893 eq_ctrl_set_select_24 & clocked_valid_pulse |
2894 eq_ctrl_set_select_25 & clocked_valid_pulse |
2895 eq_ctrl_set_select_26 & clocked_valid_pulse |
2896 eq_ctrl_set_select_27 & clocked_valid_pulse |
2897 eq_ctrl_set_select_28 & clocked_valid_pulse |
2898 eq_ctrl_set_select_29 & clocked_valid_pulse |
2899 eq_ctrl_set_select_30 & clocked_valid_pulse |
2900 eq_ctrl_set_select_31 & clocked_valid_pulse |
2901 eq_ctrl_set_select_32 & clocked_valid_pulse |
2902 eq_ctrl_set_select_33 & clocked_valid_pulse |
2903 eq_ctrl_set_select_34 & clocked_valid_pulse |
2904 eq_ctrl_set_select_35 & clocked_valid_pulse;
2905 stage_1_daemon_csrbus_done_internal_1 <=
2906 eq_ctrl_clr_select_0 & clocked_valid_pulse |
2907 eq_ctrl_clr_select_1 & clocked_valid_pulse |
2908 eq_ctrl_clr_select_2 & clocked_valid_pulse |
2909 eq_ctrl_clr_select_3 & clocked_valid_pulse |
2910 eq_ctrl_clr_select_4 & clocked_valid_pulse |
2911 eq_ctrl_clr_select_5 & clocked_valid_pulse |
2912 eq_ctrl_clr_select_6 & clocked_valid_pulse |
2913 eq_ctrl_clr_select_7 & clocked_valid_pulse |
2914 eq_ctrl_clr_select_8 & clocked_valid_pulse |
2915 eq_ctrl_clr_select_9 & clocked_valid_pulse |
2916 eq_ctrl_clr_select_10 & clocked_valid_pulse |
2917 eq_ctrl_clr_select_11 & clocked_valid_pulse |
2918 eq_ctrl_clr_select_12 & clocked_valid_pulse |
2919 eq_ctrl_clr_select_13 & clocked_valid_pulse |
2920 eq_ctrl_clr_select_14 & clocked_valid_pulse |
2921 eq_ctrl_clr_select_15 & clocked_valid_pulse |
2922 eq_ctrl_clr_select_16 & clocked_valid_pulse |
2923 eq_ctrl_clr_select_17 & clocked_valid_pulse |
2924 eq_ctrl_clr_select_18 & clocked_valid_pulse |
2925 eq_ctrl_clr_select_19 & clocked_valid_pulse |
2926 eq_ctrl_clr_select_20 & clocked_valid_pulse |
2927 eq_ctrl_clr_select_21 & clocked_valid_pulse |
2928 eq_ctrl_clr_select_22 & clocked_valid_pulse |
2929 eq_ctrl_clr_select_23 & clocked_valid_pulse |
2930 eq_ctrl_clr_select_24 & clocked_valid_pulse |
2931 eq_ctrl_clr_select_25 & clocked_valid_pulse |
2932 eq_ctrl_clr_select_26 & clocked_valid_pulse |
2933 eq_ctrl_clr_select_27 & clocked_valid_pulse |
2934 eq_ctrl_clr_select_28 & clocked_valid_pulse |
2935 eq_ctrl_clr_select_29 & clocked_valid_pulse |
2936 eq_ctrl_clr_select_30 & clocked_valid_pulse |
2937 eq_ctrl_clr_select_31 & clocked_valid_pulse |
2938 eq_ctrl_clr_select_32 & clocked_valid_pulse |
2939 eq_ctrl_clr_select_33 & clocked_valid_pulse |
2940 eq_ctrl_clr_select_34 & clocked_valid_pulse |
2941 eq_ctrl_clr_select_35 & clocked_valid_pulse |
2942 eq_state_select_0 & clocked_valid_pulse |
2943 eq_state_select_1 & clocked_valid_pulse |
2944 eq_state_select_2 & clocked_valid_pulse |
2945 eq_state_select_3 & clocked_valid_pulse |
2946 eq_state_select_4 & clocked_valid_pulse |
2947 eq_state_select_5 & clocked_valid_pulse |
2948 eq_state_select_6 & clocked_valid_pulse |
2949 eq_state_select_7 & clocked_valid_pulse |
2950 eq_state_select_8 & clocked_valid_pulse |
2951 eq_state_select_9 & clocked_valid_pulse |
2952 eq_state_select_10 & clocked_valid_pulse |
2953 eq_state_select_11 & clocked_valid_pulse |
2954 eq_state_select_12 & clocked_valid_pulse |
2955 eq_state_select_13 & clocked_valid_pulse |
2956 eq_state_select_14 & clocked_valid_pulse |
2957 eq_state_select_15 & clocked_valid_pulse |
2958 eq_state_select_16 & clocked_valid_pulse |
2959 eq_state_select_17 & clocked_valid_pulse |
2960 eq_state_select_18 & clocked_valid_pulse |
2961 eq_state_select_19 & clocked_valid_pulse |
2962 eq_state_select_20 & clocked_valid_pulse |
2963 eq_state_select_21 & clocked_valid_pulse |
2964 eq_state_select_22 & clocked_valid_pulse |
2965 eq_state_select_23 & clocked_valid_pulse |
2966 eq_state_select_24 & clocked_valid_pulse |
2967 eq_state_select_25 & clocked_valid_pulse |
2968 eq_state_select_26 & clocked_valid_pulse |
2969 eq_state_select_27 & clocked_valid_pulse |
2970 eq_state_select_28 & clocked_valid_pulse |
2971 eq_state_select_29 & clocked_valid_pulse |
2972 eq_state_select_30 & clocked_valid_pulse |
2973 eq_state_select_31 & clocked_valid_pulse |
2974 eq_state_select_32 & clocked_valid_pulse |
2975 eq_state_select_33 & clocked_valid_pulse |
2976 eq_state_select_34 & clocked_valid_pulse |
2977 eq_state_select_35 & clocked_valid_pulse;
2978 end
2979 if(~rst_l)
2980 begin
2981 stage_2_daemon_csrbus_done_internal_0 <= 1'b0;
2982 end
2983 else
2984 begin
2985 stage_2_daemon_csrbus_done_internal_0 <=
2986 stage_1_daemon_csrbus_done_internal_0 |
2987 stage_1_daemon_csrbus_done_internal_1;
2988 end
2989 end
2990
2991//----- OUTPUT: daemon_csrbus_done
2992assign daemon_csrbus_done = daemon_csrbus_valid &
2993 (
2994 stage_2_daemon_csrbus_done_internal_0
2995 );
2996
2997// daemon_csrbus_done gets asserted only when csrbus_valid is high
2998/* 0in assert -name daemon_csrbus_done_high
2999 -var daemon_csrbus_valid -active daemon_csrbus_done
3000 -message "csrbus_done got asserted while csrbus_valid is low"
3001 -module dmu_imu_eqs_addr_decode
3002 -clock clk
3003*/
3004
3005// daemon_csrbus_done is a pulse
3006/* 0in assert_timer -name daemon_csrbus_done_pulse
3007 -var daemon_csrbus_done -max 1
3008 -message "csrbus_done pulse length is not 1"
3009 -module dmu_imu_eqs_addr_decode
3010 -clock clk
3011*/
3012
3013endmodule // dmu_imu_eqs_addr_decode
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