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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_eqs_csr_eq_tail.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_eqs_csr_eq_tail.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_eqs_csr_eq_tail
36 (
37 clk,
38 rst_l,
39 eq_tail_w_ld_0,
40 eq_tail_w_ld_1,
41 eq_tail_w_ld_2,
42 eq_tail_w_ld_3,
43 eq_tail_w_ld_4,
44 eq_tail_w_ld_5,
45 eq_tail_w_ld_6,
46 eq_tail_w_ld_7,
47 eq_tail_w_ld_8,
48 eq_tail_w_ld_9,
49 eq_tail_w_ld_10,
50 eq_tail_w_ld_11,
51 eq_tail_w_ld_12,
52 eq_tail_w_ld_13,
53 eq_tail_w_ld_14,
54 eq_tail_w_ld_15,
55 eq_tail_w_ld_16,
56 eq_tail_w_ld_17,
57 eq_tail_w_ld_18,
58 eq_tail_w_ld_19,
59 eq_tail_w_ld_20,
60 eq_tail_w_ld_21,
61 eq_tail_w_ld_22,
62 eq_tail_w_ld_23,
63 eq_tail_w_ld_24,
64 eq_tail_w_ld_25,
65 eq_tail_w_ld_26,
66 eq_tail_w_ld_27,
67 eq_tail_w_ld_28,
68 eq_tail_w_ld_29,
69 eq_tail_w_ld_30,
70 eq_tail_w_ld_31,
71 eq_tail_w_ld_32,
72 eq_tail_w_ld_33,
73 eq_tail_w_ld_34,
74 eq_tail_w_ld_35,
75 csrbus_wr_data,
76 eq_tail_csrbus_read_data_0,
77 eq_tail_csrbus_read_data_1,
78 eq_tail_csrbus_read_data_2,
79 eq_tail_csrbus_read_data_3,
80 eq_tail_csrbus_read_data_4,
81 eq_tail_csrbus_read_data_5,
82 eq_tail_csrbus_read_data_6,
83 eq_tail_csrbus_read_data_7,
84 eq_tail_csrbus_read_data_8,
85 eq_tail_csrbus_read_data_9,
86 eq_tail_csrbus_read_data_10,
87 eq_tail_csrbus_read_data_11,
88 eq_tail_csrbus_read_data_12,
89 eq_tail_csrbus_read_data_13,
90 eq_tail_csrbus_read_data_14,
91 eq_tail_csrbus_read_data_15,
92 eq_tail_csrbus_read_data_16,
93 eq_tail_csrbus_read_data_17,
94 eq_tail_csrbus_read_data_18,
95 eq_tail_csrbus_read_data_19,
96 eq_tail_csrbus_read_data_20,
97 eq_tail_csrbus_read_data_21,
98 eq_tail_csrbus_read_data_22,
99 eq_tail_csrbus_read_data_23,
100 eq_tail_csrbus_read_data_24,
101 eq_tail_csrbus_read_data_25,
102 eq_tail_csrbus_read_data_26,
103 eq_tail_csrbus_read_data_27,
104 eq_tail_csrbus_read_data_28,
105 eq_tail_csrbus_read_data_29,
106 eq_tail_csrbus_read_data_30,
107 eq_tail_csrbus_read_data_31,
108 eq_tail_csrbus_read_data_32,
109 eq_tail_csrbus_read_data_33,
110 eq_tail_csrbus_read_data_34,
111 eq_tail_csrbus_read_data_35,
112 eq_tail_overr_hw_ld_0,
113 eq_tail_overr_hw_ld_1,
114 eq_tail_overr_hw_ld_2,
115 eq_tail_overr_hw_ld_3,
116 eq_tail_overr_hw_ld_4,
117 eq_tail_overr_hw_ld_5,
118 eq_tail_overr_hw_ld_6,
119 eq_tail_overr_hw_ld_7,
120 eq_tail_overr_hw_ld_8,
121 eq_tail_overr_hw_ld_9,
122 eq_tail_overr_hw_ld_10,
123 eq_tail_overr_hw_ld_11,
124 eq_tail_overr_hw_ld_12,
125 eq_tail_overr_hw_ld_13,
126 eq_tail_overr_hw_ld_14,
127 eq_tail_overr_hw_ld_15,
128 eq_tail_overr_hw_ld_16,
129 eq_tail_overr_hw_ld_17,
130 eq_tail_overr_hw_ld_18,
131 eq_tail_overr_hw_ld_19,
132 eq_tail_overr_hw_ld_20,
133 eq_tail_overr_hw_ld_21,
134 eq_tail_overr_hw_ld_22,
135 eq_tail_overr_hw_ld_23,
136 eq_tail_overr_hw_ld_24,
137 eq_tail_overr_hw_ld_25,
138 eq_tail_overr_hw_ld_26,
139 eq_tail_overr_hw_ld_27,
140 eq_tail_overr_hw_ld_28,
141 eq_tail_overr_hw_ld_29,
142 eq_tail_overr_hw_ld_30,
143 eq_tail_overr_hw_ld_31,
144 eq_tail_overr_hw_ld_32,
145 eq_tail_overr_hw_ld_33,
146 eq_tail_overr_hw_ld_34,
147 eq_tail_overr_hw_ld_35,
148 eq_tail_overr_hw_write_0,
149 eq_tail_overr_hw_write_1,
150 eq_tail_overr_hw_write_2,
151 eq_tail_overr_hw_write_3,
152 eq_tail_overr_hw_write_4,
153 eq_tail_overr_hw_write_5,
154 eq_tail_overr_hw_write_6,
155 eq_tail_overr_hw_write_7,
156 eq_tail_overr_hw_write_8,
157 eq_tail_overr_hw_write_9,
158 eq_tail_overr_hw_write_10,
159 eq_tail_overr_hw_write_11,
160 eq_tail_overr_hw_write_12,
161 eq_tail_overr_hw_write_13,
162 eq_tail_overr_hw_write_14,
163 eq_tail_overr_hw_write_15,
164 eq_tail_overr_hw_write_16,
165 eq_tail_overr_hw_write_17,
166 eq_tail_overr_hw_write_18,
167 eq_tail_overr_hw_write_19,
168 eq_tail_overr_hw_write_20,
169 eq_tail_overr_hw_write_21,
170 eq_tail_overr_hw_write_22,
171 eq_tail_overr_hw_write_23,
172 eq_tail_overr_hw_write_24,
173 eq_tail_overr_hw_write_25,
174 eq_tail_overr_hw_write_26,
175 eq_tail_overr_hw_write_27,
176 eq_tail_overr_hw_write_28,
177 eq_tail_overr_hw_write_29,
178 eq_tail_overr_hw_write_30,
179 eq_tail_overr_hw_write_31,
180 eq_tail_overr_hw_write_32,
181 eq_tail_overr_hw_write_33,
182 eq_tail_overr_hw_write_34,
183 eq_tail_overr_hw_write_35,
184 eq_tail_tail_hw_ld_0,
185 eq_tail_tail_hw_ld_1,
186 eq_tail_tail_hw_ld_2,
187 eq_tail_tail_hw_ld_3,
188 eq_tail_tail_hw_ld_4,
189 eq_tail_tail_hw_ld_5,
190 eq_tail_tail_hw_ld_6,
191 eq_tail_tail_hw_ld_7,
192 eq_tail_tail_hw_ld_8,
193 eq_tail_tail_hw_ld_9,
194 eq_tail_tail_hw_ld_10,
195 eq_tail_tail_hw_ld_11,
196 eq_tail_tail_hw_ld_12,
197 eq_tail_tail_hw_ld_13,
198 eq_tail_tail_hw_ld_14,
199 eq_tail_tail_hw_ld_15,
200 eq_tail_tail_hw_ld_16,
201 eq_tail_tail_hw_ld_17,
202 eq_tail_tail_hw_ld_18,
203 eq_tail_tail_hw_ld_19,
204 eq_tail_tail_hw_ld_20,
205 eq_tail_tail_hw_ld_21,
206 eq_tail_tail_hw_ld_22,
207 eq_tail_tail_hw_ld_23,
208 eq_tail_tail_hw_ld_24,
209 eq_tail_tail_hw_ld_25,
210 eq_tail_tail_hw_ld_26,
211 eq_tail_tail_hw_ld_27,
212 eq_tail_tail_hw_ld_28,
213 eq_tail_tail_hw_ld_29,
214 eq_tail_tail_hw_ld_30,
215 eq_tail_tail_hw_ld_31,
216 eq_tail_tail_hw_ld_32,
217 eq_tail_tail_hw_ld_33,
218 eq_tail_tail_hw_ld_34,
219 eq_tail_tail_hw_ld_35,
220 eq_tail_tail_hw_write_0,
221 eq_tail_tail_hw_write_1,
222 eq_tail_tail_hw_write_2,
223 eq_tail_tail_hw_write_3,
224 eq_tail_tail_hw_write_4,
225 eq_tail_tail_hw_write_5,
226 eq_tail_tail_hw_write_6,
227 eq_tail_tail_hw_write_7,
228 eq_tail_tail_hw_write_8,
229 eq_tail_tail_hw_write_9,
230 eq_tail_tail_hw_write_10,
231 eq_tail_tail_hw_write_11,
232 eq_tail_tail_hw_write_12,
233 eq_tail_tail_hw_write_13,
234 eq_tail_tail_hw_write_14,
235 eq_tail_tail_hw_write_15,
236 eq_tail_tail_hw_write_16,
237 eq_tail_tail_hw_write_17,
238 eq_tail_tail_hw_write_18,
239 eq_tail_tail_hw_write_19,
240 eq_tail_tail_hw_write_20,
241 eq_tail_tail_hw_write_21,
242 eq_tail_tail_hw_write_22,
243 eq_tail_tail_hw_write_23,
244 eq_tail_tail_hw_write_24,
245 eq_tail_tail_hw_write_25,
246 eq_tail_tail_hw_write_26,
247 eq_tail_tail_hw_write_27,
248 eq_tail_tail_hw_write_28,
249 eq_tail_tail_hw_write_29,
250 eq_tail_tail_hw_write_30,
251 eq_tail_tail_hw_write_31,
252 eq_tail_tail_hw_write_32,
253 eq_tail_tail_hw_write_33,
254 eq_tail_tail_hw_write_34,
255 eq_tail_tail_hw_write_35,
256 eq_tail_tail_hw_read_0,
257 eq_tail_tail_hw_read_1,
258 eq_tail_tail_hw_read_2,
259 eq_tail_tail_hw_read_3,
260 eq_tail_tail_hw_read_4,
261 eq_tail_tail_hw_read_5,
262 eq_tail_tail_hw_read_6,
263 eq_tail_tail_hw_read_7,
264 eq_tail_tail_hw_read_8,
265 eq_tail_tail_hw_read_9,
266 eq_tail_tail_hw_read_10,
267 eq_tail_tail_hw_read_11,
268 eq_tail_tail_hw_read_12,
269 eq_tail_tail_hw_read_13,
270 eq_tail_tail_hw_read_14,
271 eq_tail_tail_hw_read_15,
272 eq_tail_tail_hw_read_16,
273 eq_tail_tail_hw_read_17,
274 eq_tail_tail_hw_read_18,
275 eq_tail_tail_hw_read_19,
276 eq_tail_tail_hw_read_20,
277 eq_tail_tail_hw_read_21,
278 eq_tail_tail_hw_read_22,
279 eq_tail_tail_hw_read_23,
280 eq_tail_tail_hw_read_24,
281 eq_tail_tail_hw_read_25,
282 eq_tail_tail_hw_read_26,
283 eq_tail_tail_hw_read_27,
284 eq_tail_tail_hw_read_28,
285 eq_tail_tail_hw_read_29,
286 eq_tail_tail_hw_read_30,
287 eq_tail_tail_hw_read_31,
288 eq_tail_tail_hw_read_32,
289 eq_tail_tail_hw_read_33,
290 eq_tail_tail_hw_read_34,
291 eq_tail_tail_hw_read_35
292 );
293
294//====================================================================
295// Polarity declarations
296//====================================================================
297input clk; // Clock
298input rst_l; // Reset signal
299input eq_tail_w_ld_0; // SW load bus
300input eq_tail_w_ld_1; // SW load bus
301input eq_tail_w_ld_2; // SW load bus
302input eq_tail_w_ld_3; // SW load bus
303input eq_tail_w_ld_4; // SW load bus
304input eq_tail_w_ld_5; // SW load bus
305input eq_tail_w_ld_6; // SW load bus
306input eq_tail_w_ld_7; // SW load bus
307input eq_tail_w_ld_8; // SW load bus
308input eq_tail_w_ld_9; // SW load bus
309input eq_tail_w_ld_10; // SW load bus
310input eq_tail_w_ld_11; // SW load bus
311input eq_tail_w_ld_12; // SW load bus
312input eq_tail_w_ld_13; // SW load bus
313input eq_tail_w_ld_14; // SW load bus
314input eq_tail_w_ld_15; // SW load bus
315input eq_tail_w_ld_16; // SW load bus
316input eq_tail_w_ld_17; // SW load bus
317input eq_tail_w_ld_18; // SW load bus
318input eq_tail_w_ld_19; // SW load bus
319input eq_tail_w_ld_20; // SW load bus
320input eq_tail_w_ld_21; // SW load bus
321input eq_tail_w_ld_22; // SW load bus
322input eq_tail_w_ld_23; // SW load bus
323input eq_tail_w_ld_24; // SW load bus
324input eq_tail_w_ld_25; // SW load bus
325input eq_tail_w_ld_26; // SW load bus
326input eq_tail_w_ld_27; // SW load bus
327input eq_tail_w_ld_28; // SW load bus
328input eq_tail_w_ld_29; // SW load bus
329input eq_tail_w_ld_30; // SW load bus
330input eq_tail_w_ld_31; // SW load bus
331input eq_tail_w_ld_32; // SW load bus
332input eq_tail_w_ld_33; // SW load bus
333input eq_tail_w_ld_34; // SW load bus
334input eq_tail_w_ld_35; // SW load bus
335input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
336output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_0;
337 // SW read data
338output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_1;
339 // SW read data
340output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_2;
341 // SW read data
342output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_3;
343 // SW read data
344output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_4;
345 // SW read data
346output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_5;
347 // SW read data
348output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_6;
349 // SW read data
350output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_7;
351 // SW read data
352output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_8;
353 // SW read data
354output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_9;
355 // SW read data
356output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_10;
357 // SW read data
358output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_11;
359 // SW read data
360output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_12;
361 // SW read data
362output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_13;
363 // SW read data
364output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_14;
365 // SW read data
366output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_15;
367 // SW read data
368output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_16;
369 // SW read data
370output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_17;
371 // SW read data
372output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_18;
373 // SW read data
374output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_19;
375 // SW read data
376output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_20;
377 // SW read data
378output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_21;
379 // SW read data
380output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_22;
381 // SW read data
382output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_23;
383 // SW read data
384output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_24;
385 // SW read data
386output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_25;
387 // SW read data
388output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_26;
389 // SW read data
390output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_27;
391 // SW read data
392output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_28;
393 // SW read data
394output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_29;
395 // SW read data
396output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_30;
397 // SW read data
398output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_31;
399 // SW read data
400output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_32;
401 // SW read data
402output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_33;
403 // SW read data
404output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_34;
405 // SW read data
406output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_35;
407 // SW read data
408input eq_tail_overr_hw_ld_0; // Hardware load enable for eq_tail_overr. When
409 // set, <hw write signal> will be loaded into
410 // eq_tail.
411input eq_tail_overr_hw_ld_1; // Hardware load enable for eq_tail_overr. When
412 // set, <hw write signal> will be loaded into
413 // eq_tail.
414input eq_tail_overr_hw_ld_2; // Hardware load enable for eq_tail_overr. When
415 // set, <hw write signal> will be loaded into
416 // eq_tail.
417input eq_tail_overr_hw_ld_3; // Hardware load enable for eq_tail_overr. When
418 // set, <hw write signal> will be loaded into
419 // eq_tail.
420input eq_tail_overr_hw_ld_4; // Hardware load enable for eq_tail_overr. When
421 // set, <hw write signal> will be loaded into
422 // eq_tail.
423input eq_tail_overr_hw_ld_5; // Hardware load enable for eq_tail_overr. When
424 // set, <hw write signal> will be loaded into
425 // eq_tail.
426input eq_tail_overr_hw_ld_6; // Hardware load enable for eq_tail_overr. When
427 // set, <hw write signal> will be loaded into
428 // eq_tail.
429input eq_tail_overr_hw_ld_7; // Hardware load enable for eq_tail_overr. When
430 // set, <hw write signal> will be loaded into
431 // eq_tail.
432input eq_tail_overr_hw_ld_8; // Hardware load enable for eq_tail_overr. When
433 // set, <hw write signal> will be loaded into
434 // eq_tail.
435input eq_tail_overr_hw_ld_9; // Hardware load enable for eq_tail_overr. When
436 // set, <hw write signal> will be loaded into
437 // eq_tail.
438input eq_tail_overr_hw_ld_10; // Hardware load enable for eq_tail_overr. When
439 // set, <hw write signal> will be loaded into
440 // eq_tail.
441input eq_tail_overr_hw_ld_11; // Hardware load enable for eq_tail_overr. When
442 // set, <hw write signal> will be loaded into
443 // eq_tail.
444input eq_tail_overr_hw_ld_12; // Hardware load enable for eq_tail_overr. When
445 // set, <hw write signal> will be loaded into
446 // eq_tail.
447input eq_tail_overr_hw_ld_13; // Hardware load enable for eq_tail_overr. When
448 // set, <hw write signal> will be loaded into
449 // eq_tail.
450input eq_tail_overr_hw_ld_14; // Hardware load enable for eq_tail_overr. When
451 // set, <hw write signal> will be loaded into
452 // eq_tail.
453input eq_tail_overr_hw_ld_15; // Hardware load enable for eq_tail_overr. When
454 // set, <hw write signal> will be loaded into
455 // eq_tail.
456input eq_tail_overr_hw_ld_16; // Hardware load enable for eq_tail_overr. When
457 // set, <hw write signal> will be loaded into
458 // eq_tail.
459input eq_tail_overr_hw_ld_17; // Hardware load enable for eq_tail_overr. When
460 // set, <hw write signal> will be loaded into
461 // eq_tail.
462input eq_tail_overr_hw_ld_18; // Hardware load enable for eq_tail_overr. When
463 // set, <hw write signal> will be loaded into
464 // eq_tail.
465input eq_tail_overr_hw_ld_19; // Hardware load enable for eq_tail_overr. When
466 // set, <hw write signal> will be loaded into
467 // eq_tail.
468input eq_tail_overr_hw_ld_20; // Hardware load enable for eq_tail_overr. When
469 // set, <hw write signal> will be loaded into
470 // eq_tail.
471input eq_tail_overr_hw_ld_21; // Hardware load enable for eq_tail_overr. When
472 // set, <hw write signal> will be loaded into
473 // eq_tail.
474input eq_tail_overr_hw_ld_22; // Hardware load enable for eq_tail_overr. When
475 // set, <hw write signal> will be loaded into
476 // eq_tail.
477input eq_tail_overr_hw_ld_23; // Hardware load enable for eq_tail_overr. When
478 // set, <hw write signal> will be loaded into
479 // eq_tail.
480input eq_tail_overr_hw_ld_24; // Hardware load enable for eq_tail_overr. When
481 // set, <hw write signal> will be loaded into
482 // eq_tail.
483input eq_tail_overr_hw_ld_25; // Hardware load enable for eq_tail_overr. When
484 // set, <hw write signal> will be loaded into
485 // eq_tail.
486input eq_tail_overr_hw_ld_26; // Hardware load enable for eq_tail_overr. When
487 // set, <hw write signal> will be loaded into
488 // eq_tail.
489input eq_tail_overr_hw_ld_27; // Hardware load enable for eq_tail_overr. When
490 // set, <hw write signal> will be loaded into
491 // eq_tail.
492input eq_tail_overr_hw_ld_28; // Hardware load enable for eq_tail_overr. When
493 // set, <hw write signal> will be loaded into
494 // eq_tail.
495input eq_tail_overr_hw_ld_29; // Hardware load enable for eq_tail_overr. When
496 // set, <hw write signal> will be loaded into
497 // eq_tail.
498input eq_tail_overr_hw_ld_30; // Hardware load enable for eq_tail_overr. When
499 // set, <hw write signal> will be loaded into
500 // eq_tail.
501input eq_tail_overr_hw_ld_31; // Hardware load enable for eq_tail_overr. When
502 // set, <hw write signal> will be loaded into
503 // eq_tail.
504input eq_tail_overr_hw_ld_32; // Hardware load enable for eq_tail_overr. When
505 // set, <hw write signal> will be loaded into
506 // eq_tail.
507input eq_tail_overr_hw_ld_33; // Hardware load enable for eq_tail_overr. When
508 // set, <hw write signal> will be loaded into
509 // eq_tail.
510input eq_tail_overr_hw_ld_34; // Hardware load enable for eq_tail_overr. When
511 // set, <hw write signal> will be loaded into
512 // eq_tail.
513input eq_tail_overr_hw_ld_35; // Hardware load enable for eq_tail_overr. When
514 // set, <hw write signal> will be loaded into
515 // eq_tail.
516input eq_tail_overr_hw_write_0; // data bus for hw loading of eq_tail_overr.
517input eq_tail_overr_hw_write_1; // data bus for hw loading of eq_tail_overr.
518input eq_tail_overr_hw_write_2; // data bus for hw loading of eq_tail_overr.
519input eq_tail_overr_hw_write_3; // data bus for hw loading of eq_tail_overr.
520input eq_tail_overr_hw_write_4; // data bus for hw loading of eq_tail_overr.
521input eq_tail_overr_hw_write_5; // data bus for hw loading of eq_tail_overr.
522input eq_tail_overr_hw_write_6; // data bus for hw loading of eq_tail_overr.
523input eq_tail_overr_hw_write_7; // data bus for hw loading of eq_tail_overr.
524input eq_tail_overr_hw_write_8; // data bus for hw loading of eq_tail_overr.
525input eq_tail_overr_hw_write_9; // data bus for hw loading of eq_tail_overr.
526input eq_tail_overr_hw_write_10; // data bus for hw loading of eq_tail_overr.
527input eq_tail_overr_hw_write_11; // data bus for hw loading of eq_tail_overr.
528input eq_tail_overr_hw_write_12; // data bus for hw loading of eq_tail_overr.
529input eq_tail_overr_hw_write_13; // data bus for hw loading of eq_tail_overr.
530input eq_tail_overr_hw_write_14; // data bus for hw loading of eq_tail_overr.
531input eq_tail_overr_hw_write_15; // data bus for hw loading of eq_tail_overr.
532input eq_tail_overr_hw_write_16; // data bus for hw loading of eq_tail_overr.
533input eq_tail_overr_hw_write_17; // data bus for hw loading of eq_tail_overr.
534input eq_tail_overr_hw_write_18; // data bus for hw loading of eq_tail_overr.
535input eq_tail_overr_hw_write_19; // data bus for hw loading of eq_tail_overr.
536input eq_tail_overr_hw_write_20; // data bus for hw loading of eq_tail_overr.
537input eq_tail_overr_hw_write_21; // data bus for hw loading of eq_tail_overr.
538input eq_tail_overr_hw_write_22; // data bus for hw loading of eq_tail_overr.
539input eq_tail_overr_hw_write_23; // data bus for hw loading of eq_tail_overr.
540input eq_tail_overr_hw_write_24; // data bus for hw loading of eq_tail_overr.
541input eq_tail_overr_hw_write_25; // data bus for hw loading of eq_tail_overr.
542input eq_tail_overr_hw_write_26; // data bus for hw loading of eq_tail_overr.
543input eq_tail_overr_hw_write_27; // data bus for hw loading of eq_tail_overr.
544input eq_tail_overr_hw_write_28; // data bus for hw loading of eq_tail_overr.
545input eq_tail_overr_hw_write_29; // data bus for hw loading of eq_tail_overr.
546input eq_tail_overr_hw_write_30; // data bus for hw loading of eq_tail_overr.
547input eq_tail_overr_hw_write_31; // data bus for hw loading of eq_tail_overr.
548input eq_tail_overr_hw_write_32; // data bus for hw loading of eq_tail_overr.
549input eq_tail_overr_hw_write_33; // data bus for hw loading of eq_tail_overr.
550input eq_tail_overr_hw_write_34; // data bus for hw loading of eq_tail_overr.
551input eq_tail_overr_hw_write_35; // data bus for hw loading of eq_tail_overr.
552input eq_tail_tail_hw_ld_0; // Hardware load enable for eq_tail_tail. When
553 // set, <hw write signal> will be loaded into
554 // eq_tail.
555input eq_tail_tail_hw_ld_1; // Hardware load enable for eq_tail_tail. When
556 // set, <hw write signal> will be loaded into
557 // eq_tail.
558input eq_tail_tail_hw_ld_2; // Hardware load enable for eq_tail_tail. When
559 // set, <hw write signal> will be loaded into
560 // eq_tail.
561input eq_tail_tail_hw_ld_3; // Hardware load enable for eq_tail_tail. When
562 // set, <hw write signal> will be loaded into
563 // eq_tail.
564input eq_tail_tail_hw_ld_4; // Hardware load enable for eq_tail_tail. When
565 // set, <hw write signal> will be loaded into
566 // eq_tail.
567input eq_tail_tail_hw_ld_5; // Hardware load enable for eq_tail_tail. When
568 // set, <hw write signal> will be loaded into
569 // eq_tail.
570input eq_tail_tail_hw_ld_6; // Hardware load enable for eq_tail_tail. When
571 // set, <hw write signal> will be loaded into
572 // eq_tail.
573input eq_tail_tail_hw_ld_7; // Hardware load enable for eq_tail_tail. When
574 // set, <hw write signal> will be loaded into
575 // eq_tail.
576input eq_tail_tail_hw_ld_8; // Hardware load enable for eq_tail_tail. When
577 // set, <hw write signal> will be loaded into
578 // eq_tail.
579input eq_tail_tail_hw_ld_9; // Hardware load enable for eq_tail_tail. When
580 // set, <hw write signal> will be loaded into
581 // eq_tail.
582input eq_tail_tail_hw_ld_10; // Hardware load enable for eq_tail_tail. When
583 // set, <hw write signal> will be loaded into
584 // eq_tail.
585input eq_tail_tail_hw_ld_11; // Hardware load enable for eq_tail_tail. When
586 // set, <hw write signal> will be loaded into
587 // eq_tail.
588input eq_tail_tail_hw_ld_12; // Hardware load enable for eq_tail_tail. When
589 // set, <hw write signal> will be loaded into
590 // eq_tail.
591input eq_tail_tail_hw_ld_13; // Hardware load enable for eq_tail_tail. When
592 // set, <hw write signal> will be loaded into
593 // eq_tail.
594input eq_tail_tail_hw_ld_14; // Hardware load enable for eq_tail_tail. When
595 // set, <hw write signal> will be loaded into
596 // eq_tail.
597input eq_tail_tail_hw_ld_15; // Hardware load enable for eq_tail_tail. When
598 // set, <hw write signal> will be loaded into
599 // eq_tail.
600input eq_tail_tail_hw_ld_16; // Hardware load enable for eq_tail_tail. When
601 // set, <hw write signal> will be loaded into
602 // eq_tail.
603input eq_tail_tail_hw_ld_17; // Hardware load enable for eq_tail_tail. When
604 // set, <hw write signal> will be loaded into
605 // eq_tail.
606input eq_tail_tail_hw_ld_18; // Hardware load enable for eq_tail_tail. When
607 // set, <hw write signal> will be loaded into
608 // eq_tail.
609input eq_tail_tail_hw_ld_19; // Hardware load enable for eq_tail_tail. When
610 // set, <hw write signal> will be loaded into
611 // eq_tail.
612input eq_tail_tail_hw_ld_20; // Hardware load enable for eq_tail_tail. When
613 // set, <hw write signal> will be loaded into
614 // eq_tail.
615input eq_tail_tail_hw_ld_21; // Hardware load enable for eq_tail_tail. When
616 // set, <hw write signal> will be loaded into
617 // eq_tail.
618input eq_tail_tail_hw_ld_22; // Hardware load enable for eq_tail_tail. When
619 // set, <hw write signal> will be loaded into
620 // eq_tail.
621input eq_tail_tail_hw_ld_23; // Hardware load enable for eq_tail_tail. When
622 // set, <hw write signal> will be loaded into
623 // eq_tail.
624input eq_tail_tail_hw_ld_24; // Hardware load enable for eq_tail_tail. When
625 // set, <hw write signal> will be loaded into
626 // eq_tail.
627input eq_tail_tail_hw_ld_25; // Hardware load enable for eq_tail_tail. When
628 // set, <hw write signal> will be loaded into
629 // eq_tail.
630input eq_tail_tail_hw_ld_26; // Hardware load enable for eq_tail_tail. When
631 // set, <hw write signal> will be loaded into
632 // eq_tail.
633input eq_tail_tail_hw_ld_27; // Hardware load enable for eq_tail_tail. When
634 // set, <hw write signal> will be loaded into
635 // eq_tail.
636input eq_tail_tail_hw_ld_28; // Hardware load enable for eq_tail_tail. When
637 // set, <hw write signal> will be loaded into
638 // eq_tail.
639input eq_tail_tail_hw_ld_29; // Hardware load enable for eq_tail_tail. When
640 // set, <hw write signal> will be loaded into
641 // eq_tail.
642input eq_tail_tail_hw_ld_30; // Hardware load enable for eq_tail_tail. When
643 // set, <hw write signal> will be loaded into
644 // eq_tail.
645input eq_tail_tail_hw_ld_31; // Hardware load enable for eq_tail_tail. When
646 // set, <hw write signal> will be loaded into
647 // eq_tail.
648input eq_tail_tail_hw_ld_32; // Hardware load enable for eq_tail_tail. When
649 // set, <hw write signal> will be loaded into
650 // eq_tail.
651input eq_tail_tail_hw_ld_33; // Hardware load enable for eq_tail_tail. When
652 // set, <hw write signal> will be loaded into
653 // eq_tail.
654input eq_tail_tail_hw_ld_34; // Hardware load enable for eq_tail_tail. When
655 // set, <hw write signal> will be loaded into
656 // eq_tail.
657input eq_tail_tail_hw_ld_35; // Hardware load enable for eq_tail_tail. When
658 // set, <hw write signal> will be loaded into
659 // eq_tail.
660input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_0;
661 // data bus for hw loading of eq_tail_tail.
662input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_1;
663 // data bus for hw loading of eq_tail_tail.
664input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_2;
665 // data bus for hw loading of eq_tail_tail.
666input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_3;
667 // data bus for hw loading of eq_tail_tail.
668input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_4;
669 // data bus for hw loading of eq_tail_tail.
670input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_5;
671 // data bus for hw loading of eq_tail_tail.
672input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_6;
673 // data bus for hw loading of eq_tail_tail.
674input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_7;
675 // data bus for hw loading of eq_tail_tail.
676input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_8;
677 // data bus for hw loading of eq_tail_tail.
678input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_9;
679 // data bus for hw loading of eq_tail_tail.
680input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_10;
681 // data bus for hw loading of eq_tail_tail.
682input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_11;
683 // data bus for hw loading of eq_tail_tail.
684input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_12;
685 // data bus for hw loading of eq_tail_tail.
686input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_13;
687 // data bus for hw loading of eq_tail_tail.
688input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_14;
689 // data bus for hw loading of eq_tail_tail.
690input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_15;
691 // data bus for hw loading of eq_tail_tail.
692input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_16;
693 // data bus for hw loading of eq_tail_tail.
694input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_17;
695 // data bus for hw loading of eq_tail_tail.
696input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_18;
697 // data bus for hw loading of eq_tail_tail.
698input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_19;
699 // data bus for hw loading of eq_tail_tail.
700input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_20;
701 // data bus for hw loading of eq_tail_tail.
702input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_21;
703 // data bus for hw loading of eq_tail_tail.
704input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_22;
705 // data bus for hw loading of eq_tail_tail.
706input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_23;
707 // data bus for hw loading of eq_tail_tail.
708input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_24;
709 // data bus for hw loading of eq_tail_tail.
710input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_25;
711 // data bus for hw loading of eq_tail_tail.
712input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_26;
713 // data bus for hw loading of eq_tail_tail.
714input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_27;
715 // data bus for hw loading of eq_tail_tail.
716input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_28;
717 // data bus for hw loading of eq_tail_tail.
718input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_29;
719 // data bus for hw loading of eq_tail_tail.
720input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_30;
721 // data bus for hw loading of eq_tail_tail.
722input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_31;
723 // data bus for hw loading of eq_tail_tail.
724input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_32;
725 // data bus for hw loading of eq_tail_tail.
726input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_33;
727 // data bus for hw loading of eq_tail_tail.
728input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_34;
729 // data bus for hw loading of eq_tail_tail.
730input [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_35;
731 // data bus for hw loading of eq_tail_tail.
732output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_0;
733 // This signal provides the current value of eq_tail_tail.
734output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_1;
735 // This signal provides the current value of eq_tail_tail.
736output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_2;
737 // This signal provides the current value of eq_tail_tail.
738output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_3;
739 // This signal provides the current value of eq_tail_tail.
740output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_4;
741 // This signal provides the current value of eq_tail_tail.
742output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_5;
743 // This signal provides the current value of eq_tail_tail.
744output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_6;
745 // This signal provides the current value of eq_tail_tail.
746output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_7;
747 // This signal provides the current value of eq_tail_tail.
748output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_8;
749 // This signal provides the current value of eq_tail_tail.
750output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_9;
751 // This signal provides the current value of eq_tail_tail.
752output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_10;
753 // This signal provides the current value of eq_tail_tail.
754output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_11;
755 // This signal provides the current value of eq_tail_tail.
756output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_12;
757 // This signal provides the current value of eq_tail_tail.
758output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_13;
759 // This signal provides the current value of eq_tail_tail.
760output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_14;
761 // This signal provides the current value of eq_tail_tail.
762output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_15;
763 // This signal provides the current value of eq_tail_tail.
764output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_16;
765 // This signal provides the current value of eq_tail_tail.
766output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_17;
767 // This signal provides the current value of eq_tail_tail.
768output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_18;
769 // This signal provides the current value of eq_tail_tail.
770output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_19;
771 // This signal provides the current value of eq_tail_tail.
772output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_20;
773 // This signal provides the current value of eq_tail_tail.
774output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_21;
775 // This signal provides the current value of eq_tail_tail.
776output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_22;
777 // This signal provides the current value of eq_tail_tail.
778output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_23;
779 // This signal provides the current value of eq_tail_tail.
780output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_24;
781 // This signal provides the current value of eq_tail_tail.
782output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_25;
783 // This signal provides the current value of eq_tail_tail.
784output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_26;
785 // This signal provides the current value of eq_tail_tail.
786output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_27;
787 // This signal provides the current value of eq_tail_tail.
788output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_28;
789 // This signal provides the current value of eq_tail_tail.
790output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_29;
791 // This signal provides the current value of eq_tail_tail.
792output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_30;
793 // This signal provides the current value of eq_tail_tail.
794output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_31;
795 // This signal provides the current value of eq_tail_tail.
796output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_32;
797 // This signal provides the current value of eq_tail_tail.
798output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_33;
799 // This signal provides the current value of eq_tail_tail.
800output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_34;
801 // This signal provides the current value of eq_tail_tail.
802output [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_35;
803 // This signal provides the current value of eq_tail_tail.
804
805//====================================================================
806// Type declarations
807//====================================================================
808wire clk; // Clock
809wire rst_l; // Reset signal
810wire eq_tail_w_ld_0; // SW load bus
811wire eq_tail_w_ld_1; // SW load bus
812wire eq_tail_w_ld_2; // SW load bus
813wire eq_tail_w_ld_3; // SW load bus
814wire eq_tail_w_ld_4; // SW load bus
815wire eq_tail_w_ld_5; // SW load bus
816wire eq_tail_w_ld_6; // SW load bus
817wire eq_tail_w_ld_7; // SW load bus
818wire eq_tail_w_ld_8; // SW load bus
819wire eq_tail_w_ld_9; // SW load bus
820wire eq_tail_w_ld_10; // SW load bus
821wire eq_tail_w_ld_11; // SW load bus
822wire eq_tail_w_ld_12; // SW load bus
823wire eq_tail_w_ld_13; // SW load bus
824wire eq_tail_w_ld_14; // SW load bus
825wire eq_tail_w_ld_15; // SW load bus
826wire eq_tail_w_ld_16; // SW load bus
827wire eq_tail_w_ld_17; // SW load bus
828wire eq_tail_w_ld_18; // SW load bus
829wire eq_tail_w_ld_19; // SW load bus
830wire eq_tail_w_ld_20; // SW load bus
831wire eq_tail_w_ld_21; // SW load bus
832wire eq_tail_w_ld_22; // SW load bus
833wire eq_tail_w_ld_23; // SW load bus
834wire eq_tail_w_ld_24; // SW load bus
835wire eq_tail_w_ld_25; // SW load bus
836wire eq_tail_w_ld_26; // SW load bus
837wire eq_tail_w_ld_27; // SW load bus
838wire eq_tail_w_ld_28; // SW load bus
839wire eq_tail_w_ld_29; // SW load bus
840wire eq_tail_w_ld_30; // SW load bus
841wire eq_tail_w_ld_31; // SW load bus
842wire eq_tail_w_ld_32; // SW load bus
843wire eq_tail_w_ld_33; // SW load bus
844wire eq_tail_w_ld_34; // SW load bus
845wire eq_tail_w_ld_35; // SW load bus
846wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
847wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_0;
848 // SW read data
849wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_1;
850 // SW read data
851wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_2;
852 // SW read data
853wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_3;
854 // SW read data
855wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_4;
856 // SW read data
857wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_5;
858 // SW read data
859wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_6;
860 // SW read data
861wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_7;
862 // SW read data
863wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_8;
864 // SW read data
865wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_9;
866 // SW read data
867wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_10;
868 // SW read data
869wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_11;
870 // SW read data
871wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_12;
872 // SW read data
873wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_13;
874 // SW read data
875wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_14;
876 // SW read data
877wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_15;
878 // SW read data
879wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_16;
880 // SW read data
881wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_17;
882 // SW read data
883wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_18;
884 // SW read data
885wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_19;
886 // SW read data
887wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_20;
888 // SW read data
889wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_21;
890 // SW read data
891wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_22;
892 // SW read data
893wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_23;
894 // SW read data
895wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_24;
896 // SW read data
897wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_25;
898 // SW read data
899wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_26;
900 // SW read data
901wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_27;
902 // SW read data
903wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_28;
904 // SW read data
905wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_29;
906 // SW read data
907wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_30;
908 // SW read data
909wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_31;
910 // SW read data
911wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_32;
912 // SW read data
913wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_33;
914 // SW read data
915wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_34;
916 // SW read data
917wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] eq_tail_csrbus_read_data_35;
918 // SW read data
919wire eq_tail_overr_hw_ld_0; // Hardware load enable for eq_tail_overr. When
920 // set, <hw write signal> will be loaded into
921 // eq_tail.
922wire eq_tail_overr_hw_ld_1; // Hardware load enable for eq_tail_overr. When
923 // set, <hw write signal> will be loaded into
924 // eq_tail.
925wire eq_tail_overr_hw_ld_2; // Hardware load enable for eq_tail_overr. When
926 // set, <hw write signal> will be loaded into
927 // eq_tail.
928wire eq_tail_overr_hw_ld_3; // Hardware load enable for eq_tail_overr. When
929 // set, <hw write signal> will be loaded into
930 // eq_tail.
931wire eq_tail_overr_hw_ld_4; // Hardware load enable for eq_tail_overr. When
932 // set, <hw write signal> will be loaded into
933 // eq_tail.
934wire eq_tail_overr_hw_ld_5; // Hardware load enable for eq_tail_overr. When
935 // set, <hw write signal> will be loaded into
936 // eq_tail.
937wire eq_tail_overr_hw_ld_6; // Hardware load enable for eq_tail_overr. When
938 // set, <hw write signal> will be loaded into
939 // eq_tail.
940wire eq_tail_overr_hw_ld_7; // Hardware load enable for eq_tail_overr. When
941 // set, <hw write signal> will be loaded into
942 // eq_tail.
943wire eq_tail_overr_hw_ld_8; // Hardware load enable for eq_tail_overr. When
944 // set, <hw write signal> will be loaded into
945 // eq_tail.
946wire eq_tail_overr_hw_ld_9; // Hardware load enable for eq_tail_overr. When
947 // set, <hw write signal> will be loaded into
948 // eq_tail.
949wire eq_tail_overr_hw_ld_10; // Hardware load enable for eq_tail_overr. When
950 // set, <hw write signal> will be loaded into
951 // eq_tail.
952wire eq_tail_overr_hw_ld_11; // Hardware load enable for eq_tail_overr. When
953 // set, <hw write signal> will be loaded into
954 // eq_tail.
955wire eq_tail_overr_hw_ld_12; // Hardware load enable for eq_tail_overr. When
956 // set, <hw write signal> will be loaded into
957 // eq_tail.
958wire eq_tail_overr_hw_ld_13; // Hardware load enable for eq_tail_overr. When
959 // set, <hw write signal> will be loaded into
960 // eq_tail.
961wire eq_tail_overr_hw_ld_14; // Hardware load enable for eq_tail_overr. When
962 // set, <hw write signal> will be loaded into
963 // eq_tail.
964wire eq_tail_overr_hw_ld_15; // Hardware load enable for eq_tail_overr. When
965 // set, <hw write signal> will be loaded into
966 // eq_tail.
967wire eq_tail_overr_hw_ld_16; // Hardware load enable for eq_tail_overr. When
968 // set, <hw write signal> will be loaded into
969 // eq_tail.
970wire eq_tail_overr_hw_ld_17; // Hardware load enable for eq_tail_overr. When
971 // set, <hw write signal> will be loaded into
972 // eq_tail.
973wire eq_tail_overr_hw_ld_18; // Hardware load enable for eq_tail_overr. When
974 // set, <hw write signal> will be loaded into
975 // eq_tail.
976wire eq_tail_overr_hw_ld_19; // Hardware load enable for eq_tail_overr. When
977 // set, <hw write signal> will be loaded into
978 // eq_tail.
979wire eq_tail_overr_hw_ld_20; // Hardware load enable for eq_tail_overr. When
980 // set, <hw write signal> will be loaded into
981 // eq_tail.
982wire eq_tail_overr_hw_ld_21; // Hardware load enable for eq_tail_overr. When
983 // set, <hw write signal> will be loaded into
984 // eq_tail.
985wire eq_tail_overr_hw_ld_22; // Hardware load enable for eq_tail_overr. When
986 // set, <hw write signal> will be loaded into
987 // eq_tail.
988wire eq_tail_overr_hw_ld_23; // Hardware load enable for eq_tail_overr. When
989 // set, <hw write signal> will be loaded into
990 // eq_tail.
991wire eq_tail_overr_hw_ld_24; // Hardware load enable for eq_tail_overr. When
992 // set, <hw write signal> will be loaded into
993 // eq_tail.
994wire eq_tail_overr_hw_ld_25; // Hardware load enable for eq_tail_overr. When
995 // set, <hw write signal> will be loaded into
996 // eq_tail.
997wire eq_tail_overr_hw_ld_26; // Hardware load enable for eq_tail_overr. When
998 // set, <hw write signal> will be loaded into
999 // eq_tail.
1000wire eq_tail_overr_hw_ld_27; // Hardware load enable for eq_tail_overr. When
1001 // set, <hw write signal> will be loaded into
1002 // eq_tail.
1003wire eq_tail_overr_hw_ld_28; // Hardware load enable for eq_tail_overr. When
1004 // set, <hw write signal> will be loaded into
1005 // eq_tail.
1006wire eq_tail_overr_hw_ld_29; // Hardware load enable for eq_tail_overr. When
1007 // set, <hw write signal> will be loaded into
1008 // eq_tail.
1009wire eq_tail_overr_hw_ld_30; // Hardware load enable for eq_tail_overr. When
1010 // set, <hw write signal> will be loaded into
1011 // eq_tail.
1012wire eq_tail_overr_hw_ld_31; // Hardware load enable for eq_tail_overr. When
1013 // set, <hw write signal> will be loaded into
1014 // eq_tail.
1015wire eq_tail_overr_hw_ld_32; // Hardware load enable for eq_tail_overr. When
1016 // set, <hw write signal> will be loaded into
1017 // eq_tail.
1018wire eq_tail_overr_hw_ld_33; // Hardware load enable for eq_tail_overr. When
1019 // set, <hw write signal> will be loaded into
1020 // eq_tail.
1021wire eq_tail_overr_hw_ld_34; // Hardware load enable for eq_tail_overr. When
1022 // set, <hw write signal> will be loaded into
1023 // eq_tail.
1024wire eq_tail_overr_hw_ld_35; // Hardware load enable for eq_tail_overr. When
1025 // set, <hw write signal> will be loaded into
1026 // eq_tail.
1027wire eq_tail_overr_hw_write_0; // data bus for hw loading of eq_tail_overr.
1028wire eq_tail_overr_hw_write_1; // data bus for hw loading of eq_tail_overr.
1029wire eq_tail_overr_hw_write_2; // data bus for hw loading of eq_tail_overr.
1030wire eq_tail_overr_hw_write_3; // data bus for hw loading of eq_tail_overr.
1031wire eq_tail_overr_hw_write_4; // data bus for hw loading of eq_tail_overr.
1032wire eq_tail_overr_hw_write_5; // data bus for hw loading of eq_tail_overr.
1033wire eq_tail_overr_hw_write_6; // data bus for hw loading of eq_tail_overr.
1034wire eq_tail_overr_hw_write_7; // data bus for hw loading of eq_tail_overr.
1035wire eq_tail_overr_hw_write_8; // data bus for hw loading of eq_tail_overr.
1036wire eq_tail_overr_hw_write_9; // data bus for hw loading of eq_tail_overr.
1037wire eq_tail_overr_hw_write_10; // data bus for hw loading of eq_tail_overr.
1038wire eq_tail_overr_hw_write_11; // data bus for hw loading of eq_tail_overr.
1039wire eq_tail_overr_hw_write_12; // data bus for hw loading of eq_tail_overr.
1040wire eq_tail_overr_hw_write_13; // data bus for hw loading of eq_tail_overr.
1041wire eq_tail_overr_hw_write_14; // data bus for hw loading of eq_tail_overr.
1042wire eq_tail_overr_hw_write_15; // data bus for hw loading of eq_tail_overr.
1043wire eq_tail_overr_hw_write_16; // data bus for hw loading of eq_tail_overr.
1044wire eq_tail_overr_hw_write_17; // data bus for hw loading of eq_tail_overr.
1045wire eq_tail_overr_hw_write_18; // data bus for hw loading of eq_tail_overr.
1046wire eq_tail_overr_hw_write_19; // data bus for hw loading of eq_tail_overr.
1047wire eq_tail_overr_hw_write_20; // data bus for hw loading of eq_tail_overr.
1048wire eq_tail_overr_hw_write_21; // data bus for hw loading of eq_tail_overr.
1049wire eq_tail_overr_hw_write_22; // data bus for hw loading of eq_tail_overr.
1050wire eq_tail_overr_hw_write_23; // data bus for hw loading of eq_tail_overr.
1051wire eq_tail_overr_hw_write_24; // data bus for hw loading of eq_tail_overr.
1052wire eq_tail_overr_hw_write_25; // data bus for hw loading of eq_tail_overr.
1053wire eq_tail_overr_hw_write_26; // data bus for hw loading of eq_tail_overr.
1054wire eq_tail_overr_hw_write_27; // data bus for hw loading of eq_tail_overr.
1055wire eq_tail_overr_hw_write_28; // data bus for hw loading of eq_tail_overr.
1056wire eq_tail_overr_hw_write_29; // data bus for hw loading of eq_tail_overr.
1057wire eq_tail_overr_hw_write_30; // data bus for hw loading of eq_tail_overr.
1058wire eq_tail_overr_hw_write_31; // data bus for hw loading of eq_tail_overr.
1059wire eq_tail_overr_hw_write_32; // data bus for hw loading of eq_tail_overr.
1060wire eq_tail_overr_hw_write_33; // data bus for hw loading of eq_tail_overr.
1061wire eq_tail_overr_hw_write_34; // data bus for hw loading of eq_tail_overr.
1062wire eq_tail_overr_hw_write_35; // data bus for hw loading of eq_tail_overr.
1063wire eq_tail_tail_hw_ld_0; // Hardware load enable for eq_tail_tail. When set,
1064 // <hw write signal> will be loaded into eq_tail.
1065wire eq_tail_tail_hw_ld_1; // Hardware load enable for eq_tail_tail. When set,
1066 // <hw write signal> will be loaded into eq_tail.
1067wire eq_tail_tail_hw_ld_2; // Hardware load enable for eq_tail_tail. When set,
1068 // <hw write signal> will be loaded into eq_tail.
1069wire eq_tail_tail_hw_ld_3; // Hardware load enable for eq_tail_tail. When set,
1070 // <hw write signal> will be loaded into eq_tail.
1071wire eq_tail_tail_hw_ld_4; // Hardware load enable for eq_tail_tail. When set,
1072 // <hw write signal> will be loaded into eq_tail.
1073wire eq_tail_tail_hw_ld_5; // Hardware load enable for eq_tail_tail. When set,
1074 // <hw write signal> will be loaded into eq_tail.
1075wire eq_tail_tail_hw_ld_6; // Hardware load enable for eq_tail_tail. When set,
1076 // <hw write signal> will be loaded into eq_tail.
1077wire eq_tail_tail_hw_ld_7; // Hardware load enable for eq_tail_tail. When set,
1078 // <hw write signal> will be loaded into eq_tail.
1079wire eq_tail_tail_hw_ld_8; // Hardware load enable for eq_tail_tail. When set,
1080 // <hw write signal> will be loaded into eq_tail.
1081wire eq_tail_tail_hw_ld_9; // Hardware load enable for eq_tail_tail. When set,
1082 // <hw write signal> will be loaded into eq_tail.
1083wire eq_tail_tail_hw_ld_10; // Hardware load enable for eq_tail_tail. When set,
1084 // <hw write signal> will be loaded into eq_tail.
1085wire eq_tail_tail_hw_ld_11; // Hardware load enable for eq_tail_tail. When set,
1086 // <hw write signal> will be loaded into eq_tail.
1087wire eq_tail_tail_hw_ld_12; // Hardware load enable for eq_tail_tail. When set,
1088 // <hw write signal> will be loaded into eq_tail.
1089wire eq_tail_tail_hw_ld_13; // Hardware load enable for eq_tail_tail. When set,
1090 // <hw write signal> will be loaded into eq_tail.
1091wire eq_tail_tail_hw_ld_14; // Hardware load enable for eq_tail_tail. When set,
1092 // <hw write signal> will be loaded into eq_tail.
1093wire eq_tail_tail_hw_ld_15; // Hardware load enable for eq_tail_tail. When set,
1094 // <hw write signal> will be loaded into eq_tail.
1095wire eq_tail_tail_hw_ld_16; // Hardware load enable for eq_tail_tail. When set,
1096 // <hw write signal> will be loaded into eq_tail.
1097wire eq_tail_tail_hw_ld_17; // Hardware load enable for eq_tail_tail. When set,
1098 // <hw write signal> will be loaded into eq_tail.
1099wire eq_tail_tail_hw_ld_18; // Hardware load enable for eq_tail_tail. When set,
1100 // <hw write signal> will be loaded into eq_tail.
1101wire eq_tail_tail_hw_ld_19; // Hardware load enable for eq_tail_tail. When set,
1102 // <hw write signal> will be loaded into eq_tail.
1103wire eq_tail_tail_hw_ld_20; // Hardware load enable for eq_tail_tail. When set,
1104 // <hw write signal> will be loaded into eq_tail.
1105wire eq_tail_tail_hw_ld_21; // Hardware load enable for eq_tail_tail. When set,
1106 // <hw write signal> will be loaded into eq_tail.
1107wire eq_tail_tail_hw_ld_22; // Hardware load enable for eq_tail_tail. When set,
1108 // <hw write signal> will be loaded into eq_tail.
1109wire eq_tail_tail_hw_ld_23; // Hardware load enable for eq_tail_tail. When set,
1110 // <hw write signal> will be loaded into eq_tail.
1111wire eq_tail_tail_hw_ld_24; // Hardware load enable for eq_tail_tail. When set,
1112 // <hw write signal> will be loaded into eq_tail.
1113wire eq_tail_tail_hw_ld_25; // Hardware load enable for eq_tail_tail. When set,
1114 // <hw write signal> will be loaded into eq_tail.
1115wire eq_tail_tail_hw_ld_26; // Hardware load enable for eq_tail_tail. When set,
1116 // <hw write signal> will be loaded into eq_tail.
1117wire eq_tail_tail_hw_ld_27; // Hardware load enable for eq_tail_tail. When set,
1118 // <hw write signal> will be loaded into eq_tail.
1119wire eq_tail_tail_hw_ld_28; // Hardware load enable for eq_tail_tail. When set,
1120 // <hw write signal> will be loaded into eq_tail.
1121wire eq_tail_tail_hw_ld_29; // Hardware load enable for eq_tail_tail. When set,
1122 // <hw write signal> will be loaded into eq_tail.
1123wire eq_tail_tail_hw_ld_30; // Hardware load enable for eq_tail_tail. When set,
1124 // <hw write signal> will be loaded into eq_tail.
1125wire eq_tail_tail_hw_ld_31; // Hardware load enable for eq_tail_tail. When set,
1126 // <hw write signal> will be loaded into eq_tail.
1127wire eq_tail_tail_hw_ld_32; // Hardware load enable for eq_tail_tail. When set,
1128 // <hw write signal> will be loaded into eq_tail.
1129wire eq_tail_tail_hw_ld_33; // Hardware load enable for eq_tail_tail. When set,
1130 // <hw write signal> will be loaded into eq_tail.
1131wire eq_tail_tail_hw_ld_34; // Hardware load enable for eq_tail_tail. When set,
1132 // <hw write signal> will be loaded into eq_tail.
1133wire eq_tail_tail_hw_ld_35; // Hardware load enable for eq_tail_tail. When set,
1134 // <hw write signal> will be loaded into eq_tail.
1135wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_0;
1136 // data bus for hw loading of eq_tail_tail.
1137wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_1;
1138 // data bus for hw loading of eq_tail_tail.
1139wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_2;
1140 // data bus for hw loading of eq_tail_tail.
1141wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_3;
1142 // data bus for hw loading of eq_tail_tail.
1143wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_4;
1144 // data bus for hw loading of eq_tail_tail.
1145wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_5;
1146 // data bus for hw loading of eq_tail_tail.
1147wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_6;
1148 // data bus for hw loading of eq_tail_tail.
1149wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_7;
1150 // data bus for hw loading of eq_tail_tail.
1151wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_8;
1152 // data bus for hw loading of eq_tail_tail.
1153wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_9;
1154 // data bus for hw loading of eq_tail_tail.
1155wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_10;
1156 // data bus for hw loading of eq_tail_tail.
1157wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_11;
1158 // data bus for hw loading of eq_tail_tail.
1159wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_12;
1160 // data bus for hw loading of eq_tail_tail.
1161wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_13;
1162 // data bus for hw loading of eq_tail_tail.
1163wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_14;
1164 // data bus for hw loading of eq_tail_tail.
1165wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_15;
1166 // data bus for hw loading of eq_tail_tail.
1167wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_16;
1168 // data bus for hw loading of eq_tail_tail.
1169wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_17;
1170 // data bus for hw loading of eq_tail_tail.
1171wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_18;
1172 // data bus for hw loading of eq_tail_tail.
1173wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_19;
1174 // data bus for hw loading of eq_tail_tail.
1175wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_20;
1176 // data bus for hw loading of eq_tail_tail.
1177wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_21;
1178 // data bus for hw loading of eq_tail_tail.
1179wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_22;
1180 // data bus for hw loading of eq_tail_tail.
1181wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_23;
1182 // data bus for hw loading of eq_tail_tail.
1183wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_24;
1184 // data bus for hw loading of eq_tail_tail.
1185wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_25;
1186 // data bus for hw loading of eq_tail_tail.
1187wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_26;
1188 // data bus for hw loading of eq_tail_tail.
1189wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_27;
1190 // data bus for hw loading of eq_tail_tail.
1191wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_28;
1192 // data bus for hw loading of eq_tail_tail.
1193wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_29;
1194 // data bus for hw loading of eq_tail_tail.
1195wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_30;
1196 // data bus for hw loading of eq_tail_tail.
1197wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_31;
1198 // data bus for hw loading of eq_tail_tail.
1199wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_32;
1200 // data bus for hw loading of eq_tail_tail.
1201wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_33;
1202 // data bus for hw loading of eq_tail_tail.
1203wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_34;
1204 // data bus for hw loading of eq_tail_tail.
1205wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_write_35;
1206 // data bus for hw loading of eq_tail_tail.
1207wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_0;
1208 // This signal provides the current value of eq_tail_tail.
1209wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_1;
1210 // This signal provides the current value of eq_tail_tail.
1211wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_2;
1212 // This signal provides the current value of eq_tail_tail.
1213wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_3;
1214 // This signal provides the current value of eq_tail_tail.
1215wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_4;
1216 // This signal provides the current value of eq_tail_tail.
1217wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_5;
1218 // This signal provides the current value of eq_tail_tail.
1219wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_6;
1220 // This signal provides the current value of eq_tail_tail.
1221wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_7;
1222 // This signal provides the current value of eq_tail_tail.
1223wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_8;
1224 // This signal provides the current value of eq_tail_tail.
1225wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_9;
1226 // This signal provides the current value of eq_tail_tail.
1227wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_10;
1228 // This signal provides the current value of eq_tail_tail.
1229wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_11;
1230 // This signal provides the current value of eq_tail_tail.
1231wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_12;
1232 // This signal provides the current value of eq_tail_tail.
1233wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_13;
1234 // This signal provides the current value of eq_tail_tail.
1235wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_14;
1236 // This signal provides the current value of eq_tail_tail.
1237wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_15;
1238 // This signal provides the current value of eq_tail_tail.
1239wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_16;
1240 // This signal provides the current value of eq_tail_tail.
1241wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_17;
1242 // This signal provides the current value of eq_tail_tail.
1243wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_18;
1244 // This signal provides the current value of eq_tail_tail.
1245wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_19;
1246 // This signal provides the current value of eq_tail_tail.
1247wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_20;
1248 // This signal provides the current value of eq_tail_tail.
1249wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_21;
1250 // This signal provides the current value of eq_tail_tail.
1251wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_22;
1252 // This signal provides the current value of eq_tail_tail.
1253wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_23;
1254 // This signal provides the current value of eq_tail_tail.
1255wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_24;
1256 // This signal provides the current value of eq_tail_tail.
1257wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_25;
1258 // This signal provides the current value of eq_tail_tail.
1259wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_26;
1260 // This signal provides the current value of eq_tail_tail.
1261wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_27;
1262 // This signal provides the current value of eq_tail_tail.
1263wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_28;
1264 // This signal provides the current value of eq_tail_tail.
1265wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_29;
1266 // This signal provides the current value of eq_tail_tail.
1267wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_30;
1268 // This signal provides the current value of eq_tail_tail.
1269wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_31;
1270 // This signal provides the current value of eq_tail_tail.
1271wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_32;
1272 // This signal provides the current value of eq_tail_tail.
1273wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_33;
1274 // This signal provides the current value of eq_tail_tail.
1275wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_34;
1276 // This signal provides the current value of eq_tail_tail.
1277wire [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC] eq_tail_tail_hw_read_35;
1278 // This signal provides the current value of eq_tail_tail.
1279
1280//====================================================================
1281// Logic
1282//====================================================================
1283
1284// synopsys translate_off
1285// verilint 123 off
1286// verilint 498 off
1287reg omni_ld_0;
1288reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_0;
1289
1290// vlint flag_unsynthesizable_initial off
1291initial
1292 begin
1293 omni_ld_0 = 1'b0;
1294 omni_data_0 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1295 end// vlint flag_unsynthesizable_initial on
1296
1297reg omni_ld_1;
1298reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_1;
1299
1300// vlint flag_unsynthesizable_initial off
1301initial
1302 begin
1303 omni_ld_1 = 1'b0;
1304 omni_data_1 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1305 end// vlint flag_unsynthesizable_initial on
1306
1307reg omni_ld_2;
1308reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_2;
1309
1310// vlint flag_unsynthesizable_initial off
1311initial
1312 begin
1313 omni_ld_2 = 1'b0;
1314 omni_data_2 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1315 end// vlint flag_unsynthesizable_initial on
1316
1317reg omni_ld_3;
1318reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_3;
1319
1320// vlint flag_unsynthesizable_initial off
1321initial
1322 begin
1323 omni_ld_3 = 1'b0;
1324 omni_data_3 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1325 end// vlint flag_unsynthesizable_initial on
1326
1327reg omni_ld_4;
1328reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_4;
1329
1330// vlint flag_unsynthesizable_initial off
1331initial
1332 begin
1333 omni_ld_4 = 1'b0;
1334 omni_data_4 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1335 end// vlint flag_unsynthesizable_initial on
1336
1337reg omni_ld_5;
1338reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_5;
1339
1340// vlint flag_unsynthesizable_initial off
1341initial
1342 begin
1343 omni_ld_5 = 1'b0;
1344 omni_data_5 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1345 end// vlint flag_unsynthesizable_initial on
1346
1347reg omni_ld_6;
1348reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_6;
1349
1350// vlint flag_unsynthesizable_initial off
1351initial
1352 begin
1353 omni_ld_6 = 1'b0;
1354 omni_data_6 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1355 end// vlint flag_unsynthesizable_initial on
1356
1357reg omni_ld_7;
1358reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_7;
1359
1360// vlint flag_unsynthesizable_initial off
1361initial
1362 begin
1363 omni_ld_7 = 1'b0;
1364 omni_data_7 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1365 end// vlint flag_unsynthesizable_initial on
1366
1367reg omni_ld_8;
1368reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_8;
1369
1370// vlint flag_unsynthesizable_initial off
1371initial
1372 begin
1373 omni_ld_8 = 1'b0;
1374 omni_data_8 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1375 end// vlint flag_unsynthesizable_initial on
1376
1377reg omni_ld_9;
1378reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_9;
1379
1380// vlint flag_unsynthesizable_initial off
1381initial
1382 begin
1383 omni_ld_9 = 1'b0;
1384 omni_data_9 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1385 end// vlint flag_unsynthesizable_initial on
1386
1387reg omni_ld_10;
1388reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_10;
1389
1390// vlint flag_unsynthesizable_initial off
1391initial
1392 begin
1393 omni_ld_10 = 1'b0;
1394 omni_data_10 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1395 end// vlint flag_unsynthesizable_initial on
1396
1397reg omni_ld_11;
1398reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_11;
1399
1400// vlint flag_unsynthesizable_initial off
1401initial
1402 begin
1403 omni_ld_11 = 1'b0;
1404 omni_data_11 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1405 end// vlint flag_unsynthesizable_initial on
1406
1407reg omni_ld_12;
1408reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_12;
1409
1410// vlint flag_unsynthesizable_initial off
1411initial
1412 begin
1413 omni_ld_12 = 1'b0;
1414 omni_data_12 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1415 end// vlint flag_unsynthesizable_initial on
1416
1417reg omni_ld_13;
1418reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_13;
1419
1420// vlint flag_unsynthesizable_initial off
1421initial
1422 begin
1423 omni_ld_13 = 1'b0;
1424 omni_data_13 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1425 end// vlint flag_unsynthesizable_initial on
1426
1427reg omni_ld_14;
1428reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_14;
1429
1430// vlint flag_unsynthesizable_initial off
1431initial
1432 begin
1433 omni_ld_14 = 1'b0;
1434 omni_data_14 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1435 end// vlint flag_unsynthesizable_initial on
1436
1437reg omni_ld_15;
1438reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_15;
1439
1440// vlint flag_unsynthesizable_initial off
1441initial
1442 begin
1443 omni_ld_15 = 1'b0;
1444 omni_data_15 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1445 end// vlint flag_unsynthesizable_initial on
1446
1447reg omni_ld_16;
1448reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_16;
1449
1450// vlint flag_unsynthesizable_initial off
1451initial
1452 begin
1453 omni_ld_16 = 1'b0;
1454 omni_data_16 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1455 end// vlint flag_unsynthesizable_initial on
1456
1457reg omni_ld_17;
1458reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_17;
1459
1460// vlint flag_unsynthesizable_initial off
1461initial
1462 begin
1463 omni_ld_17 = 1'b0;
1464 omni_data_17 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1465 end// vlint flag_unsynthesizable_initial on
1466
1467reg omni_ld_18;
1468reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_18;
1469
1470// vlint flag_unsynthesizable_initial off
1471initial
1472 begin
1473 omni_ld_18 = 1'b0;
1474 omni_data_18 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1475 end// vlint flag_unsynthesizable_initial on
1476
1477reg omni_ld_19;
1478reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_19;
1479
1480// vlint flag_unsynthesizable_initial off
1481initial
1482 begin
1483 omni_ld_19 = 1'b0;
1484 omni_data_19 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1485 end// vlint flag_unsynthesizable_initial on
1486
1487reg omni_ld_20;
1488reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_20;
1489
1490// vlint flag_unsynthesizable_initial off
1491initial
1492 begin
1493 omni_ld_20 = 1'b0;
1494 omni_data_20 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1495 end// vlint flag_unsynthesizable_initial on
1496
1497reg omni_ld_21;
1498reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_21;
1499
1500// vlint flag_unsynthesizable_initial off
1501initial
1502 begin
1503 omni_ld_21 = 1'b0;
1504 omni_data_21 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1505 end// vlint flag_unsynthesizable_initial on
1506
1507reg omni_ld_22;
1508reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_22;
1509
1510// vlint flag_unsynthesizable_initial off
1511initial
1512 begin
1513 omni_ld_22 = 1'b0;
1514 omni_data_22 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1515 end// vlint flag_unsynthesizable_initial on
1516
1517reg omni_ld_23;
1518reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_23;
1519
1520// vlint flag_unsynthesizable_initial off
1521initial
1522 begin
1523 omni_ld_23 = 1'b0;
1524 omni_data_23 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1525 end// vlint flag_unsynthesizable_initial on
1526
1527reg omni_ld_24;
1528reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_24;
1529
1530// vlint flag_unsynthesizable_initial off
1531initial
1532 begin
1533 omni_ld_24 = 1'b0;
1534 omni_data_24 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1535 end// vlint flag_unsynthesizable_initial on
1536
1537reg omni_ld_25;
1538reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_25;
1539
1540// vlint flag_unsynthesizable_initial off
1541initial
1542 begin
1543 omni_ld_25 = 1'b0;
1544 omni_data_25 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1545 end// vlint flag_unsynthesizable_initial on
1546
1547reg omni_ld_26;
1548reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_26;
1549
1550// vlint flag_unsynthesizable_initial off
1551initial
1552 begin
1553 omni_ld_26 = 1'b0;
1554 omni_data_26 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1555 end// vlint flag_unsynthesizable_initial on
1556
1557reg omni_ld_27;
1558reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_27;
1559
1560// vlint flag_unsynthesizable_initial off
1561initial
1562 begin
1563 omni_ld_27 = 1'b0;
1564 omni_data_27 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1565 end// vlint flag_unsynthesizable_initial on
1566
1567reg omni_ld_28;
1568reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_28;
1569
1570// vlint flag_unsynthesizable_initial off
1571initial
1572 begin
1573 omni_ld_28 = 1'b0;
1574 omni_data_28 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1575 end// vlint flag_unsynthesizable_initial on
1576
1577reg omni_ld_29;
1578reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_29;
1579
1580// vlint flag_unsynthesizable_initial off
1581initial
1582 begin
1583 omni_ld_29 = 1'b0;
1584 omni_data_29 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1585 end// vlint flag_unsynthesizable_initial on
1586
1587reg omni_ld_30;
1588reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_30;
1589
1590// vlint flag_unsynthesizable_initial off
1591initial
1592 begin
1593 omni_ld_30 = 1'b0;
1594 omni_data_30 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1595 end// vlint flag_unsynthesizable_initial on
1596
1597reg omni_ld_31;
1598reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_31;
1599
1600// vlint flag_unsynthesizable_initial off
1601initial
1602 begin
1603 omni_ld_31 = 1'b0;
1604 omni_data_31 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1605 end// vlint flag_unsynthesizable_initial on
1606
1607reg omni_ld_32;
1608reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_32;
1609
1610// vlint flag_unsynthesizable_initial off
1611initial
1612 begin
1613 omni_ld_32 = 1'b0;
1614 omni_data_32 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1615 end// vlint flag_unsynthesizable_initial on
1616
1617reg omni_ld_33;
1618reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_33;
1619
1620// vlint flag_unsynthesizable_initial off
1621initial
1622 begin
1623 omni_ld_33 = 1'b0;
1624 omni_data_33 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1625 end// vlint flag_unsynthesizable_initial on
1626
1627reg omni_ld_34;
1628reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_34;
1629
1630// vlint flag_unsynthesizable_initial off
1631initial
1632 begin
1633 omni_ld_34 = 1'b0;
1634 omni_data_34 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1635 end// vlint flag_unsynthesizable_initial on
1636
1637reg omni_ld_35;
1638reg [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH-1:0] omni_data_35;
1639
1640// vlint flag_unsynthesizable_initial off
1641initial
1642 begin
1643 omni_ld_35 = 1'b0;
1644 omni_data_35 = `FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH'b0;
1645 end// vlint flag_unsynthesizable_initial on
1646
1647// verilint 123 on
1648// verilint 498 on
1649// synopsys translate_on
1650
1651//----- Hardware Data Out Mux Assignments
1652assign eq_tail_tail_hw_read_0=
1653 eq_tail_csrbus_read_data_0
1654 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1655assign eq_tail_tail_hw_read_1=
1656 eq_tail_csrbus_read_data_1
1657 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1658assign eq_tail_tail_hw_read_2=
1659 eq_tail_csrbus_read_data_2
1660 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1661assign eq_tail_tail_hw_read_3=
1662 eq_tail_csrbus_read_data_3
1663 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1664assign eq_tail_tail_hw_read_4=
1665 eq_tail_csrbus_read_data_4
1666 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1667assign eq_tail_tail_hw_read_5=
1668 eq_tail_csrbus_read_data_5
1669 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1670assign eq_tail_tail_hw_read_6=
1671 eq_tail_csrbus_read_data_6
1672 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1673assign eq_tail_tail_hw_read_7=
1674 eq_tail_csrbus_read_data_7
1675 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1676assign eq_tail_tail_hw_read_8=
1677 eq_tail_csrbus_read_data_8
1678 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1679assign eq_tail_tail_hw_read_9=
1680 eq_tail_csrbus_read_data_9
1681 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1682assign eq_tail_tail_hw_read_10=
1683 eq_tail_csrbus_read_data_10
1684 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1685assign eq_tail_tail_hw_read_11=
1686 eq_tail_csrbus_read_data_11
1687 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1688assign eq_tail_tail_hw_read_12=
1689 eq_tail_csrbus_read_data_12
1690 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1691assign eq_tail_tail_hw_read_13=
1692 eq_tail_csrbus_read_data_13
1693 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1694assign eq_tail_tail_hw_read_14=
1695 eq_tail_csrbus_read_data_14
1696 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1697assign eq_tail_tail_hw_read_15=
1698 eq_tail_csrbus_read_data_15
1699 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1700assign eq_tail_tail_hw_read_16=
1701 eq_tail_csrbus_read_data_16
1702 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1703assign eq_tail_tail_hw_read_17=
1704 eq_tail_csrbus_read_data_17
1705 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1706assign eq_tail_tail_hw_read_18=
1707 eq_tail_csrbus_read_data_18
1708 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1709assign eq_tail_tail_hw_read_19=
1710 eq_tail_csrbus_read_data_19
1711 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1712assign eq_tail_tail_hw_read_20=
1713 eq_tail_csrbus_read_data_20
1714 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1715assign eq_tail_tail_hw_read_21=
1716 eq_tail_csrbus_read_data_21
1717 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1718assign eq_tail_tail_hw_read_22=
1719 eq_tail_csrbus_read_data_22
1720 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1721assign eq_tail_tail_hw_read_23=
1722 eq_tail_csrbus_read_data_23
1723 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1724assign eq_tail_tail_hw_read_24=
1725 eq_tail_csrbus_read_data_24
1726 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1727assign eq_tail_tail_hw_read_25=
1728 eq_tail_csrbus_read_data_25
1729 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1730assign eq_tail_tail_hw_read_26=
1731 eq_tail_csrbus_read_data_26
1732 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1733assign eq_tail_tail_hw_read_27=
1734 eq_tail_csrbus_read_data_27
1735 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1736assign eq_tail_tail_hw_read_28=
1737 eq_tail_csrbus_read_data_28
1738 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1739assign eq_tail_tail_hw_read_29=
1740 eq_tail_csrbus_read_data_29
1741 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1742assign eq_tail_tail_hw_read_30=
1743 eq_tail_csrbus_read_data_30
1744 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1745assign eq_tail_tail_hw_read_31=
1746 eq_tail_csrbus_read_data_31
1747 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1748assign eq_tail_tail_hw_read_32=
1749 eq_tail_csrbus_read_data_32
1750 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1751assign eq_tail_tail_hw_read_33=
1752 eq_tail_csrbus_read_data_33
1753 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1754assign eq_tail_tail_hw_read_34=
1755 eq_tail_csrbus_read_data_34
1756 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1757assign eq_tail_tail_hw_read_35=
1758 eq_tail_csrbus_read_data_35
1759 [`FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC];
1760
1761//====================================================================
1762// Instantiation of entries
1763//====================================================================
1764
1765//----- Entry 0
1766dmu_imu_eqs_csr_eq_tail_entry eq_tail_0
1767 (
1768 // synopsys translate_off
1769 .omni_ld (omni_ld_0),
1770 .omni_data (omni_data_0),
1771 // synopsys translate_on
1772 .clk (clk),
1773 .rst_l (rst_l),
1774 .w_ld (eq_tail_w_ld_0),
1775 .csrbus_wr_data (csrbus_wr_data),
1776 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_0),
1777 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_0),
1778 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_0),
1779 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_0),
1780 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_0)
1781 );
1782
1783//----- Entry 1
1784dmu_imu_eqs_csr_eq_tail_entry eq_tail_1
1785 (
1786 // synopsys translate_off
1787 .omni_ld (omni_ld_1),
1788 .omni_data (omni_data_1),
1789 // synopsys translate_on
1790 .clk (clk),
1791 .rst_l (rst_l),
1792 .w_ld (eq_tail_w_ld_1),
1793 .csrbus_wr_data (csrbus_wr_data),
1794 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_1),
1795 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_1),
1796 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_1),
1797 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_1),
1798 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_1)
1799 );
1800
1801//----- Entry 2
1802dmu_imu_eqs_csr_eq_tail_entry eq_tail_2
1803 (
1804 // synopsys translate_off
1805 .omni_ld (omni_ld_2),
1806 .omni_data (omni_data_2),
1807 // synopsys translate_on
1808 .clk (clk),
1809 .rst_l (rst_l),
1810 .w_ld (eq_tail_w_ld_2),
1811 .csrbus_wr_data (csrbus_wr_data),
1812 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_2),
1813 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_2),
1814 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_2),
1815 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_2),
1816 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_2)
1817 );
1818
1819//----- Entry 3
1820dmu_imu_eqs_csr_eq_tail_entry eq_tail_3
1821 (
1822 // synopsys translate_off
1823 .omni_ld (omni_ld_3),
1824 .omni_data (omni_data_3),
1825 // synopsys translate_on
1826 .clk (clk),
1827 .rst_l (rst_l),
1828 .w_ld (eq_tail_w_ld_3),
1829 .csrbus_wr_data (csrbus_wr_data),
1830 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_3),
1831 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_3),
1832 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_3),
1833 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_3),
1834 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_3)
1835 );
1836
1837//----- Entry 4
1838dmu_imu_eqs_csr_eq_tail_entry eq_tail_4
1839 (
1840 // synopsys translate_off
1841 .omni_ld (omni_ld_4),
1842 .omni_data (omni_data_4),
1843 // synopsys translate_on
1844 .clk (clk),
1845 .rst_l (rst_l),
1846 .w_ld (eq_tail_w_ld_4),
1847 .csrbus_wr_data (csrbus_wr_data),
1848 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_4),
1849 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_4),
1850 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_4),
1851 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_4),
1852 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_4)
1853 );
1854
1855//----- Entry 5
1856dmu_imu_eqs_csr_eq_tail_entry eq_tail_5
1857 (
1858 // synopsys translate_off
1859 .omni_ld (omni_ld_5),
1860 .omni_data (omni_data_5),
1861 // synopsys translate_on
1862 .clk (clk),
1863 .rst_l (rst_l),
1864 .w_ld (eq_tail_w_ld_5),
1865 .csrbus_wr_data (csrbus_wr_data),
1866 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_5),
1867 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_5),
1868 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_5),
1869 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_5),
1870 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_5)
1871 );
1872
1873//----- Entry 6
1874dmu_imu_eqs_csr_eq_tail_entry eq_tail_6
1875 (
1876 // synopsys translate_off
1877 .omni_ld (omni_ld_6),
1878 .omni_data (omni_data_6),
1879 // synopsys translate_on
1880 .clk (clk),
1881 .rst_l (rst_l),
1882 .w_ld (eq_tail_w_ld_6),
1883 .csrbus_wr_data (csrbus_wr_data),
1884 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_6),
1885 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_6),
1886 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_6),
1887 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_6),
1888 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_6)
1889 );
1890
1891//----- Entry 7
1892dmu_imu_eqs_csr_eq_tail_entry eq_tail_7
1893 (
1894 // synopsys translate_off
1895 .omni_ld (omni_ld_7),
1896 .omni_data (omni_data_7),
1897 // synopsys translate_on
1898 .clk (clk),
1899 .rst_l (rst_l),
1900 .w_ld (eq_tail_w_ld_7),
1901 .csrbus_wr_data (csrbus_wr_data),
1902 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_7),
1903 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_7),
1904 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_7),
1905 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_7),
1906 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_7)
1907 );
1908
1909//----- Entry 8
1910dmu_imu_eqs_csr_eq_tail_entry eq_tail_8
1911 (
1912 // synopsys translate_off
1913 .omni_ld (omni_ld_8),
1914 .omni_data (omni_data_8),
1915 // synopsys translate_on
1916 .clk (clk),
1917 .rst_l (rst_l),
1918 .w_ld (eq_tail_w_ld_8),
1919 .csrbus_wr_data (csrbus_wr_data),
1920 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_8),
1921 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_8),
1922 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_8),
1923 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_8),
1924 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_8)
1925 );
1926
1927//----- Entry 9
1928dmu_imu_eqs_csr_eq_tail_entry eq_tail_9
1929 (
1930 // synopsys translate_off
1931 .omni_ld (omni_ld_9),
1932 .omni_data (omni_data_9),
1933 // synopsys translate_on
1934 .clk (clk),
1935 .rst_l (rst_l),
1936 .w_ld (eq_tail_w_ld_9),
1937 .csrbus_wr_data (csrbus_wr_data),
1938 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_9),
1939 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_9),
1940 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_9),
1941 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_9),
1942 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_9)
1943 );
1944
1945//----- Entry 10
1946dmu_imu_eqs_csr_eq_tail_entry eq_tail_10
1947 (
1948 // synopsys translate_off
1949 .omni_ld (omni_ld_10),
1950 .omni_data (omni_data_10),
1951 // synopsys translate_on
1952 .clk (clk),
1953 .rst_l (rst_l),
1954 .w_ld (eq_tail_w_ld_10),
1955 .csrbus_wr_data (csrbus_wr_data),
1956 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_10),
1957 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_10),
1958 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_10),
1959 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_10),
1960 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_10)
1961 );
1962
1963//----- Entry 11
1964dmu_imu_eqs_csr_eq_tail_entry eq_tail_11
1965 (
1966 // synopsys translate_off
1967 .omni_ld (omni_ld_11),
1968 .omni_data (omni_data_11),
1969 // synopsys translate_on
1970 .clk (clk),
1971 .rst_l (rst_l),
1972 .w_ld (eq_tail_w_ld_11),
1973 .csrbus_wr_data (csrbus_wr_data),
1974 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_11),
1975 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_11),
1976 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_11),
1977 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_11),
1978 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_11)
1979 );
1980
1981//----- Entry 12
1982dmu_imu_eqs_csr_eq_tail_entry eq_tail_12
1983 (
1984 // synopsys translate_off
1985 .omni_ld (omni_ld_12),
1986 .omni_data (omni_data_12),
1987 // synopsys translate_on
1988 .clk (clk),
1989 .rst_l (rst_l),
1990 .w_ld (eq_tail_w_ld_12),
1991 .csrbus_wr_data (csrbus_wr_data),
1992 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_12),
1993 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_12),
1994 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_12),
1995 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_12),
1996 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_12)
1997 );
1998
1999//----- Entry 13
2000dmu_imu_eqs_csr_eq_tail_entry eq_tail_13
2001 (
2002 // synopsys translate_off
2003 .omni_ld (omni_ld_13),
2004 .omni_data (omni_data_13),
2005 // synopsys translate_on
2006 .clk (clk),
2007 .rst_l (rst_l),
2008 .w_ld (eq_tail_w_ld_13),
2009 .csrbus_wr_data (csrbus_wr_data),
2010 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_13),
2011 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_13),
2012 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_13),
2013 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_13),
2014 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_13)
2015 );
2016
2017//----- Entry 14
2018dmu_imu_eqs_csr_eq_tail_entry eq_tail_14
2019 (
2020 // synopsys translate_off
2021 .omni_ld (omni_ld_14),
2022 .omni_data (omni_data_14),
2023 // synopsys translate_on
2024 .clk (clk),
2025 .rst_l (rst_l),
2026 .w_ld (eq_tail_w_ld_14),
2027 .csrbus_wr_data (csrbus_wr_data),
2028 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_14),
2029 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_14),
2030 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_14),
2031 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_14),
2032 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_14)
2033 );
2034
2035//----- Entry 15
2036dmu_imu_eqs_csr_eq_tail_entry eq_tail_15
2037 (
2038 // synopsys translate_off
2039 .omni_ld (omni_ld_15),
2040 .omni_data (omni_data_15),
2041 // synopsys translate_on
2042 .clk (clk),
2043 .rst_l (rst_l),
2044 .w_ld (eq_tail_w_ld_15),
2045 .csrbus_wr_data (csrbus_wr_data),
2046 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_15),
2047 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_15),
2048 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_15),
2049 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_15),
2050 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_15)
2051 );
2052
2053//----- Entry 16
2054dmu_imu_eqs_csr_eq_tail_entry eq_tail_16
2055 (
2056 // synopsys translate_off
2057 .omni_ld (omni_ld_16),
2058 .omni_data (omni_data_16),
2059 // synopsys translate_on
2060 .clk (clk),
2061 .rst_l (rst_l),
2062 .w_ld (eq_tail_w_ld_16),
2063 .csrbus_wr_data (csrbus_wr_data),
2064 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_16),
2065 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_16),
2066 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_16),
2067 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_16),
2068 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_16)
2069 );
2070
2071//----- Entry 17
2072dmu_imu_eqs_csr_eq_tail_entry eq_tail_17
2073 (
2074 // synopsys translate_off
2075 .omni_ld (omni_ld_17),
2076 .omni_data (omni_data_17),
2077 // synopsys translate_on
2078 .clk (clk),
2079 .rst_l (rst_l),
2080 .w_ld (eq_tail_w_ld_17),
2081 .csrbus_wr_data (csrbus_wr_data),
2082 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_17),
2083 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_17),
2084 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_17),
2085 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_17),
2086 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_17)
2087 );
2088
2089//----- Entry 18
2090dmu_imu_eqs_csr_eq_tail_entry eq_tail_18
2091 (
2092 // synopsys translate_off
2093 .omni_ld (omni_ld_18),
2094 .omni_data (omni_data_18),
2095 // synopsys translate_on
2096 .clk (clk),
2097 .rst_l (rst_l),
2098 .w_ld (eq_tail_w_ld_18),
2099 .csrbus_wr_data (csrbus_wr_data),
2100 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_18),
2101 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_18),
2102 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_18),
2103 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_18),
2104 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_18)
2105 );
2106
2107//----- Entry 19
2108dmu_imu_eqs_csr_eq_tail_entry eq_tail_19
2109 (
2110 // synopsys translate_off
2111 .omni_ld (omni_ld_19),
2112 .omni_data (omni_data_19),
2113 // synopsys translate_on
2114 .clk (clk),
2115 .rst_l (rst_l),
2116 .w_ld (eq_tail_w_ld_19),
2117 .csrbus_wr_data (csrbus_wr_data),
2118 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_19),
2119 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_19),
2120 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_19),
2121 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_19),
2122 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_19)
2123 );
2124
2125//----- Entry 20
2126dmu_imu_eqs_csr_eq_tail_entry eq_tail_20
2127 (
2128 // synopsys translate_off
2129 .omni_ld (omni_ld_20),
2130 .omni_data (omni_data_20),
2131 // synopsys translate_on
2132 .clk (clk),
2133 .rst_l (rst_l),
2134 .w_ld (eq_tail_w_ld_20),
2135 .csrbus_wr_data (csrbus_wr_data),
2136 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_20),
2137 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_20),
2138 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_20),
2139 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_20),
2140 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_20)
2141 );
2142
2143//----- Entry 21
2144dmu_imu_eqs_csr_eq_tail_entry eq_tail_21
2145 (
2146 // synopsys translate_off
2147 .omni_ld (omni_ld_21),
2148 .omni_data (omni_data_21),
2149 // synopsys translate_on
2150 .clk (clk),
2151 .rst_l (rst_l),
2152 .w_ld (eq_tail_w_ld_21),
2153 .csrbus_wr_data (csrbus_wr_data),
2154 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_21),
2155 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_21),
2156 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_21),
2157 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_21),
2158 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_21)
2159 );
2160
2161//----- Entry 22
2162dmu_imu_eqs_csr_eq_tail_entry eq_tail_22
2163 (
2164 // synopsys translate_off
2165 .omni_ld (omni_ld_22),
2166 .omni_data (omni_data_22),
2167 // synopsys translate_on
2168 .clk (clk),
2169 .rst_l (rst_l),
2170 .w_ld (eq_tail_w_ld_22),
2171 .csrbus_wr_data (csrbus_wr_data),
2172 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_22),
2173 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_22),
2174 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_22),
2175 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_22),
2176 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_22)
2177 );
2178
2179//----- Entry 23
2180dmu_imu_eqs_csr_eq_tail_entry eq_tail_23
2181 (
2182 // synopsys translate_off
2183 .omni_ld (omni_ld_23),
2184 .omni_data (omni_data_23),
2185 // synopsys translate_on
2186 .clk (clk),
2187 .rst_l (rst_l),
2188 .w_ld (eq_tail_w_ld_23),
2189 .csrbus_wr_data (csrbus_wr_data),
2190 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_23),
2191 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_23),
2192 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_23),
2193 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_23),
2194 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_23)
2195 );
2196
2197//----- Entry 24
2198dmu_imu_eqs_csr_eq_tail_entry eq_tail_24
2199 (
2200 // synopsys translate_off
2201 .omni_ld (omni_ld_24),
2202 .omni_data (omni_data_24),
2203 // synopsys translate_on
2204 .clk (clk),
2205 .rst_l (rst_l),
2206 .w_ld (eq_tail_w_ld_24),
2207 .csrbus_wr_data (csrbus_wr_data),
2208 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_24),
2209 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_24),
2210 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_24),
2211 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_24),
2212 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_24)
2213 );
2214
2215//----- Entry 25
2216dmu_imu_eqs_csr_eq_tail_entry eq_tail_25
2217 (
2218 // synopsys translate_off
2219 .omni_ld (omni_ld_25),
2220 .omni_data (omni_data_25),
2221 // synopsys translate_on
2222 .clk (clk),
2223 .rst_l (rst_l),
2224 .w_ld (eq_tail_w_ld_25),
2225 .csrbus_wr_data (csrbus_wr_data),
2226 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_25),
2227 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_25),
2228 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_25),
2229 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_25),
2230 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_25)
2231 );
2232
2233//----- Entry 26
2234dmu_imu_eqs_csr_eq_tail_entry eq_tail_26
2235 (
2236 // synopsys translate_off
2237 .omni_ld (omni_ld_26),
2238 .omni_data (omni_data_26),
2239 // synopsys translate_on
2240 .clk (clk),
2241 .rst_l (rst_l),
2242 .w_ld (eq_tail_w_ld_26),
2243 .csrbus_wr_data (csrbus_wr_data),
2244 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_26),
2245 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_26),
2246 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_26),
2247 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_26),
2248 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_26)
2249 );
2250
2251//----- Entry 27
2252dmu_imu_eqs_csr_eq_tail_entry eq_tail_27
2253 (
2254 // synopsys translate_off
2255 .omni_ld (omni_ld_27),
2256 .omni_data (omni_data_27),
2257 // synopsys translate_on
2258 .clk (clk),
2259 .rst_l (rst_l),
2260 .w_ld (eq_tail_w_ld_27),
2261 .csrbus_wr_data (csrbus_wr_data),
2262 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_27),
2263 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_27),
2264 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_27),
2265 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_27),
2266 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_27)
2267 );
2268
2269//----- Entry 28
2270dmu_imu_eqs_csr_eq_tail_entry eq_tail_28
2271 (
2272 // synopsys translate_off
2273 .omni_ld (omni_ld_28),
2274 .omni_data (omni_data_28),
2275 // synopsys translate_on
2276 .clk (clk),
2277 .rst_l (rst_l),
2278 .w_ld (eq_tail_w_ld_28),
2279 .csrbus_wr_data (csrbus_wr_data),
2280 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_28),
2281 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_28),
2282 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_28),
2283 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_28),
2284 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_28)
2285 );
2286
2287//----- Entry 29
2288dmu_imu_eqs_csr_eq_tail_entry eq_tail_29
2289 (
2290 // synopsys translate_off
2291 .omni_ld (omni_ld_29),
2292 .omni_data (omni_data_29),
2293 // synopsys translate_on
2294 .clk (clk),
2295 .rst_l (rst_l),
2296 .w_ld (eq_tail_w_ld_29),
2297 .csrbus_wr_data (csrbus_wr_data),
2298 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_29),
2299 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_29),
2300 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_29),
2301 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_29),
2302 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_29)
2303 );
2304
2305//----- Entry 30
2306dmu_imu_eqs_csr_eq_tail_entry eq_tail_30
2307 (
2308 // synopsys translate_off
2309 .omni_ld (omni_ld_30),
2310 .omni_data (omni_data_30),
2311 // synopsys translate_on
2312 .clk (clk),
2313 .rst_l (rst_l),
2314 .w_ld (eq_tail_w_ld_30),
2315 .csrbus_wr_data (csrbus_wr_data),
2316 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_30),
2317 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_30),
2318 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_30),
2319 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_30),
2320 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_30)
2321 );
2322
2323//----- Entry 31
2324dmu_imu_eqs_csr_eq_tail_entry eq_tail_31
2325 (
2326 // synopsys translate_off
2327 .omni_ld (omni_ld_31),
2328 .omni_data (omni_data_31),
2329 // synopsys translate_on
2330 .clk (clk),
2331 .rst_l (rst_l),
2332 .w_ld (eq_tail_w_ld_31),
2333 .csrbus_wr_data (csrbus_wr_data),
2334 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_31),
2335 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_31),
2336 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_31),
2337 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_31),
2338 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_31)
2339 );
2340
2341//----- Entry 32
2342dmu_imu_eqs_csr_eq_tail_entry eq_tail_32
2343 (
2344 // synopsys translate_off
2345 .omni_ld (omni_ld_32),
2346 .omni_data (omni_data_32),
2347 // synopsys translate_on
2348 .clk (clk),
2349 .rst_l (rst_l),
2350 .w_ld (eq_tail_w_ld_32),
2351 .csrbus_wr_data (csrbus_wr_data),
2352 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_32),
2353 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_32),
2354 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_32),
2355 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_32),
2356 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_32)
2357 );
2358
2359//----- Entry 33
2360dmu_imu_eqs_csr_eq_tail_entry eq_tail_33
2361 (
2362 // synopsys translate_off
2363 .omni_ld (omni_ld_33),
2364 .omni_data (omni_data_33),
2365 // synopsys translate_on
2366 .clk (clk),
2367 .rst_l (rst_l),
2368 .w_ld (eq_tail_w_ld_33),
2369 .csrbus_wr_data (csrbus_wr_data),
2370 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_33),
2371 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_33),
2372 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_33),
2373 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_33),
2374 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_33)
2375 );
2376
2377//----- Entry 34
2378dmu_imu_eqs_csr_eq_tail_entry eq_tail_34
2379 (
2380 // synopsys translate_off
2381 .omni_ld (omni_ld_34),
2382 .omni_data (omni_data_34),
2383 // synopsys translate_on
2384 .clk (clk),
2385 .rst_l (rst_l),
2386 .w_ld (eq_tail_w_ld_34),
2387 .csrbus_wr_data (csrbus_wr_data),
2388 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_34),
2389 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_34),
2390 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_34),
2391 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_34),
2392 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_34)
2393 );
2394
2395//----- Entry 35
2396dmu_imu_eqs_csr_eq_tail_entry eq_tail_35
2397 (
2398 // synopsys translate_off
2399 .omni_ld (omni_ld_35),
2400 .omni_data (omni_data_35),
2401 // synopsys translate_on
2402 .clk (clk),
2403 .rst_l (rst_l),
2404 .w_ld (eq_tail_w_ld_35),
2405 .csrbus_wr_data (csrbus_wr_data),
2406 .eq_tail_csrbus_read_data (eq_tail_csrbus_read_data_35),
2407 .eq_tail_overr_hw_ld (eq_tail_overr_hw_ld_35),
2408 .eq_tail_overr_hw_write (eq_tail_overr_hw_write_35),
2409 .eq_tail_tail_hw_ld (eq_tail_tail_hw_ld_35),
2410 .eq_tail_tail_hw_write (eq_tail_tail_hw_write_35)
2411 );
2412
2413endmodule // dmu_imu_eqs_csr_eq_tail
Full OpenSPARC design & verification tarball including full HDL.