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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_ics_addr_decode.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_ics_addr_decode.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
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29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_ics_addr_decode
36 (
37 clk,
38 rst_l,
39 daemon_csrbus_valid,
40 daemon_csrbus_addr,
41 csrbus_src_bus,
42 daemon_csrbus_wr,
43 daemon_csrbus_wr_out,
44 daemon_csrbus_wr_data,
45 daemon_csrbus_wr_data_out,
46 daemon_csrbus_mapped,
47 csrbus_acc_vio,
48 daemon_transaction_in_progress,
49 instance_id,
50 daemon_csrbus_done,
51 imu_error_log_en_reg_select_pulse,
52 imu_int_en_reg_select_pulse,
53 imu_enabled_error_status_reg_select,
54 imu_logged_error_status_reg_select_pulse,
55 imu_logged_error_status_reg_rw1c_alias,
56 imu_logged_error_status_reg_rw1s_alias,
57 imu_rds_error_log_reg_select_pulse,
58 imu_scs_error_log_reg_select_pulse,
59 imu_eqs_error_log_reg_select_pulse,
60 dmc_interrupt_mask_reg_select_pulse,
61 dmc_interrupt_status_reg_select,
62 imu_perf_cntrl_select_pulse,
63 imu_perf_cnt0_select_pulse,
64 imu_perf_cnt1_select_pulse,
65 msi_32_addr_reg_select_pulse,
66 msi_64_addr_reg_select_pulse,
67 mem_64_pcie_offset_reg_select_pulse
68 );
69
70//====================================================================
71// Polarity declarations
72//====================================================================
73input clk; // Clock signal
74input rst_l; // Reset
75input daemon_csrbus_valid; // Daemon_Valid
76input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
77input [1:0] csrbus_src_bus; // Source bus
78input daemon_csrbus_wr; // Read/Write signal
79output daemon_csrbus_wr_out; // Read/Write signal
80input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
81output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
82output daemon_csrbus_mapped; // mapped
83output csrbus_acc_vio; // acc_vio
84input daemon_transaction_in_progress; // daemon_transaction_in_progress
85input instance_id; // Instance ID
86output daemon_csrbus_done; // Operation is done
87output imu_error_log_en_reg_select_pulse; // select signal
88output imu_int_en_reg_select_pulse; // select signal
89output imu_enabled_error_status_reg_select; // select signal
90output imu_logged_error_status_reg_select_pulse; // select signal
91output imu_logged_error_status_reg_rw1c_alias; // alias signal
92output imu_logged_error_status_reg_rw1s_alias; // alias signal
93output imu_rds_error_log_reg_select_pulse; // select signal
94output imu_scs_error_log_reg_select_pulse; // select signal
95output imu_eqs_error_log_reg_select_pulse; // select signal
96output dmc_interrupt_mask_reg_select_pulse; // select signal
97output dmc_interrupt_status_reg_select; // select signal
98output imu_perf_cntrl_select_pulse; // select signal
99output imu_perf_cnt0_select_pulse; // select signal
100output imu_perf_cnt1_select_pulse; // select signal
101output msi_32_addr_reg_select_pulse; // select signal
102output msi_64_addr_reg_select_pulse; // select signal
103output mem_64_pcie_offset_reg_select_pulse; // select signal
104
105//====================================================================
106// Type declarations
107//====================================================================
108wire clk; // Clock signal
109wire rst_l; // Reset
110wire daemon_csrbus_valid; // Daemon_Valid
111wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
112wire [1:0] csrbus_src_bus; // Source bus
113wire daemon_csrbus_wr; // Read/Write signal
114reg daemon_csrbus_wr_out; // Read/Write signal
115wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
116reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
117wire daemon_csrbus_mapped; // mapped
118wire csrbus_acc_vio; // acc_vio
119wire daemon_transaction_in_progress; // daemon_transaction_in_progress
120wire instance_id; // Instance ID
121wire daemon_csrbus_done; // Operation is done
122reg imu_error_log_en_reg_select_pulse; // select signal
123reg imu_int_en_reg_select_pulse; // select signal
124reg imu_enabled_error_status_reg_select; // select signal
125reg imu_logged_error_status_reg_select_pulse; // select signal
126wire imu_logged_error_status_reg_rw1c_alias; // alias signal
127wire imu_logged_error_status_reg_rw1s_alias; // alias signal
128reg imu_rds_error_log_reg_select_pulse; // select signal
129reg imu_scs_error_log_reg_select_pulse; // select signal
130reg imu_eqs_error_log_reg_select_pulse; // select signal
131reg dmc_interrupt_mask_reg_select_pulse; // select signal
132reg dmc_interrupt_status_reg_select; // select signal
133reg imu_perf_cntrl_select_pulse; // select signal
134reg imu_perf_cnt0_select_pulse; // select signal
135reg imu_perf_cnt1_select_pulse; // select signal
136reg msi_32_addr_reg_select_pulse; // select signal
137reg msi_64_addr_reg_select_pulse; // select signal
138reg mem_64_pcie_offset_reg_select_pulse; // select signal
139
140
141//====================================================================
142// Clocked valid
143//====================================================================
144reg clocked_valid;
145reg clocked_valid_pulse;
146always @(posedge clk)
147 begin
148 if(~rst_l)
149 begin
150 clocked_valid <= 1'b0;
151 clocked_valid_pulse <= 1'b0;
152 end
153 else
154 begin
155 clocked_valid <= daemon_csrbus_valid;
156 clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid;
157 end
158 end
159
160//====================================================================
161// Address Decode
162//====================================================================
163reg imu_error_log_en_reg_addr_decoded;
164reg imu_int_en_reg_addr_decoded;
165reg imu_enabled_error_status_reg_addr_decoded;
166reg imu_logged_error_status_reg_rw1c_alias_addr_decoded;
167reg imu_logged_error_status_reg_rw1s_alias_addr_decoded;
168reg imu_rds_error_log_reg_addr_decoded;
169reg imu_scs_error_log_reg_addr_decoded;
170reg imu_eqs_error_log_reg_addr_decoded;
171reg dmc_interrupt_mask_reg_addr_decoded;
172reg dmc_interrupt_status_reg_addr_decoded;
173reg imu_perf_cntrl_addr_decoded;
174reg imu_perf_cnt0_addr_decoded;
175reg imu_perf_cnt1_addr_decoded;
176reg msi_32_addr_reg_addr_decoded;
177reg msi_64_addr_reg_addr_decoded;
178reg mem_64_pcie_offset_reg_addr_decoded;
179
180always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id)
181 begin
182 if (~daemon_csrbus_valid)
183 begin
184 imu_error_log_en_reg_addr_decoded = 1'b0;
185 imu_int_en_reg_addr_decoded = 1'b0;
186 imu_enabled_error_status_reg_addr_decoded = 1'b0;
187 imu_logged_error_status_reg_rw1c_alias_addr_decoded = 1'b0;
188 imu_logged_error_status_reg_rw1s_alias_addr_decoded = 1'b0;
189 imu_rds_error_log_reg_addr_decoded = 1'b0;
190 imu_scs_error_log_reg_addr_decoded = 1'b0;
191 imu_eqs_error_log_reg_addr_decoded = 1'b0;
192 dmc_interrupt_mask_reg_addr_decoded = 1'b0;
193 dmc_interrupt_status_reg_addr_decoded = 1'b0;
194 imu_perf_cntrl_addr_decoded = 1'b0;
195 imu_perf_cnt0_addr_decoded = 1'b0;
196 imu_perf_cnt1_addr_decoded = 1'b0;
197 msi_32_addr_reg_addr_decoded = 1'b0;
198 msi_64_addr_reg_addr_decoded = 1'b0;
199 mem_64_pcie_offset_reg_addr_decoded = 1'b0;
200 end
201 else
202 case (instance_id)
203
204 `FIRE_DLC_IMU_ICS_INSTANCE_ID_VALUE_A:
205 begin
206 imu_error_log_en_reg_addr_decoded =
207 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_HW_ADDR;
208 imu_int_en_reg_addr_decoded =
209 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_HW_ADDR;
210 imu_enabled_error_status_reg_addr_decoded =
211 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_HW_ADDR;
212 imu_logged_error_status_reg_rw1c_alias_addr_decoded =
213 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_ADDR;
214 imu_logged_error_status_reg_rw1s_alias_addr_decoded =
215 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_ADDR;
216 imu_rds_error_log_reg_addr_decoded =
217 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_HW_ADDR;
218 imu_scs_error_log_reg_addr_decoded =
219 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_HW_ADDR;
220 imu_eqs_error_log_reg_addr_decoded =
221 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_HW_ADDR;
222 dmc_interrupt_mask_reg_addr_decoded =
223 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_HW_ADDR;
224 dmc_interrupt_status_reg_addr_decoded =
225 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_HW_ADDR;
226 imu_perf_cntrl_addr_decoded =
227 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_HW_ADDR;
228 imu_perf_cnt0_addr_decoded =
229 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_HW_ADDR;
230 imu_perf_cnt1_addr_decoded =
231 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_HW_ADDR;
232 msi_32_addr_reg_addr_decoded =
233 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_HW_ADDR;
234 msi_64_addr_reg_addr_decoded =
235 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_HW_ADDR;
236 mem_64_pcie_offset_reg_addr_decoded =
237 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_HW_ADDR;
238 end
239
240 `FIRE_DLC_IMU_ICS_INSTANCE_ID_VALUE_B:
241 begin
242 imu_error_log_en_reg_addr_decoded =
243 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_ERROR_LOG_EN_REG_HW_ADDR;
244 imu_int_en_reg_addr_decoded =
245 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_INT_EN_REG_HW_ADDR;
246 imu_enabled_error_status_reg_addr_decoded =
247 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_ENABLED_ERROR_STATUS_REG_HW_ADDR;
248 imu_logged_error_status_reg_rw1c_alias_addr_decoded =
249 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_ADDR;
250 imu_logged_error_status_reg_rw1s_alias_addr_decoded =
251 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_ADDR;
252 imu_rds_error_log_reg_addr_decoded =
253 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_RDS_ERROR_LOG_REG_HW_ADDR;
254 imu_scs_error_log_reg_addr_decoded =
255 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_SCS_ERROR_LOG_REG_HW_ADDR;
256 imu_eqs_error_log_reg_addr_decoded =
257 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_EQS_ERROR_LOG_REG_HW_ADDR;
258 dmc_interrupt_mask_reg_addr_decoded =
259 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_MASK_REG_HW_ADDR;
260 dmc_interrupt_status_reg_addr_decoded =
261 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_STATUS_REG_HW_ADDR;
262 imu_perf_cntrl_addr_decoded =
263 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNTRL_HW_ADDR;
264 imu_perf_cnt0_addr_decoded =
265 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT0_HW_ADDR;
266 imu_perf_cnt1_addr_decoded =
267 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT1_HW_ADDR;
268 msi_32_addr_reg_addr_decoded =
269 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_MSI_32_ADDR_REG_HW_ADDR;
270 msi_64_addr_reg_addr_decoded =
271 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_MSI_64_ADDR_REG_HW_ADDR;
272 mem_64_pcie_offset_reg_addr_decoded =
273 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_ICS_CSR_B_MEM_64_PCIE_OFFSET_REG_HW_ADDR;
274 end
275
276 default:
277 begin
278 imu_error_log_en_reg_addr_decoded = 1'b0;
279 imu_int_en_reg_addr_decoded = 1'b0;
280 imu_enabled_error_status_reg_addr_decoded = 1'b0;
281 imu_logged_error_status_reg_rw1s_alias_addr_decoded = 1'b0;
282 imu_logged_error_status_reg_rw1c_alias_addr_decoded = 1'b0;
283 imu_rds_error_log_reg_addr_decoded = 1'b0;
284 imu_scs_error_log_reg_addr_decoded = 1'b0;
285 imu_eqs_error_log_reg_addr_decoded = 1'b0;
286 dmc_interrupt_mask_reg_addr_decoded = 1'b0;
287 dmc_interrupt_status_reg_addr_decoded = 1'b0;
288 imu_perf_cntrl_addr_decoded = 1'b0;
289 imu_perf_cnt0_addr_decoded = 1'b0;
290 imu_perf_cnt1_addr_decoded = 1'b0;
291 msi_32_addr_reg_addr_decoded = 1'b0;
292 msi_64_addr_reg_addr_decoded = 1'b0;
293 mem_64_pcie_offset_reg_addr_decoded = 1'b0;
294// vlint flag_system_call off
295 // synopsys translate_off
296 if(daemon_csrbus_valid)
297 begin // axis tbcall_region
298`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_imu_ics_csr is bad"); `endif
299 end // end of tbcall_region
300 // synopsys translate_on
301// vlint flag_system_call on
302 end
303 endcase
304 end
305
306//====================================================================
307// Register violations
308//====================================================================
309//----- reg_acc_vio: imu_error_log_en_reg
310reg imu_error_log_en_reg_acc_vio;
311always @(csrbus_src_bus or daemon_csrbus_wr or
312 imu_error_log_en_reg_addr_decoded or
313 daemon_transaction_in_progress)
314 begin
315 if (daemon_transaction_in_progress | ~imu_error_log_en_reg_addr_decoded)
316 imu_error_log_en_reg_acc_vio = 1'b0;
317 else
318 case ({csrbus_src_bus, daemon_csrbus_wr})
319 // reads
320 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
321 imu_error_log_en_reg_acc_vio = 1'b0;
322 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
323 imu_error_log_en_reg_acc_vio = 1'b0;
324 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
325 imu_error_log_en_reg_acc_vio = 1'b0;
326 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
327 imu_error_log_en_reg_acc_vio = 1'b0;
328 // writes
329 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
330 imu_error_log_en_reg_acc_vio = 1'b0;
331 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
332 imu_error_log_en_reg_acc_vio = 1'b0;
333 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
334 imu_error_log_en_reg_acc_vio = 1'b0;
335 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
336 imu_error_log_en_reg_acc_vio = 1'b0;
337
338 default:
339 begin
340 imu_error_log_en_reg_acc_vio = 1'b0;
341 begin // axis tbcall_region
342 // vlint flag_system_call off
343 // synopsys translate_off
344`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_error_log_en_reg"); `endif
345 // synopsys translate_on
346 // vlint flag_system_call on
347 end // end of tbcall_region
348 end
349 endcase
350 end
351//----- reg_acc_vio: imu_int_en_reg
352reg imu_int_en_reg_acc_vio;
353always @(csrbus_src_bus or daemon_csrbus_wr or
354 imu_int_en_reg_addr_decoded or
355 daemon_transaction_in_progress)
356 begin
357 if (daemon_transaction_in_progress | ~imu_int_en_reg_addr_decoded)
358 imu_int_en_reg_acc_vio = 1'b0;
359 else
360 case ({csrbus_src_bus, daemon_csrbus_wr})
361 // reads
362 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
363 imu_int_en_reg_acc_vio = 1'b0;
364 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
365 imu_int_en_reg_acc_vio = 1'b0;
366 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
367 imu_int_en_reg_acc_vio = 1'b0;
368 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
369 imu_int_en_reg_acc_vio = 1'b0;
370 // writes
371 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
372 imu_int_en_reg_acc_vio = 1'b0;
373 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
374 imu_int_en_reg_acc_vio = 1'b0;
375 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
376 imu_int_en_reg_acc_vio = 1'b0;
377 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
378 imu_int_en_reg_acc_vio = 1'b0;
379
380 default:
381 begin
382 imu_int_en_reg_acc_vio = 1'b0;
383 begin // axis tbcall_region
384 // vlint flag_system_call off
385 // synopsys translate_off
386`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_int_en_reg"); `endif
387 // synopsys translate_on
388 // vlint flag_system_call on
389 end // end of tbcall_region
390 end
391 endcase
392 end
393//----- reg_acc_vio: imu_enabled_error_status_reg
394reg imu_enabled_error_status_reg_acc_vio;
395always @(csrbus_src_bus or daemon_csrbus_wr or
396 imu_enabled_error_status_reg_addr_decoded or
397 daemon_transaction_in_progress)
398 begin
399 if (daemon_transaction_in_progress | ~imu_enabled_error_status_reg_addr_decoded)
400 imu_enabled_error_status_reg_acc_vio = 1'b0;
401 else
402 case ({csrbus_src_bus, daemon_csrbus_wr})
403 // reads
404 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
405 imu_enabled_error_status_reg_acc_vio = 1'b0;
406 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
407 imu_enabled_error_status_reg_acc_vio = 1'b0;
408 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
409 imu_enabled_error_status_reg_acc_vio = 1'b0;
410 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
411 imu_enabled_error_status_reg_acc_vio = 1'b0;
412 // writes
413 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
414 imu_enabled_error_status_reg_acc_vio = 1'b0;
415 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
416 imu_enabled_error_status_reg_acc_vio = 1'b0;
417 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
418 imu_enabled_error_status_reg_acc_vio = 1'b0;
419 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
420 imu_enabled_error_status_reg_acc_vio = 1'b0;
421
422 default:
423 begin
424 imu_enabled_error_status_reg_acc_vio = 1'b0;
425 begin // axis tbcall_region
426 // vlint flag_system_call off
427 // synopsys translate_off
428`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_enabled_error_status_reg"); `endif
429 // synopsys translate_on
430 // vlint flag_system_call on
431 end // end of tbcall_region
432 end
433 endcase
434 end
435//----- reg_acc_vio: imu_logged_error_status_reg
436reg imu_logged_error_status_reg_acc_vio;
437always @(csrbus_src_bus or daemon_csrbus_wr or
438 imu_logged_error_status_reg_rw1c_alias_addr_decoded or
439 imu_logged_error_status_reg_rw1s_alias_addr_decoded or
440 daemon_transaction_in_progress)
441 begin
442 if (daemon_transaction_in_progress |
443 ~ (imu_logged_error_status_reg_rw1c_alias_addr_decoded | imu_logged_error_status_reg_rw1s_alias_addr_decoded))
444 imu_logged_error_status_reg_acc_vio = 1'b0;
445 else
446 case ({csrbus_src_bus, daemon_csrbus_wr})
447 // reads
448 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
449 imu_logged_error_status_reg_acc_vio = 1'b0;
450 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
451 imu_logged_error_status_reg_acc_vio = 1'b0;
452 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
453 imu_logged_error_status_reg_acc_vio = 1'b0;
454 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
455 imu_logged_error_status_reg_acc_vio = 1'b0;
456 // writes
457 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
458 imu_logged_error_status_reg_acc_vio = 1'b0;
459 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
460 imu_logged_error_status_reg_acc_vio = 1'b0;
461 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
462 imu_logged_error_status_reg_acc_vio = 1'b0;
463 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
464 imu_logged_error_status_reg_acc_vio = 1'b0;
465
466 default:
467 begin
468 imu_logged_error_status_reg_acc_vio = 1'b0;
469 begin // axis tbcall_region
470 // vlint flag_system_call off
471 // synopsys translate_off
472`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_logged_error_status_reg_rw1c_alias"); `endif
473 // synopsys translate_on
474 // vlint flag_system_call on
475 end // end of tbcall_region
476 end
477 endcase
478 end
479//----- reg_acc_vio: imu_rds_error_log_reg
480reg imu_rds_error_log_reg_acc_vio;
481always @(csrbus_src_bus or daemon_csrbus_wr or
482 imu_rds_error_log_reg_addr_decoded or
483 daemon_transaction_in_progress)
484 begin
485 if (daemon_transaction_in_progress | ~imu_rds_error_log_reg_addr_decoded)
486 imu_rds_error_log_reg_acc_vio = 1'b0;
487 else
488 case ({csrbus_src_bus, daemon_csrbus_wr})
489 // reads
490 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
491 imu_rds_error_log_reg_acc_vio = 1'b0;
492 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
493 imu_rds_error_log_reg_acc_vio = 1'b0;
494 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
495 imu_rds_error_log_reg_acc_vio = 1'b0;
496 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
497 imu_rds_error_log_reg_acc_vio = 1'b0;
498 // writes
499 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
500 imu_rds_error_log_reg_acc_vio = 1'b0;
501 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
502 imu_rds_error_log_reg_acc_vio = 1'b0;
503 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
504 imu_rds_error_log_reg_acc_vio = 1'b0;
505 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
506 imu_rds_error_log_reg_acc_vio = 1'b0;
507
508 default:
509 begin
510 imu_rds_error_log_reg_acc_vio = 1'b0;
511 begin // axis tbcall_region
512 // vlint flag_system_call off
513 // synopsys translate_off
514`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_rds_error_log_reg"); `endif
515 // synopsys translate_on
516 // vlint flag_system_call on
517 end // end of tbcall_region
518 end
519 endcase
520 end
521//----- reg_acc_vio: imu_scs_error_log_reg
522reg imu_scs_error_log_reg_acc_vio;
523always @(csrbus_src_bus or daemon_csrbus_wr or
524 imu_scs_error_log_reg_addr_decoded or
525 daemon_transaction_in_progress)
526 begin
527 if (daemon_transaction_in_progress | ~imu_scs_error_log_reg_addr_decoded)
528 imu_scs_error_log_reg_acc_vio = 1'b0;
529 else
530 case ({csrbus_src_bus, daemon_csrbus_wr})
531 // reads
532 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
533 imu_scs_error_log_reg_acc_vio = 1'b0;
534 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
535 imu_scs_error_log_reg_acc_vio = 1'b0;
536 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
537 imu_scs_error_log_reg_acc_vio = 1'b0;
538 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
539 imu_scs_error_log_reg_acc_vio = 1'b0;
540 // writes
541 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
542 imu_scs_error_log_reg_acc_vio = 1'b0;
543 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
544 imu_scs_error_log_reg_acc_vio = 1'b0;
545 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
546 imu_scs_error_log_reg_acc_vio = 1'b0;
547 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
548 imu_scs_error_log_reg_acc_vio = 1'b0;
549
550 default:
551 begin
552 imu_scs_error_log_reg_acc_vio = 1'b0;
553 begin // axis tbcall_region
554 // vlint flag_system_call off
555 // synopsys translate_off
556`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_scs_error_log_reg"); `endif
557 // synopsys translate_on
558 // vlint flag_system_call on
559 end // end of tbcall_region
560 end
561 endcase
562 end
563//----- reg_acc_vio: imu_eqs_error_log_reg
564reg imu_eqs_error_log_reg_acc_vio;
565always @(csrbus_src_bus or daemon_csrbus_wr or
566 imu_eqs_error_log_reg_addr_decoded or
567 daemon_transaction_in_progress)
568 begin
569 if (daemon_transaction_in_progress | ~imu_eqs_error_log_reg_addr_decoded)
570 imu_eqs_error_log_reg_acc_vio = 1'b0;
571 else
572 case ({csrbus_src_bus, daemon_csrbus_wr})
573 // reads
574 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
575 imu_eqs_error_log_reg_acc_vio = 1'b0;
576 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
577 imu_eqs_error_log_reg_acc_vio = 1'b0;
578 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
579 imu_eqs_error_log_reg_acc_vio = 1'b0;
580 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
581 imu_eqs_error_log_reg_acc_vio = 1'b0;
582 // writes
583 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
584 imu_eqs_error_log_reg_acc_vio = 1'b0;
585 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
586 imu_eqs_error_log_reg_acc_vio = 1'b0;
587 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
588 imu_eqs_error_log_reg_acc_vio = 1'b0;
589 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
590 imu_eqs_error_log_reg_acc_vio = 1'b0;
591
592 default:
593 begin
594 imu_eqs_error_log_reg_acc_vio = 1'b0;
595 begin // axis tbcall_region
596 // vlint flag_system_call off
597 // synopsys translate_off
598`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_eqs_error_log_reg"); `endif
599 // synopsys translate_on
600 // vlint flag_system_call on
601 end // end of tbcall_region
602 end
603 endcase
604 end
605//----- reg_acc_vio: dmc_interrupt_mask_reg
606reg dmc_interrupt_mask_reg_acc_vio;
607always @(csrbus_src_bus or daemon_csrbus_wr or
608 dmc_interrupt_mask_reg_addr_decoded or
609 daemon_transaction_in_progress)
610 begin
611 if (daemon_transaction_in_progress | ~dmc_interrupt_mask_reg_addr_decoded)
612 dmc_interrupt_mask_reg_acc_vio = 1'b0;
613 else
614 case ({csrbus_src_bus, daemon_csrbus_wr})
615 // reads
616 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
617 dmc_interrupt_mask_reg_acc_vio = 1'b0;
618 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
619 dmc_interrupt_mask_reg_acc_vio = 1'b0;
620 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
621 dmc_interrupt_mask_reg_acc_vio = 1'b0;
622 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
623 dmc_interrupt_mask_reg_acc_vio = 1'b0;
624 // writes
625 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
626 dmc_interrupt_mask_reg_acc_vio = 1'b0;
627 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
628 dmc_interrupt_mask_reg_acc_vio = 1'b0;
629 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
630 dmc_interrupt_mask_reg_acc_vio = 1'b0;
631 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
632 dmc_interrupt_mask_reg_acc_vio = 1'b0;
633
634 default:
635 begin
636 dmc_interrupt_mask_reg_acc_vio = 1'b0;
637 begin // axis tbcall_region
638 // vlint flag_system_call off
639 // synopsys translate_off
640`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_dmc_interrupt_mask_reg"); `endif
641 // synopsys translate_on
642 // vlint flag_system_call on
643 end // end of tbcall_region
644 end
645 endcase
646 end
647//----- reg_acc_vio: dmc_interrupt_status_reg
648reg dmc_interrupt_status_reg_acc_vio;
649always @(csrbus_src_bus or daemon_csrbus_wr or
650 dmc_interrupt_status_reg_addr_decoded or
651 daemon_transaction_in_progress)
652 begin
653 if (daemon_transaction_in_progress | ~dmc_interrupt_status_reg_addr_decoded)
654 dmc_interrupt_status_reg_acc_vio = 1'b0;
655 else
656 case ({csrbus_src_bus, daemon_csrbus_wr})
657 // reads
658 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
659 dmc_interrupt_status_reg_acc_vio = 1'b0;
660 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
661 dmc_interrupt_status_reg_acc_vio = 1'b0;
662 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
663 dmc_interrupt_status_reg_acc_vio = 1'b0;
664 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
665 dmc_interrupt_status_reg_acc_vio = 1'b0;
666 // writes
667 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
668 dmc_interrupt_status_reg_acc_vio = 1'b0;
669 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
670 dmc_interrupt_status_reg_acc_vio = 1'b0;
671 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
672 dmc_interrupt_status_reg_acc_vio = 1'b0;
673 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
674 dmc_interrupt_status_reg_acc_vio = 1'b0;
675
676 default:
677 begin
678 dmc_interrupt_status_reg_acc_vio = 1'b0;
679 begin // axis tbcall_region
680 // vlint flag_system_call off
681 // synopsys translate_off
682`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_dmc_interrupt_status_reg"); `endif
683 // synopsys translate_on
684 // vlint flag_system_call on
685 end // end of tbcall_region
686 end
687 endcase
688 end
689//----- reg_acc_vio: imu_perf_cntrl
690reg imu_perf_cntrl_acc_vio;
691always @(csrbus_src_bus or daemon_csrbus_wr or
692 imu_perf_cntrl_addr_decoded or
693 daemon_transaction_in_progress)
694 begin
695 if (daemon_transaction_in_progress | ~imu_perf_cntrl_addr_decoded)
696 imu_perf_cntrl_acc_vio = 1'b0;
697 else
698 case ({csrbus_src_bus, daemon_csrbus_wr})
699 // reads
700 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
701 imu_perf_cntrl_acc_vio = 1'b0;
702 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
703 imu_perf_cntrl_acc_vio = 1'b0;
704 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
705 imu_perf_cntrl_acc_vio = 1'b0;
706 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
707 imu_perf_cntrl_acc_vio = 1'b0;
708 // writes
709 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
710 imu_perf_cntrl_acc_vio = 1'b0;
711 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
712 imu_perf_cntrl_acc_vio = 1'b0;
713 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
714 imu_perf_cntrl_acc_vio = 1'b0;
715 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
716 imu_perf_cntrl_acc_vio = 1'b0;
717
718 default:
719 begin
720 imu_perf_cntrl_acc_vio = 1'b0;
721 begin // axis tbcall_region
722 // vlint flag_system_call off
723 // synopsys translate_off
724`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_perf_cntrl"); `endif
725 // synopsys translate_on
726 // vlint flag_system_call on
727 end // end of tbcall_region
728 end
729 endcase
730 end
731//----- reg_acc_vio: imu_perf_cnt0
732reg imu_perf_cnt0_acc_vio;
733always @(csrbus_src_bus or daemon_csrbus_wr or
734 imu_perf_cnt0_addr_decoded or
735 daemon_transaction_in_progress)
736 begin
737 if (daemon_transaction_in_progress | ~imu_perf_cnt0_addr_decoded)
738 imu_perf_cnt0_acc_vio = 1'b0;
739 else
740 case ({csrbus_src_bus, daemon_csrbus_wr})
741 // reads
742 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
743 imu_perf_cnt0_acc_vio = 1'b0;
744 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
745 imu_perf_cnt0_acc_vio = 1'b0;
746 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
747 imu_perf_cnt0_acc_vio = 1'b0;
748 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
749 imu_perf_cnt0_acc_vio = 1'b0;
750 // writes
751 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
752 imu_perf_cnt0_acc_vio = 1'b0;
753 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
754 imu_perf_cnt0_acc_vio = 1'b0;
755 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
756 imu_perf_cnt0_acc_vio = 1'b0;
757 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
758 imu_perf_cnt0_acc_vio = 1'b0;
759
760 default:
761 begin
762 imu_perf_cnt0_acc_vio = 1'b0;
763 begin // axis tbcall_region
764 // vlint flag_system_call off
765 // synopsys translate_off
766`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_perf_cnt0"); `endif
767 // synopsys translate_on
768 // vlint flag_system_call on
769 end // end of tbcall_region
770 end
771 endcase
772 end
773//----- reg_acc_vio: imu_perf_cnt1
774reg imu_perf_cnt1_acc_vio;
775always @(csrbus_src_bus or daemon_csrbus_wr or
776 imu_perf_cnt1_addr_decoded or
777 daemon_transaction_in_progress)
778 begin
779 if (daemon_transaction_in_progress | ~imu_perf_cnt1_addr_decoded)
780 imu_perf_cnt1_acc_vio = 1'b0;
781 else
782 case ({csrbus_src_bus, daemon_csrbus_wr})
783 // reads
784 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
785 imu_perf_cnt1_acc_vio = 1'b0;
786 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
787 imu_perf_cnt1_acc_vio = 1'b0;
788 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
789 imu_perf_cnt1_acc_vio = 1'b0;
790 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
791 imu_perf_cnt1_acc_vio = 1'b0;
792 // writes
793 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
794 imu_perf_cnt1_acc_vio = 1'b0;
795 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
796 imu_perf_cnt1_acc_vio = 1'b0;
797 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
798 imu_perf_cnt1_acc_vio = 1'b0;
799 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
800 imu_perf_cnt1_acc_vio = 1'b0;
801
802 default:
803 begin
804 imu_perf_cnt1_acc_vio = 1'b0;
805 begin // axis tbcall_region
806 // vlint flag_system_call off
807 // synopsys translate_off
808`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_imu_perf_cnt1"); `endif
809 // synopsys translate_on
810 // vlint flag_system_call on
811 end // end of tbcall_region
812 end
813 endcase
814 end
815//----- reg_acc_vio: msi_32_addr_reg
816reg msi_32_addr_reg_acc_vio;
817always @(csrbus_src_bus or daemon_csrbus_wr or
818 msi_32_addr_reg_addr_decoded or
819 daemon_transaction_in_progress)
820 begin
821 if (daemon_transaction_in_progress | ~msi_32_addr_reg_addr_decoded)
822 msi_32_addr_reg_acc_vio = 1'b0;
823 else
824 case ({csrbus_src_bus, daemon_csrbus_wr})
825 // reads
826 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
827 msi_32_addr_reg_acc_vio = 1'b0;
828 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
829 msi_32_addr_reg_acc_vio = 1'b0;
830 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
831 msi_32_addr_reg_acc_vio = 1'b0;
832 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
833 msi_32_addr_reg_acc_vio = 1'b0;
834 // writes
835 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
836 msi_32_addr_reg_acc_vio = 1'b0;
837 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
838 msi_32_addr_reg_acc_vio = 1'b0;
839 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
840 msi_32_addr_reg_acc_vio = 1'b0;
841 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
842 msi_32_addr_reg_acc_vio = 1'b0;
843
844 default:
845 begin
846 msi_32_addr_reg_acc_vio = 1'b0;
847 begin // axis tbcall_region
848 // vlint flag_system_call off
849 // synopsys translate_off
850`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_msi_32_addr_reg"); `endif
851 // synopsys translate_on
852 // vlint flag_system_call on
853 end // end of tbcall_region
854 end
855 endcase
856 end
857//----- reg_acc_vio: msi_64_addr_reg
858reg msi_64_addr_reg_acc_vio;
859always @(csrbus_src_bus or daemon_csrbus_wr or
860 msi_64_addr_reg_addr_decoded or
861 daemon_transaction_in_progress)
862 begin
863 if (daemon_transaction_in_progress | ~msi_64_addr_reg_addr_decoded)
864 msi_64_addr_reg_acc_vio = 1'b0;
865 else
866 case ({csrbus_src_bus, daemon_csrbus_wr})
867 // reads
868 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
869 msi_64_addr_reg_acc_vio = 1'b0;
870 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
871 msi_64_addr_reg_acc_vio = 1'b0;
872 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
873 msi_64_addr_reg_acc_vio = 1'b0;
874 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
875 msi_64_addr_reg_acc_vio = 1'b0;
876 // writes
877 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
878 msi_64_addr_reg_acc_vio = 1'b0;
879 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
880 msi_64_addr_reg_acc_vio = 1'b0;
881 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
882 msi_64_addr_reg_acc_vio = 1'b0;
883 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
884 msi_64_addr_reg_acc_vio = 1'b0;
885
886 default:
887 begin
888 msi_64_addr_reg_acc_vio = 1'b0;
889 begin // axis tbcall_region
890 // vlint flag_system_call off
891 // synopsys translate_off
892`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_msi_64_addr_reg"); `endif
893 // synopsys translate_on
894 // vlint flag_system_call on
895 end // end of tbcall_region
896 end
897 endcase
898 end
899//----- reg_acc_vio: mem_64_pcie_offset_reg
900reg mem_64_pcie_offset_reg_acc_vio;
901always @(csrbus_src_bus or daemon_csrbus_wr or
902 mem_64_pcie_offset_reg_addr_decoded or
903 daemon_transaction_in_progress)
904 begin
905 if (daemon_transaction_in_progress | ~mem_64_pcie_offset_reg_addr_decoded)
906 mem_64_pcie_offset_reg_acc_vio = 1'b0;
907 else
908 case ({csrbus_src_bus, daemon_csrbus_wr})
909 // reads
910 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
911 mem_64_pcie_offset_reg_acc_vio = 1'b0;
912 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
913 mem_64_pcie_offset_reg_acc_vio = 1'b0;
914 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
915 mem_64_pcie_offset_reg_acc_vio = 1'b0;
916 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
917 mem_64_pcie_offset_reg_acc_vio = 1'b0;
918 // writes
919 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
920 mem_64_pcie_offset_reg_acc_vio = 1'b0;
921 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
922 mem_64_pcie_offset_reg_acc_vio = 1'b0;
923 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
924 mem_64_pcie_offset_reg_acc_vio = 1'b0;
925 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
926 mem_64_pcie_offset_reg_acc_vio = 1'b0;
927
928 default:
929 begin
930 mem_64_pcie_offset_reg_acc_vio = 1'b0;
931 begin // axis tbcall_region
932 // vlint flag_system_call off
933 // synopsys translate_off
934`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_ics_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_ics_csr_a_mem_64_pcie_offset_reg"); `endif
935 // synopsys translate_on
936 // vlint flag_system_call on
937 end // end of tbcall_region
938 end
939 endcase
940 end
941
942//====================================================================
943// Status: daemon_csrbus_mapped / csrbus_acc_vio
944//====================================================================
945//----- OUTPUT: daemon_csrbus_mapped
946assign daemon_csrbus_mapped = clocked_valid_pulse &
947 (
948 imu_error_log_en_reg_addr_decoded |
949 imu_int_en_reg_addr_decoded |
950 imu_enabled_error_status_reg_addr_decoded |
951 imu_logged_error_status_reg_rw1s_alias_addr_decoded |
952 imu_logged_error_status_reg_rw1c_alias_addr_decoded |
953 imu_rds_error_log_reg_addr_decoded |
954 imu_scs_error_log_reg_addr_decoded |
955 imu_eqs_error_log_reg_addr_decoded |
956 dmc_interrupt_mask_reg_addr_decoded |
957 dmc_interrupt_status_reg_addr_decoded |
958 imu_perf_cntrl_addr_decoded |
959 imu_perf_cnt0_addr_decoded |
960 imu_perf_cnt1_addr_decoded |
961 msi_32_addr_reg_addr_decoded |
962 msi_64_addr_reg_addr_decoded |
963 mem_64_pcie_offset_reg_addr_decoded
964 );
965
966
967// daemon_csrbus_mapped gets asserted after fixed number of cycles
968// after daemon_csrbus_valid become high
969/* 0in assert_together -name mapped_after_valid
970 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1))
971 -follower $0in_rising_edge(daemon_csrbus_mapped)
972 -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid")
973 -module dmu_imu_ics_addr_decode
974 -clock clk
975 -active $0in_rising_edge(daemon_csrbus_mapped)
976*/
977
978// daemon_csrbus_mapped is a pulse
979/* 0in assert_timer -name daemon_csrbus_mapped_pulse
980 -var daemon_csrbus_mapped -max 1
981 -message "daemon_csrbus_mapped pulse length is not 1"
982 -module dmu_imu_ics_addr_decode
983 -clock clk
984*/
985//----- OUTPUT: csrbus_acc_vio
986assign csrbus_acc_vio = clocked_valid_pulse &
987 imu_error_log_en_reg_acc_vio |
988 imu_int_en_reg_acc_vio |
989 imu_enabled_error_status_reg_acc_vio |
990 imu_logged_error_status_reg_acc_vio |
991 imu_rds_error_log_reg_acc_vio |
992 imu_scs_error_log_reg_acc_vio |
993 imu_eqs_error_log_reg_acc_vio |
994 dmc_interrupt_mask_reg_acc_vio |
995 dmc_interrupt_status_reg_acc_vio |
996 imu_perf_cntrl_acc_vio |
997 imu_perf_cnt0_acc_vio |
998 imu_perf_cnt1_acc_vio |
999 msi_32_addr_reg_acc_vio |
1000 msi_64_addr_reg_acc_vio |
1001 mem_64_pcie_offset_reg_acc_vio;
1002
1003//====================================================================
1004// Select
1005//====================================================================
1006always @(posedge clk)
1007 begin
1008 if(~rst_l)
1009 begin
1010 imu_error_log_en_reg_select_pulse <= 1'b0;
1011 imu_int_en_reg_select_pulse <= 1'b0;
1012 imu_enabled_error_status_reg_select <= 1'b0;
1013 imu_logged_error_status_reg_select_pulse <= 1'b0;
1014 imu_rds_error_log_reg_select_pulse <= 1'b0;
1015 imu_scs_error_log_reg_select_pulse <= 1'b0;
1016 imu_eqs_error_log_reg_select_pulse <= 1'b0;
1017 dmc_interrupt_mask_reg_select_pulse <= 1'b0;
1018 dmc_interrupt_status_reg_select <= 1'b0;
1019 imu_perf_cntrl_select_pulse <= 1'b0;
1020 imu_perf_cnt0_select_pulse <= 1'b0;
1021 imu_perf_cnt1_select_pulse <= 1'b0;
1022 msi_32_addr_reg_select_pulse <= 1'b0;
1023 msi_64_addr_reg_select_pulse <= 1'b0;
1024 mem_64_pcie_offset_reg_select_pulse <= 1'b0;
1025 end
1026 else
1027 begin
1028 imu_error_log_en_reg_select_pulse <=
1029 ~imu_error_log_en_reg_acc_vio &
1030 clocked_valid_pulse &
1031 imu_error_log_en_reg_addr_decoded;
1032
1033 imu_int_en_reg_select_pulse <=
1034 ~imu_int_en_reg_acc_vio &
1035 clocked_valid_pulse &
1036 imu_int_en_reg_addr_decoded;
1037
1038 imu_enabled_error_status_reg_select <=
1039 ~imu_enabled_error_status_reg_acc_vio &
1040 imu_enabled_error_status_reg_addr_decoded;
1041
1042 imu_logged_error_status_reg_select_pulse <=
1043 ~imu_logged_error_status_reg_acc_vio &
1044 clocked_valid_pulse &
1045 (
1046 imu_logged_error_status_reg_rw1c_alias_addr_decoded |
1047 imu_logged_error_status_reg_rw1s_alias_addr_decoded
1048 );
1049
1050 imu_rds_error_log_reg_select_pulse <=
1051 ~imu_rds_error_log_reg_acc_vio &
1052 clocked_valid_pulse &
1053 imu_rds_error_log_reg_addr_decoded;
1054
1055 imu_scs_error_log_reg_select_pulse <=
1056 ~imu_scs_error_log_reg_acc_vio &
1057 clocked_valid_pulse &
1058 imu_scs_error_log_reg_addr_decoded;
1059
1060 imu_eqs_error_log_reg_select_pulse <=
1061 ~imu_eqs_error_log_reg_acc_vio &
1062 clocked_valid_pulse &
1063 imu_eqs_error_log_reg_addr_decoded;
1064
1065 dmc_interrupt_mask_reg_select_pulse <=
1066 ~dmc_interrupt_mask_reg_acc_vio &
1067 clocked_valid_pulse &
1068 dmc_interrupt_mask_reg_addr_decoded;
1069
1070 dmc_interrupt_status_reg_select <=
1071 ~dmc_interrupt_status_reg_acc_vio &
1072 dmc_interrupt_status_reg_addr_decoded;
1073
1074 imu_perf_cntrl_select_pulse <=
1075 ~imu_perf_cntrl_acc_vio &
1076 clocked_valid_pulse &
1077 imu_perf_cntrl_addr_decoded;
1078
1079 imu_perf_cnt0_select_pulse <=
1080 ~imu_perf_cnt0_acc_vio &
1081 clocked_valid_pulse &
1082 imu_perf_cnt0_addr_decoded;
1083
1084 imu_perf_cnt1_select_pulse <=
1085 ~imu_perf_cnt1_acc_vio &
1086 clocked_valid_pulse &
1087 imu_perf_cnt1_addr_decoded;
1088
1089 msi_32_addr_reg_select_pulse <=
1090 ~msi_32_addr_reg_acc_vio &
1091 clocked_valid_pulse &
1092 msi_32_addr_reg_addr_decoded;
1093
1094 msi_64_addr_reg_select_pulse <=
1095 ~msi_64_addr_reg_acc_vio &
1096 clocked_valid_pulse &
1097 msi_64_addr_reg_addr_decoded;
1098
1099 mem_64_pcie_offset_reg_select_pulse <=
1100 ~mem_64_pcie_offset_reg_acc_vio &
1101 clocked_valid_pulse &
1102 mem_64_pcie_offset_reg_addr_decoded;
1103
1104 end
1105 end
1106
1107//====================================================================
1108// daemon_csrbus_wr / daemon_csrbus_wr_data
1109//====================================================================
1110always @(posedge clk)
1111 begin
1112 if(~rst_l)
1113 begin
1114 daemon_csrbus_wr_out <= 1'b0;
1115 daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0;
1116 end
1117 else
1118 begin
1119 daemon_csrbus_wr_out <= daemon_csrbus_wr;
1120 daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data;
1121 end
1122 end
1123
1124//====================================================================
1125// Cycle Counter: Used for ExtReadTiming / ExtWriteTiming
1126//====================================================================
1127
1128//====================================================================
1129// Alias
1130//====================================================================
1131assign imu_logged_error_status_reg_rw1c_alias=
1132 imu_logged_error_status_reg_rw1c_alias_addr_decoded;
1133
1134assign imu_logged_error_status_reg_rw1s_alias=
1135 imu_logged_error_status_reg_rw1s_alias_addr_decoded;
1136
1137
1138//====================================================================
1139// OUTPUT: daemon_csrbus_done (pipelining)
1140//====================================================================
1141//----- DONE for internal/extern registers
1142reg stage_1_daemon_csrbus_done_internal_0;
1143reg stage_2_daemon_csrbus_done_internal_0;
1144
1145always @(posedge clk)
1146 begin
1147 if(~rst_l)
1148 begin
1149 stage_1_daemon_csrbus_done_internal_0 <= 1'b0;
1150 end
1151 else
1152 begin
1153 stage_1_daemon_csrbus_done_internal_0 <=
1154 imu_error_log_en_reg_select_pulse |
1155 imu_int_en_reg_select_pulse |
1156 imu_logged_error_status_reg_select_pulse |
1157 imu_rds_error_log_reg_select_pulse |
1158 imu_scs_error_log_reg_select_pulse |
1159 imu_eqs_error_log_reg_select_pulse |
1160 dmc_interrupt_mask_reg_select_pulse |
1161 imu_perf_cntrl_select_pulse |
1162 imu_perf_cnt0_select_pulse |
1163 imu_perf_cnt1_select_pulse |
1164 msi_32_addr_reg_select_pulse |
1165 msi_64_addr_reg_select_pulse |
1166 mem_64_pcie_offset_reg_select_pulse |
1167 imu_enabled_error_status_reg_select & clocked_valid_pulse |
1168 dmc_interrupt_status_reg_select & clocked_valid_pulse;
1169 end
1170 if(~rst_l)
1171 begin
1172 stage_2_daemon_csrbus_done_internal_0 <= 1'b0;
1173 end
1174 else
1175 begin
1176 stage_2_daemon_csrbus_done_internal_0 <=
1177 stage_1_daemon_csrbus_done_internal_0;
1178 end
1179 end
1180
1181//----- OUTPUT: daemon_csrbus_done
1182assign daemon_csrbus_done = daemon_csrbus_valid &
1183 (
1184 stage_2_daemon_csrbus_done_internal_0
1185 );
1186
1187// daemon_csrbus_done gets asserted only when csrbus_valid is high
1188/* 0in assert -name daemon_csrbus_done_high
1189 -var daemon_csrbus_valid -active daemon_csrbus_done
1190 -message "csrbus_done got asserted while csrbus_valid is low"
1191 -module dmu_imu_ics_addr_decode
1192 -clock clk
1193*/
1194
1195// daemon_csrbus_done is a pulse
1196/* 0in assert_timer -name daemon_csrbus_done_pulse
1197 -var daemon_csrbus_done -max 1
1198 -message "csrbus_done pulse length is not 1"
1199 -module dmu_imu_ics_addr_decode
1200 -clock clk
1201*/
1202
1203endmodule // dmu_imu_ics_addr_decode
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