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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_ics_csr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_ics_csr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_ics_csr
36 (
37 clk,
38 csrbus_addr,
39 csrbus_wr_data,
40 csrbus_wr,
41 csrbus_valid,
42 csrbus_mapped,
43 csrbus_done,
44 csrbus_read_data,
45 por_l,
46 rst_l,
47 csrbus_src_bus,
48 csrbus_acc_vio,
49 instance_id,
50 imu_error_log_en_reg_spare_log_en_hw_read,
51 imu_error_log_en_reg_eq_over_log_en_hw_read,
52 imu_error_log_en_reg_eq_not_en_log_en_hw_read,
53 imu_error_log_en_reg_msi_mal_err_log_en_hw_read,
54 imu_error_log_en_reg_msi_par_err_log_en_hw_read,
55 imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read,
56 imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read,
57 imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read,
58 imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read,
59 imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read,
60 imu_error_log_en_reg_msi_not_en_log_en_hw_read,
61 imu_int_en_reg_spare_s_int_en_hw_read,
62 imu_int_en_reg_eq_over_s_int_en_hw_read,
63 imu_int_en_reg_eq_not_en_s_int_en_hw_read,
64 imu_int_en_reg_msi_mal_err_s_int_en_hw_read,
65 imu_int_en_reg_msi_par_err_s_int_en_hw_read,
66 imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read,
67 imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read,
68 imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read,
69 imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read,
70 imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read,
71 imu_int_en_reg_msi_not_en_s_int_en_hw_read,
72 imu_int_en_reg_spare_p_int_en_hw_read,
73 imu_int_en_reg_eq_over_p_int_en_hw_read,
74 imu_int_en_reg_eq_not_en_p_int_en_hw_read,
75 imu_int_en_reg_msi_mal_err_p_int_en_hw_read,
76 imu_int_en_reg_msi_par_err_p_int_en_hw_read,
77 imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read,
78 imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read,
79 imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read,
80 imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read,
81 imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read,
82 imu_int_en_reg_msi_not_en_p_int_en_hw_read,
83 imu_enabled_error_status_reg_spare_s_ext_read_data,
84 imu_enabled_error_status_reg_eq_over_s_ext_read_data,
85 imu_enabled_error_status_reg_eq_not_en_s_ext_read_data,
86 imu_enabled_error_status_reg_msi_mal_err_s_ext_read_data,
87 imu_enabled_error_status_reg_msi_par_err_s_ext_read_data,
88 imu_enabled_error_status_reg_pmeack_mes_not_en_s_ext_read_data,
89 imu_enabled_error_status_reg_pmpme_mes_not_en_s_ext_read_data,
90 imu_enabled_error_status_reg_fatal_mes_not_en_s_ext_read_data,
91 imu_enabled_error_status_reg_nonfatal_mes_not_en_s_ext_read_data,
92 imu_enabled_error_status_reg_cor_mes_not_en_s_ext_read_data,
93 imu_enabled_error_status_reg_msi_not_en_s_ext_read_data,
94 imu_enabled_error_status_reg_spare_p_ext_read_data,
95 imu_enabled_error_status_reg_eq_over_p_ext_read_data,
96 imu_enabled_error_status_reg_eq_not_en_p_ext_read_data,
97 imu_enabled_error_status_reg_msi_mal_err_p_ext_read_data,
98 imu_enabled_error_status_reg_msi_par_err_p_ext_read_data,
99 imu_enabled_error_status_reg_pmeack_mes_not_en_p_ext_read_data,
100 imu_enabled_error_status_reg_pmpme_mes_not_en_p_ext_read_data,
101 imu_enabled_error_status_reg_fatal_mes_not_en_p_ext_read_data,
102 imu_enabled_error_status_reg_nonfatal_mes_not_en_p_ext_read_data,
103 imu_enabled_error_status_reg_cor_mes_not_en_p_ext_read_data,
104 imu_enabled_error_status_reg_msi_not_en_p_ext_read_data,
105 imu_logged_error_status_reg_spare_s_hw_set,
106 imu_logged_error_status_reg_spare_s_hw_read,
107 imu_logged_error_status_reg_eq_over_s_hw_set,
108 imu_logged_error_status_reg_eq_over_s_hw_read,
109 imu_logged_error_status_reg_eq_not_en_s_hw_set,
110 imu_logged_error_status_reg_eq_not_en_s_hw_read,
111 imu_logged_error_status_reg_msi_mal_err_s_hw_set,
112 imu_logged_error_status_reg_msi_mal_err_s_hw_read,
113 imu_logged_error_status_reg_msi_par_err_s_hw_set,
114 imu_logged_error_status_reg_msi_par_err_s_hw_read,
115 imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set,
116 imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read,
117 imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set,
118 imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read,
119 imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set,
120 imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read,
121 imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set,
122 imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read,
123 imu_logged_error_status_reg_cor_mes_not_en_s_hw_set,
124 imu_logged_error_status_reg_cor_mes_not_en_s_hw_read,
125 imu_logged_error_status_reg_msi_not_en_s_hw_set,
126 imu_logged_error_status_reg_msi_not_en_s_hw_read,
127 imu_logged_error_status_reg_spare_p_hw_set,
128 imu_logged_error_status_reg_spare_p_hw_read,
129 imu_logged_error_status_reg_eq_over_p_hw_set,
130 imu_logged_error_status_reg_eq_over_p_hw_read,
131 imu_logged_error_status_reg_eq_not_en_p_hw_set,
132 imu_logged_error_status_reg_eq_not_en_p_hw_read,
133 imu_logged_error_status_reg_msi_mal_err_p_hw_set,
134 imu_logged_error_status_reg_msi_mal_err_p_hw_read,
135 imu_logged_error_status_reg_msi_par_err_p_hw_set,
136 imu_logged_error_status_reg_msi_par_err_p_hw_read,
137 imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set,
138 imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read,
139 imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set,
140 imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read,
141 imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set,
142 imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read,
143 imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set,
144 imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read,
145 imu_logged_error_status_reg_cor_mes_not_en_p_hw_set,
146 imu_logged_error_status_reg_cor_mes_not_en_p_hw_read,
147 imu_logged_error_status_reg_msi_not_en_p_hw_set,
148 imu_logged_error_status_reg_msi_not_en_p_hw_read,
149 imu_rds_error_log_reg_hw_ld,
150 imu_rds_error_log_reg_hw_write,
151 imu_scs_error_log_reg_hw_ld,
152 imu_scs_error_log_reg_hw_write,
153 imu_eqs_error_log_reg_hw_ld,
154 imu_eqs_error_log_reg_hw_write,
155 dmc_interrupt_mask_reg_dmc_hw_read,
156 dmc_interrupt_mask_reg_debug_trig_en_hw_read,
157 dmc_interrupt_mask_reg_mmu_hw_read,
158 dmc_interrupt_mask_reg_imu_hw_read,
159 dmc_interrupt_status_reg_mmu_ext_read_data,
160 dmc_interrupt_status_reg_imu_ext_read_data,
161 imu_perf_cntrl_sel1_hw_read,
162 imu_perf_cntrl_sel0_hw_read,
163 imu_perf_cnt0_cnt_hw_write,
164 imu_perf_cnt0_cnt_hw_read,
165 imu_perf_cnt1_cnt_hw_write,
166 imu_perf_cnt1_cnt_hw_read,
167 msi_32_addr_reg_addr_hw_read,
168 msi_64_addr_reg_addr_hw_read,
169 mem_64_pcie_offset_reg_addr_hw_read,
170 mem_64_pcie_offset_reg_spare_control_load_7_hw_ld,
171 mem_64_pcie_offset_reg_spare_control_load_7_hw_write,
172 mem_64_pcie_offset_reg_spare_control_load_7_hw_read,
173 mem_64_pcie_offset_reg_spare_control_load_6_hw_ld,
174 mem_64_pcie_offset_reg_spare_control_load_6_hw_write,
175 mem_64_pcie_offset_reg_spare_control_load_6_hw_read,
176 mem_64_pcie_offset_reg_spare_control_load_5_hw_ld,
177 mem_64_pcie_offset_reg_spare_control_load_5_hw_write,
178 mem_64_pcie_offset_reg_spare_control_load_5_hw_read,
179 mem_64_pcie_offset_reg_spare_control_load_4_hw_ld,
180 mem_64_pcie_offset_reg_spare_control_load_4_hw_write,
181 mem_64_pcie_offset_reg_spare_control_load_4_hw_read,
182 mem_64_pcie_offset_reg_spare_control_load_3_hw_ld,
183 mem_64_pcie_offset_reg_spare_control_load_3_hw_write,
184 mem_64_pcie_offset_reg_spare_control_load_3_hw_read,
185 mem_64_pcie_offset_reg_spare_control_load_2_hw_ld,
186 mem_64_pcie_offset_reg_spare_control_load_2_hw_write,
187 mem_64_pcie_offset_reg_spare_control_load_2_hw_read,
188 mem_64_pcie_offset_reg_spare_control_load_1_hw_ld,
189 mem_64_pcie_offset_reg_spare_control_load_1_hw_write,
190 mem_64_pcie_offset_reg_spare_control_load_1_hw_read,
191 mem_64_pcie_offset_reg_spare_control_load_0_hw_ld,
192 mem_64_pcie_offset_reg_spare_control_load_0_hw_write,
193 mem_64_pcie_offset_reg_spare_control_load_0_hw_read,
194 mem_64_pcie_offset_reg_spare_control_hw_write,
195 mem_64_pcie_offset_reg_spare_control_hw_read,
196 mem_64_pcie_offset_reg_spare_status_hw_read
197 );
198
199//====================================================
200// Polarity declarations
201//====================================================
202input clk; // Clock signal
203input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
204input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
205input csrbus_wr; // Read/Write signal
206input csrbus_valid; // Valid address
207output csrbus_mapped; // Address is mapped
208output csrbus_done; // Operation is done
209output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
210input por_l; // Reset signal
211input rst_l; // Reset signal
212input [1:0] csrbus_src_bus; // Source bus
213output csrbus_acc_vio; // Violation signal
214input instance_id; // Instance ID
215output [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read;
216 // This signal provides the current value of
217 // imu_error_log_en_reg_spare_log_en.
218output imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the
219 // current value of
220 // imu_error_log_en_reg_eq_over_log_en.
221output imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides
222 // the current value of
223 // imu_error_log_en_reg_eq_not_en_log_en.
224output imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides
225 // the current value of
226 // imu_error_log_en_reg_msi_mal_err_log_en.
227output imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides
228 // the current value of
229 // imu_error_log_en_reg_msi_par_err_log_en.
230output imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal
231 // provides the
232 // current value
233 // of
234 // imu_error_log_en_reg_pmeack_mes_not_en_log_en.
235output imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal
236 // provides the
237 // current value
238 // of
239 // imu_error_log_en_reg_pmpme_mes_not_en_log_en.
240output imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal
241 // provides the
242 // current value
243 // of
244 // imu_error_log_en_reg_fatal_mes_not_en_log_en.
245output imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal
246 // provides the
247 // current
248 // value of
249 // imu_error_log_en_reg_nonfatal_mes_not_en_log_en.
250output imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal
251 // provides the
252 // current value of
253 // imu_error_log_en_reg_cor_mes_not_en_log_en.
254output imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides
255 // the current value of
256 // imu_error_log_en_reg_msi_not_en_log_en.
257output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC] imu_int_en_reg_spare_s_int_en_hw_read;
258 // This signal provides the current value of imu_int_en_reg_spare_s_int_en.
259output imu_int_en_reg_eq_over_s_int_en_hw_read; // This signal provides the
260 // current value of
261 // imu_int_en_reg_eq_over_s_int_en.
262output imu_int_en_reg_eq_not_en_s_int_en_hw_read; // This signal provides the
263 // current value of
264 // imu_int_en_reg_eq_not_en_s_int_en.
265output imu_int_en_reg_msi_mal_err_s_int_en_hw_read; // This signal provides the
266 // current value of
267 // imu_int_en_reg_msi_mal_err_s_int_en.
268output imu_int_en_reg_msi_par_err_s_int_en_hw_read; // This signal provides the
269 // current value of
270 // imu_int_en_reg_msi_par_err_s_int_en.
271output imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read; // This signal
272 // provides the
273 // current value of
274 // imu_int_en_reg_pmeack_mes_not_en_s_int_en.
275output imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read; // This signal
276 // provides the
277 // current value of
278 // imu_int_en_reg_pmpme_mes_not_en_s_int_en.
279output imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read; // This signal
280 // provides the
281 // current value of
282 // imu_int_en_reg_fatal_mes_not_en_s_int_en.
283output imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read; // This signal
284 // provides the
285 // current value of
286 // imu_int_en_reg_nonfatal_mes_not_en_s_int_en.
287output imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read; // This signal provides
288 // the current value of
289 // imu_int_en_reg_cor_mes_not_en_s_int_en.
290output imu_int_en_reg_msi_not_en_s_int_en_hw_read; // This signal provides the
291 // current value of
292 // imu_int_en_reg_msi_not_en_s_int_en.
293output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC] imu_int_en_reg_spare_p_int_en_hw_read;
294 // This signal provides the current value of imu_int_en_reg_spare_p_int_en.
295output imu_int_en_reg_eq_over_p_int_en_hw_read; // This signal provides the
296 // current value of
297 // imu_int_en_reg_eq_over_p_int_en.
298output imu_int_en_reg_eq_not_en_p_int_en_hw_read; // This signal provides the
299 // current value of
300 // imu_int_en_reg_eq_not_en_p_int_en.
301output imu_int_en_reg_msi_mal_err_p_int_en_hw_read; // This signal provides the
302 // current value of
303 // imu_int_en_reg_msi_mal_err_p_int_en.
304output imu_int_en_reg_msi_par_err_p_int_en_hw_read; // This signal provides the
305 // current value of
306 // imu_int_en_reg_msi_par_err_p_int_en.
307output imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read; // This signal
308 // provides the
309 // current value of
310 // imu_int_en_reg_pmeack_mes_not_en_p_int_en.
311output imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read; // This signal
312 // provides the
313 // current value of
314 // imu_int_en_reg_pmpme_mes_not_en_p_int_en.
315output imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read; // This signal
316 // provides the
317 // current value of
318 // imu_int_en_reg_fatal_mes_not_en_p_int_en.
319output imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read; // This signal
320 // provides the
321 // current value of
322 // imu_int_en_reg_nonfatal_mes_not_en_p_int_en.
323output imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read; // This signal provides
324 // the current value of
325 // imu_int_en_reg_cor_mes_not_en_p_int_en.
326output imu_int_en_reg_msi_not_en_p_int_en_hw_read; // This signal provides the
327 // current value of
328 // imu_int_en_reg_msi_not_en_p_int_en.
329input [4:0] imu_enabled_error_status_reg_spare_s_ext_read_data; // Ext read
330 // data
331 // (decode)
332input [0:0] imu_enabled_error_status_reg_eq_over_s_ext_read_data;
333 // Ext read data (decode)
334input [0:0] imu_enabled_error_status_reg_eq_not_en_s_ext_read_data;
335 // Ext read data (decode)
336input [0:0] imu_enabled_error_status_reg_msi_mal_err_s_ext_read_data;
337 // Ext read data (decode)
338input [0:0] imu_enabled_error_status_reg_msi_par_err_s_ext_read_data;
339 // Ext read data (decode)
340input [0:0] imu_enabled_error_status_reg_pmeack_mes_not_en_s_ext_read_data;
341 // Ext read data (decode)
342input [0:0] imu_enabled_error_status_reg_pmpme_mes_not_en_s_ext_read_data;
343 // Ext read data (decode)
344input [0:0] imu_enabled_error_status_reg_fatal_mes_not_en_s_ext_read_data;
345 // Ext read data (decode)
346input [0:0] imu_enabled_error_status_reg_nonfatal_mes_not_en_s_ext_read_data;
347 // Ext read data (decode)
348input [0:0] imu_enabled_error_status_reg_cor_mes_not_en_s_ext_read_data;
349 // Ext read data (decode)
350input [0:0] imu_enabled_error_status_reg_msi_not_en_s_ext_read_data;
351 // Ext read data (decode)
352input [4:0] imu_enabled_error_status_reg_spare_p_ext_read_data; // Ext read
353 // data
354 // (decode)
355input [0:0] imu_enabled_error_status_reg_eq_over_p_ext_read_data;
356 // Ext read data (decode)
357input [0:0] imu_enabled_error_status_reg_eq_not_en_p_ext_read_data;
358 // Ext read data (decode)
359input [0:0] imu_enabled_error_status_reg_msi_mal_err_p_ext_read_data;
360 // Ext read data (decode)
361input [0:0] imu_enabled_error_status_reg_msi_par_err_p_ext_read_data;
362 // Ext read data (decode)
363input [0:0] imu_enabled_error_status_reg_pmeack_mes_not_en_p_ext_read_data;
364 // Ext read data (decode)
365input [0:0] imu_enabled_error_status_reg_pmpme_mes_not_en_p_ext_read_data;
366 // Ext read data (decode)
367input [0:0] imu_enabled_error_status_reg_fatal_mes_not_en_p_ext_read_data;
368 // Ext read data (decode)
369input [0:0] imu_enabled_error_status_reg_nonfatal_mes_not_en_p_ext_read_data;
370 // Ext read data (decode)
371input [0:0] imu_enabled_error_status_reg_cor_mes_not_en_p_ext_read_data;
372 // Ext read data (decode)
373input [0:0] imu_enabled_error_status_reg_msi_not_en_p_ext_read_data;
374 // Ext read data (decode)
375input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC]
376 imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for
377 // imu_logged_error_status_reg_spare_s.
378 // When set
379 // imu_logged_error_status_reg
380 // will be set to one.
381output [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC]
382 imu_logged_error_status_reg_spare_s_hw_read; // This signal provides the
383 // current value of
384 // imu_logged_error_status_reg_spare_s.
385input imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for
386 // imu_logged_error_status_reg_eq_over_s.
387 // When set
388 // imu_logged_error_status_reg
389 // will be set to one.
390output imu_logged_error_status_reg_eq_over_s_hw_read; // This signal provides
391 // the current value of
392 // imu_logged_error_status_reg_eq_over_s.
393input imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal
394 // for
395 // imu_logged_error_status_reg_eq_not_en_s.
396 // When set
397 // imu_logged_error_status_reg
398 // will be set to one.
399output imu_logged_error_status_reg_eq_not_en_s_hw_read; // This signal provides
400 // the current value of
401 // imu_logged_error_status_reg_eq_not_en_s.
402input imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal
403 // for
404 // imu_logged_error_status_reg_msi_mal_err_s.
405 // When set
406 // imu_logged_error_status_reg
407 // will be set to one.
408output imu_logged_error_status_reg_msi_mal_err_s_hw_read; // This signal
409 // provides the
410 // current value of
411 // imu_logged_error_status_reg_msi_mal_err_s.
412input imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal
413 // for
414 // imu_logged_error_status_reg_msi_par_err_s.
415 // When set
416 // imu_logged_error_status_reg
417 // will be set to one.
418output imu_logged_error_status_reg_msi_par_err_s_hw_read; // This signal
419 // provides the
420 // current value of
421 // imu_logged_error_status_reg_msi_par_err_s.
422input imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set
423 // signal for
424 // imu_logged_error_status_reg_pmeack_mes_not_en_s.
425 // When set
426 // imu_logged_error_status_reg
427 // will be set
428 // to one.
429output imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read; // This signal
430 // provides the
431 // current
432 // value of
433 // imu_logged_error_status_reg_pmeack_mes_not_en_s.
434input imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set
435 // signal for
436 // imu_logged_error_status_reg_pmpme_mes_not_en_s.
437 // When set
438 // imu_logged_error_status_reg
439 // will be set to
440 // one.
441output imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read; // This signal
442 // provides the
443 // current value
444 // of
445 // imu_logged_error_status_reg_pmpme_mes_not_en_s.
446input imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set
447 // signal for
448 // imu_logged_error_status_reg_fatal_mes_not_en_s.
449 // When set
450 // imu_logged_error_status_reg
451 // will be set to
452 // one.
453output imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read; // This signal
454 // provides the
455 // current value
456 // of
457 // imu_logged_error_status_reg_fatal_mes_not_en_s.
458input imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware
459 // set signal
460 // for
461 // imu_logged_error_status_reg_nonfatal_mes_not_en_s.
462 // When set
463 // imu_logged_error_status_reg
464 // will be set
465 // to one.
466output imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read;
467 // This signal provides the current value of
468 // imu_logged_error_status_reg_nonfatal_mes_not_en_s.
469input imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set
470 // signal for
471 // imu_logged_error_status_reg_cor_mes_not_en_s.
472 // When set
473 // imu_logged_error_status_reg
474 // will be set to
475 // one.
476output imu_logged_error_status_reg_cor_mes_not_en_s_hw_read; // This signal
477 // provides the
478 // current value
479 // of
480 // imu_logged_error_status_reg_cor_mes_not_en_s.
481input imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal
482 // for
483 // imu_logged_error_status_reg_msi_not_en_s.
484 // When set
485 // imu_logged_error_status_reg
486 // will be set to one.
487output imu_logged_error_status_reg_msi_not_en_s_hw_read; // This signal
488 // provides the
489 // current value of
490 // imu_logged_error_status_reg_msi_not_en_s.
491input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC]
492 imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for
493 // imu_logged_error_status_reg_spare_p.
494 // When set
495 // imu_logged_error_status_reg
496 // will be set to one.
497output [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC]
498 imu_logged_error_status_reg_spare_p_hw_read; // This signal provides the
499 // current value of
500 // imu_logged_error_status_reg_spare_p.
501input imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for
502 // imu_logged_error_status_reg_eq_over_p.
503 // When set
504 // imu_logged_error_status_reg
505 // will be set to one.
506output imu_logged_error_status_reg_eq_over_p_hw_read; // This signal provides
507 // the current value of
508 // imu_logged_error_status_reg_eq_over_p.
509input imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal
510 // for
511 // imu_logged_error_status_reg_eq_not_en_p.
512 // When set
513 // imu_logged_error_status_reg
514 // will be set to one.
515output imu_logged_error_status_reg_eq_not_en_p_hw_read; // This signal provides
516 // the current value of
517 // imu_logged_error_status_reg_eq_not_en_p.
518input imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal
519 // for
520 // imu_logged_error_status_reg_msi_mal_err_p.
521 // When set
522 // imu_logged_error_status_reg
523 // will be set to one.
524output imu_logged_error_status_reg_msi_mal_err_p_hw_read; // This signal
525 // provides the
526 // current value of
527 // imu_logged_error_status_reg_msi_mal_err_p.
528input imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal
529 // for
530 // imu_logged_error_status_reg_msi_par_err_p.
531 // When set
532 // imu_logged_error_status_reg
533 // will be set to one.
534output imu_logged_error_status_reg_msi_par_err_p_hw_read; // This signal
535 // provides the
536 // current value of
537 // imu_logged_error_status_reg_msi_par_err_p.
538input imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set
539 // signal for
540 // imu_logged_error_status_reg_pmeack_mes_not_en_p.
541 // When set
542 // imu_logged_error_status_reg
543 // will be set
544 // to one.
545output imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read; // This signal
546 // provides the
547 // current
548 // value of
549 // imu_logged_error_status_reg_pmeack_mes_not_en_p.
550input imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set
551 // signal for
552 // imu_logged_error_status_reg_pmpme_mes_not_en_p.
553 // When set
554 // imu_logged_error_status_reg
555 // will be set to
556 // one.
557output imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read; // This signal
558 // provides the
559 // current value
560 // of
561 // imu_logged_error_status_reg_pmpme_mes_not_en_p.
562input imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set
563 // signal for
564 // imu_logged_error_status_reg_fatal_mes_not_en_p.
565 // When set
566 // imu_logged_error_status_reg
567 // will be set to
568 // one.
569output imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read; // This signal
570 // provides the
571 // current value
572 // of
573 // imu_logged_error_status_reg_fatal_mes_not_en_p.
574input imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware
575 // set signal
576 // for
577 // imu_logged_error_status_reg_nonfatal_mes_not_en_p.
578 // When set
579 // imu_logged_error_status_reg
580 // will be set
581 // to one.
582output imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read;
583 // This signal provides the current value of
584 // imu_logged_error_status_reg_nonfatal_mes_not_en_p.
585input imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set
586 // signal for
587 // imu_logged_error_status_reg_cor_mes_not_en_p.
588 // When set
589 // imu_logged_error_status_reg
590 // will be set to
591 // one.
592output imu_logged_error_status_reg_cor_mes_not_en_p_hw_read; // This signal
593 // provides the
594 // current value
595 // of
596 // imu_logged_error_status_reg_cor_mes_not_en_p.
597input imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal
598 // for
599 // imu_logged_error_status_reg_msi_not_en_p.
600 // When set
601 // imu_logged_error_status_reg
602 // will be set to one.
603output imu_logged_error_status_reg_msi_not_en_p_hw_read; // This signal
604 // provides the
605 // current value of
606 // imu_logged_error_status_reg_msi_not_en_p.
607input imu_rds_error_log_reg_hw_ld; // Hardware load enable for
608 // imu_rds_error_log_reg. When set, <hw
609 // write signal> will be loaded into
610 // imu_rds_error_log_reg.
611input [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_hw_write;
612 // data bus for hw loading of imu_rds_error_log_reg.
613input imu_scs_error_log_reg_hw_ld; // Hardware load enable for
614 // imu_scs_error_log_reg. When set, <hw
615 // write signal> will be loaded into
616 // imu_scs_error_log_reg.
617input [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_hw_write;
618 // data bus for hw loading of imu_scs_error_log_reg.
619input imu_eqs_error_log_reg_hw_ld; // Hardware load enable for
620 // imu_eqs_error_log_reg. When set, <hw
621 // write signal> will be loaded into
622 // imu_eqs_error_log_reg.
623input [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_hw_write;
624 // data bus for hw loading of imu_eqs_error_log_reg.
625output dmc_interrupt_mask_reg_dmc_hw_read; // This signal provides the current
626 // value of
627 // dmc_interrupt_mask_reg_dmc.
628output dmc_interrupt_mask_reg_debug_trig_en_hw_read; // This signal provides
629 // the current value of
630 // dmc_interrupt_mask_reg_debug_trig_en.
631output dmc_interrupt_mask_reg_mmu_hw_read; // This signal provides the current
632 // value of
633 // dmc_interrupt_mask_reg_mmu.
634output dmc_interrupt_mask_reg_imu_hw_read; // This signal provides the current
635 // value of
636 // dmc_interrupt_mask_reg_imu.
637input [0:0] dmc_interrupt_status_reg_mmu_ext_read_data; // Ext read data
638 // (decode)
639input [0:0] dmc_interrupt_status_reg_imu_ext_read_data; // Ext read data
640 // (decode)
641output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC] imu_perf_cntrl_sel1_hw_read;
642 // This signal provides the current value of imu_perf_cntrl_sel1.
643output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC] imu_perf_cntrl_sel0_hw_read;
644 // This signal provides the current value of imu_perf_cntrl_sel0.
645input [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_write;
646 // data bus for hw loading of imu_perf_cnt0_cnt.
647output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_read;
648 // This signal provides the current value of imu_perf_cnt0_cnt.
649input [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_write;
650 // data bus for hw loading of imu_perf_cnt1_cnt.
651output [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_read;
652 // This signal provides the current value of imu_perf_cnt1_cnt.
653output [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_INT_SLC] msi_32_addr_reg_addr_hw_read;
654 // This signal provides the current value of msi_32_addr_reg_addr.
655output [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_INT_SLC] msi_64_addr_reg_addr_hw_read;
656 // This signal provides the current value of msi_64_addr_reg_addr.
657output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC] mem_64_pcie_offset_reg_addr_hw_read;
658 // This signal provides the current value of mem_64_pcie_offset_reg_addr.
659input mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load
660 // enable for
661 // mem_64_pcie_offset_reg_spare_control_load_7.
662 // When set, <hw
663 // write signal>
664 // will be loaded
665 // into
666 // mem_64_pcie_offset_reg.
667input mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw
668 // loading of
669 // mem_64_pcie_offset_reg_spare_control_load_7.
670output mem_64_pcie_offset_reg_spare_control_load_7_hw_read; // This signal
671 // provides the
672 // current value of
673 // mem_64_pcie_offset_reg_spare_control_load_7.
674input mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load
675 // enable for
676 // mem_64_pcie_offset_reg_spare_control_load_6.
677 // When set, <hw
678 // write signal>
679 // will be loaded
680 // into
681 // mem_64_pcie_offset_reg.
682input mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw
683 // loading of
684 // mem_64_pcie_offset_reg_spare_control_load_6.
685output mem_64_pcie_offset_reg_spare_control_load_6_hw_read; // This signal
686 // provides the
687 // current value of
688 // mem_64_pcie_offset_reg_spare_control_load_6.
689input mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load
690 // enable for
691 // mem_64_pcie_offset_reg_spare_control_load_5.
692 // When set, <hw
693 // write signal>
694 // will be loaded
695 // into
696 // mem_64_pcie_offset_reg.
697input mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw
698 // loading of
699 // mem_64_pcie_offset_reg_spare_control_load_5.
700output mem_64_pcie_offset_reg_spare_control_load_5_hw_read; // This signal
701 // provides the
702 // current value of
703 // mem_64_pcie_offset_reg_spare_control_load_5.
704input mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load
705 // enable for
706 // mem_64_pcie_offset_reg_spare_control_load_4.
707 // When set, <hw
708 // write signal>
709 // will be loaded
710 // into
711 // mem_64_pcie_offset_reg.
712input mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw
713 // loading of
714 // mem_64_pcie_offset_reg_spare_control_load_4.
715output mem_64_pcie_offset_reg_spare_control_load_4_hw_read; // This signal
716 // provides the
717 // current value of
718 // mem_64_pcie_offset_reg_spare_control_load_4.
719input mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load
720 // enable for
721 // mem_64_pcie_offset_reg_spare_control_load_3.
722 // When set, <hw
723 // write signal>
724 // will be loaded
725 // into
726 // mem_64_pcie_offset_reg.
727input mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw
728 // loading of
729 // mem_64_pcie_offset_reg_spare_control_load_3.
730output mem_64_pcie_offset_reg_spare_control_load_3_hw_read; // This signal
731 // provides the
732 // current value of
733 // mem_64_pcie_offset_reg_spare_control_load_3.
734input mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load
735 // enable for
736 // mem_64_pcie_offset_reg_spare_control_load_2.
737 // When set, <hw
738 // write signal>
739 // will be loaded
740 // into
741 // mem_64_pcie_offset_reg.
742input mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw
743 // loading of
744 // mem_64_pcie_offset_reg_spare_control_load_2.
745output mem_64_pcie_offset_reg_spare_control_load_2_hw_read; // This signal
746 // provides the
747 // current value of
748 // mem_64_pcie_offset_reg_spare_control_load_2.
749input mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load
750 // enable for
751 // mem_64_pcie_offset_reg_spare_control_load_1.
752 // When set, <hw
753 // write signal>
754 // will be loaded
755 // into
756 // mem_64_pcie_offset_reg.
757input mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw
758 // loading of
759 // mem_64_pcie_offset_reg_spare_control_load_1.
760output mem_64_pcie_offset_reg_spare_control_load_1_hw_read; // This signal
761 // provides the
762 // current value of
763 // mem_64_pcie_offset_reg_spare_control_load_1.
764input mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load
765 // enable for
766 // mem_64_pcie_offset_reg_spare_control_load_0.
767 // When set, <hw
768 // write signal>
769 // will be loaded
770 // into
771 // mem_64_pcie_offset_reg.
772input mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw
773 // loading of
774 // mem_64_pcie_offset_reg_spare_control_load_0.
775output mem_64_pcie_offset_reg_spare_control_load_0_hw_read; // This signal
776 // provides the
777 // current value of
778 // mem_64_pcie_offset_reg_spare_control_load_0.
779input [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC]
780 mem_64_pcie_offset_reg_spare_control_hw_write; // data bus for hw loading of
781 // mem_64_pcie_offset_reg_spare_control.
782output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC]
783 mem_64_pcie_offset_reg_spare_control_hw_read; // This signal provides the
784 // current value of
785 // mem_64_pcie_offset_reg_spare_control.
786output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC] mem_64_pcie_offset_reg_spare_status_hw_read;
787 // This signal provides the current value of
788 // mem_64_pcie_offset_reg_spare_status.
789
790//====================================================
791// Type declarations
792//====================================================
793wire clk; // Clock signal
794wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
795wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
796wire csrbus_wr; // Read/Write signal
797wire csrbus_valid; // Valid address
798wire csrbus_mapped; // Address is mapped
799wire csrbus_done; // Operation is done
800wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
801wire por_l; // Reset signal
802wire rst_l; // Reset signal
803wire [1:0] csrbus_src_bus; // Source bus
804wire csrbus_acc_vio; // Violation signal
805wire instance_id; // Instance ID
806wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read;
807 // This signal provides the current value of
808 // imu_error_log_en_reg_spare_log_en.
809wire imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the
810 // current value of
811 // imu_error_log_en_reg_eq_over_log_en.
812wire imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides the
813 // current value of
814 // imu_error_log_en_reg_eq_not_en_log_en.
815wire imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides
816 // the current value of
817 // imu_error_log_en_reg_msi_mal_err_log_en.
818wire imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides
819 // the current value of
820 // imu_error_log_en_reg_msi_par_err_log_en.
821wire imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal
822 // provides the
823 // current value of
824 // imu_error_log_en_reg_pmeack_mes_not_en_log_en.
825wire imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal
826 // provides the
827 // current value of
828 // imu_error_log_en_reg_pmpme_mes_not_en_log_en.
829wire imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal
830 // provides the
831 // current value of
832 // imu_error_log_en_reg_fatal_mes_not_en_log_en.
833wire imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal
834 // provides the
835 // current value
836 // of
837 // imu_error_log_en_reg_nonfatal_mes_not_en_log_en.
838wire imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal
839 // provides the
840 // current value of
841 // imu_error_log_en_reg_cor_mes_not_en_log_en.
842wire imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides
843 // the current value of
844 // imu_error_log_en_reg_msi_not_en_log_en.
845wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC] imu_int_en_reg_spare_s_int_en_hw_read;
846 // This signal provides the current value of imu_int_en_reg_spare_s_int_en.
847wire imu_int_en_reg_eq_over_s_int_en_hw_read; // This signal provides the
848 // current value of
849 // imu_int_en_reg_eq_over_s_int_en.
850wire imu_int_en_reg_eq_not_en_s_int_en_hw_read; // This signal provides the
851 // current value of
852 // imu_int_en_reg_eq_not_en_s_int_en.
853wire imu_int_en_reg_msi_mal_err_s_int_en_hw_read; // This signal provides the
854 // current value of
855 // imu_int_en_reg_msi_mal_err_s_int_en.
856wire imu_int_en_reg_msi_par_err_s_int_en_hw_read; // This signal provides the
857 // current value of
858 // imu_int_en_reg_msi_par_err_s_int_en.
859wire imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read; // This signal provides
860 // the current value of
861 // imu_int_en_reg_pmeack_mes_not_en_s_int_en.
862wire imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read; // This signal provides
863 // the current value of
864 // imu_int_en_reg_pmpme_mes_not_en_s_int_en.
865wire imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read; // This signal provides
866 // the current value of
867 // imu_int_en_reg_fatal_mes_not_en_s_int_en.
868wire imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read; // This signal
869 // provides the
870 // current value of
871 // imu_int_en_reg_nonfatal_mes_not_en_s_int_en.
872wire imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read; // This signal provides
873 // the current value of
874 // imu_int_en_reg_cor_mes_not_en_s_int_en.
875wire imu_int_en_reg_msi_not_en_s_int_en_hw_read; // This signal provides the
876 // current value of
877 // imu_int_en_reg_msi_not_en_s_int_en.
878wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC] imu_int_en_reg_spare_p_int_en_hw_read;
879 // This signal provides the current value of imu_int_en_reg_spare_p_int_en.
880wire imu_int_en_reg_eq_over_p_int_en_hw_read; // This signal provides the
881 // current value of
882 // imu_int_en_reg_eq_over_p_int_en.
883wire imu_int_en_reg_eq_not_en_p_int_en_hw_read; // This signal provides the
884 // current value of
885 // imu_int_en_reg_eq_not_en_p_int_en.
886wire imu_int_en_reg_msi_mal_err_p_int_en_hw_read; // This signal provides the
887 // current value of
888 // imu_int_en_reg_msi_mal_err_p_int_en.
889wire imu_int_en_reg_msi_par_err_p_int_en_hw_read; // This signal provides the
890 // current value of
891 // imu_int_en_reg_msi_par_err_p_int_en.
892wire imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read; // This signal provides
893 // the current value of
894 // imu_int_en_reg_pmeack_mes_not_en_p_int_en.
895wire imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read; // This signal provides
896 // the current value of
897 // imu_int_en_reg_pmpme_mes_not_en_p_int_en.
898wire imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read; // This signal provides
899 // the current value of
900 // imu_int_en_reg_fatal_mes_not_en_p_int_en.
901wire imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read; // This signal
902 // provides the
903 // current value of
904 // imu_int_en_reg_nonfatal_mes_not_en_p_int_en.
905wire imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read; // This signal provides
906 // the current value of
907 // imu_int_en_reg_cor_mes_not_en_p_int_en.
908wire imu_int_en_reg_msi_not_en_p_int_en_hw_read; // This signal provides the
909 // current value of
910 // imu_int_en_reg_msi_not_en_p_int_en.
911wire [4:0] imu_enabled_error_status_reg_spare_s_ext_read_data; // Ext read data
912 // (decode)
913wire [0:0] imu_enabled_error_status_reg_eq_over_s_ext_read_data; // Ext read
914 // data
915 // (decode)
916wire [0:0] imu_enabled_error_status_reg_eq_not_en_s_ext_read_data;
917 // Ext read data (decode)
918wire [0:0] imu_enabled_error_status_reg_msi_mal_err_s_ext_read_data;
919 // Ext read data (decode)
920wire [0:0] imu_enabled_error_status_reg_msi_par_err_s_ext_read_data;
921 // Ext read data (decode)
922wire [0:0] imu_enabled_error_status_reg_pmeack_mes_not_en_s_ext_read_data;
923 // Ext read data (decode)
924wire [0:0] imu_enabled_error_status_reg_pmpme_mes_not_en_s_ext_read_data;
925 // Ext read data (decode)
926wire [0:0] imu_enabled_error_status_reg_fatal_mes_not_en_s_ext_read_data;
927 // Ext read data (decode)
928wire [0:0] imu_enabled_error_status_reg_nonfatal_mes_not_en_s_ext_read_data;
929 // Ext read data (decode)
930wire [0:0] imu_enabled_error_status_reg_cor_mes_not_en_s_ext_read_data;
931 // Ext read data (decode)
932wire [0:0] imu_enabled_error_status_reg_msi_not_en_s_ext_read_data;
933 // Ext read data (decode)
934wire [4:0] imu_enabled_error_status_reg_spare_p_ext_read_data; // Ext read data
935 // (decode)
936wire [0:0] imu_enabled_error_status_reg_eq_over_p_ext_read_data; // Ext read
937 // data
938 // (decode)
939wire [0:0] imu_enabled_error_status_reg_eq_not_en_p_ext_read_data;
940 // Ext read data (decode)
941wire [0:0] imu_enabled_error_status_reg_msi_mal_err_p_ext_read_data;
942 // Ext read data (decode)
943wire [0:0] imu_enabled_error_status_reg_msi_par_err_p_ext_read_data;
944 // Ext read data (decode)
945wire [0:0] imu_enabled_error_status_reg_pmeack_mes_not_en_p_ext_read_data;
946 // Ext read data (decode)
947wire [0:0] imu_enabled_error_status_reg_pmpme_mes_not_en_p_ext_read_data;
948 // Ext read data (decode)
949wire [0:0] imu_enabled_error_status_reg_fatal_mes_not_en_p_ext_read_data;
950 // Ext read data (decode)
951wire [0:0] imu_enabled_error_status_reg_nonfatal_mes_not_en_p_ext_read_data;
952 // Ext read data (decode)
953wire [0:0] imu_enabled_error_status_reg_cor_mes_not_en_p_ext_read_data;
954 // Ext read data (decode)
955wire [0:0] imu_enabled_error_status_reg_msi_not_en_p_ext_read_data;
956 // Ext read data (decode)
957wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC]
958 imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for
959 // imu_logged_error_status_reg_spare_s.
960 // When set
961 // imu_logged_error_status_reg
962 // will be set to one.
963wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC]
964 imu_logged_error_status_reg_spare_s_hw_read; // This signal provides the
965 // current value of
966 // imu_logged_error_status_reg_spare_s.
967wire imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for
968 // imu_logged_error_status_reg_eq_over_s.
969 // When set
970 // imu_logged_error_status_reg
971 // will be set to one.
972wire imu_logged_error_status_reg_eq_over_s_hw_read; // This signal provides the
973 // current value of
974 // imu_logged_error_status_reg_eq_over_s.
975wire imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal for
976 // imu_logged_error_status_reg_eq_not_en_s.
977 // When set
978 // imu_logged_error_status_reg
979 // will be set to one.
980wire imu_logged_error_status_reg_eq_not_en_s_hw_read; // This signal provides
981 // the current value of
982 // imu_logged_error_status_reg_eq_not_en_s.
983wire imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal
984 // for
985 // imu_logged_error_status_reg_msi_mal_err_s.
986 // When set
987 // imu_logged_error_status_reg
988 // will be set to one.
989wire imu_logged_error_status_reg_msi_mal_err_s_hw_read; // This signal provides
990 // the current value of
991 // imu_logged_error_status_reg_msi_mal_err_s.
992wire imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal
993 // for
994 // imu_logged_error_status_reg_msi_par_err_s.
995 // When set
996 // imu_logged_error_status_reg
997 // will be set to one.
998wire imu_logged_error_status_reg_msi_par_err_s_hw_read; // This signal provides
999 // the current value of
1000 // imu_logged_error_status_reg_msi_par_err_s.
1001wire imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set
1002 // signal for
1003 // imu_logged_error_status_reg_pmeack_mes_not_en_s.
1004 // When set
1005 // imu_logged_error_status_reg
1006 // will be set to
1007 // one.
1008wire imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read; // This signal
1009 // provides the
1010 // current value
1011 // of
1012 // imu_logged_error_status_reg_pmeack_mes_not_en_s.
1013wire imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set
1014 // signal for
1015 // imu_logged_error_status_reg_pmpme_mes_not_en_s.
1016 // When set
1017 // imu_logged_error_status_reg
1018 // will be set to
1019 // one.
1020wire imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read; // This signal
1021 // provides the
1022 // current value
1023 // of
1024 // imu_logged_error_status_reg_pmpme_mes_not_en_s.
1025wire imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set
1026 // signal for
1027 // imu_logged_error_status_reg_fatal_mes_not_en_s.
1028 // When set
1029 // imu_logged_error_status_reg
1030 // will be set to
1031 // one.
1032wire imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read; // This signal
1033 // provides the
1034 // current value
1035 // of
1036 // imu_logged_error_status_reg_fatal_mes_not_en_s.
1037wire imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware set
1038 // signal for
1039 // imu_logged_error_status_reg_nonfatal_mes_not_en_s.
1040 // When set
1041 // imu_logged_error_status_reg
1042 // will be set
1043 // to one.
1044wire imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read; // This signal
1045 // provides the
1046 // current
1047 // value of
1048 // imu_logged_error_status_reg_nonfatal_mes_not_en_s.
1049wire imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set
1050 // signal for
1051 // imu_logged_error_status_reg_cor_mes_not_en_s.
1052 // When set
1053 // imu_logged_error_status_reg
1054 // will be set to
1055 // one.
1056wire imu_logged_error_status_reg_cor_mes_not_en_s_hw_read; // This signal
1057 // provides the
1058 // current value of
1059 // imu_logged_error_status_reg_cor_mes_not_en_s.
1060wire imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal
1061 // for
1062 // imu_logged_error_status_reg_msi_not_en_s.
1063 // When set
1064 // imu_logged_error_status_reg
1065 // will be set to one.
1066wire imu_logged_error_status_reg_msi_not_en_s_hw_read; // This signal provides
1067 // the current value of
1068 // imu_logged_error_status_reg_msi_not_en_s.
1069wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC]
1070 imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for
1071 // imu_logged_error_status_reg_spare_p.
1072 // When set
1073 // imu_logged_error_status_reg
1074 // will be set to one.
1075wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC]
1076 imu_logged_error_status_reg_spare_p_hw_read; // This signal provides the
1077 // current value of
1078 // imu_logged_error_status_reg_spare_p.
1079wire imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for
1080 // imu_logged_error_status_reg_eq_over_p.
1081 // When set
1082 // imu_logged_error_status_reg
1083 // will be set to one.
1084wire imu_logged_error_status_reg_eq_over_p_hw_read; // This signal provides the
1085 // current value of
1086 // imu_logged_error_status_reg_eq_over_p.
1087wire imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal for
1088 // imu_logged_error_status_reg_eq_not_en_p.
1089 // When set
1090 // imu_logged_error_status_reg
1091 // will be set to one.
1092wire imu_logged_error_status_reg_eq_not_en_p_hw_read; // This signal provides
1093 // the current value of
1094 // imu_logged_error_status_reg_eq_not_en_p.
1095wire imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal
1096 // for
1097 // imu_logged_error_status_reg_msi_mal_err_p.
1098 // When set
1099 // imu_logged_error_status_reg
1100 // will be set to one.
1101wire imu_logged_error_status_reg_msi_mal_err_p_hw_read; // This signal provides
1102 // the current value of
1103 // imu_logged_error_status_reg_msi_mal_err_p.
1104wire imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal
1105 // for
1106 // imu_logged_error_status_reg_msi_par_err_p.
1107 // When set
1108 // imu_logged_error_status_reg
1109 // will be set to one.
1110wire imu_logged_error_status_reg_msi_par_err_p_hw_read; // This signal provides
1111 // the current value of
1112 // imu_logged_error_status_reg_msi_par_err_p.
1113wire imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set
1114 // signal for
1115 // imu_logged_error_status_reg_pmeack_mes_not_en_p.
1116 // When set
1117 // imu_logged_error_status_reg
1118 // will be set to
1119 // one.
1120wire imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read; // This signal
1121 // provides the
1122 // current value
1123 // of
1124 // imu_logged_error_status_reg_pmeack_mes_not_en_p.
1125wire imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set
1126 // signal for
1127 // imu_logged_error_status_reg_pmpme_mes_not_en_p.
1128 // When set
1129 // imu_logged_error_status_reg
1130 // will be set to
1131 // one.
1132wire imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read; // This signal
1133 // provides the
1134 // current value
1135 // of
1136 // imu_logged_error_status_reg_pmpme_mes_not_en_p.
1137wire imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set
1138 // signal for
1139 // imu_logged_error_status_reg_fatal_mes_not_en_p.
1140 // When set
1141 // imu_logged_error_status_reg
1142 // will be set to
1143 // one.
1144wire imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read; // This signal
1145 // provides the
1146 // current value
1147 // of
1148 // imu_logged_error_status_reg_fatal_mes_not_en_p.
1149wire imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware set
1150 // signal for
1151 // imu_logged_error_status_reg_nonfatal_mes_not_en_p.
1152 // When set
1153 // imu_logged_error_status_reg
1154 // will be set
1155 // to one.
1156wire imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read; // This signal
1157 // provides the
1158 // current
1159 // value of
1160 // imu_logged_error_status_reg_nonfatal_mes_not_en_p.
1161wire imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set
1162 // signal for
1163 // imu_logged_error_status_reg_cor_mes_not_en_p.
1164 // When set
1165 // imu_logged_error_status_reg
1166 // will be set to
1167 // one.
1168wire imu_logged_error_status_reg_cor_mes_not_en_p_hw_read; // This signal
1169 // provides the
1170 // current value of
1171 // imu_logged_error_status_reg_cor_mes_not_en_p.
1172wire imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal
1173 // for
1174 // imu_logged_error_status_reg_msi_not_en_p.
1175 // When set
1176 // imu_logged_error_status_reg
1177 // will be set to one.
1178wire imu_logged_error_status_reg_msi_not_en_p_hw_read; // This signal provides
1179 // the current value of
1180 // imu_logged_error_status_reg_msi_not_en_p.
1181wire imu_rds_error_log_reg_hw_ld; // Hardware load enable for
1182 // imu_rds_error_log_reg. When set, <hw write
1183 // signal> will be loaded into
1184 // imu_rds_error_log_reg.
1185wire [`FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH-1:0] imu_rds_error_log_reg_hw_write;
1186 // data bus for hw loading of imu_rds_error_log_reg.
1187wire imu_scs_error_log_reg_hw_ld; // Hardware load enable for
1188 // imu_scs_error_log_reg. When set, <hw write
1189 // signal> will be loaded into
1190 // imu_scs_error_log_reg.
1191wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_hw_write;
1192 // data bus for hw loading of imu_scs_error_log_reg.
1193wire imu_eqs_error_log_reg_hw_ld; // Hardware load enable for
1194 // imu_eqs_error_log_reg. When set, <hw write
1195 // signal> will be loaded into
1196 // imu_eqs_error_log_reg.
1197wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_hw_write;
1198 // data bus for hw loading of imu_eqs_error_log_reg.
1199wire dmc_interrupt_mask_reg_dmc_hw_read; // This signal provides the current
1200 // value of
1201 // dmc_interrupt_mask_reg_dmc.
1202wire dmc_interrupt_mask_reg_debug_trig_en_hw_read; // This signal provides the
1203 // current value of
1204 // dmc_interrupt_mask_reg_debug_trig_en.
1205wire dmc_interrupt_mask_reg_mmu_hw_read; // This signal provides the current
1206 // value of
1207 // dmc_interrupt_mask_reg_mmu.
1208wire dmc_interrupt_mask_reg_imu_hw_read; // This signal provides the current
1209 // value of
1210 // dmc_interrupt_mask_reg_imu.
1211wire [0:0] dmc_interrupt_status_reg_mmu_ext_read_data; // Ext read data
1212 // (decode)
1213wire [0:0] dmc_interrupt_status_reg_imu_ext_read_data; // Ext read data
1214 // (decode)
1215wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC] imu_perf_cntrl_sel1_hw_read;
1216 // This signal provides the current value of imu_perf_cntrl_sel1.
1217wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC] imu_perf_cntrl_sel0_hw_read;
1218 // This signal provides the current value of imu_perf_cntrl_sel0.
1219wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_write;
1220 // data bus for hw loading of imu_perf_cnt0_cnt.
1221wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC] imu_perf_cnt0_cnt_hw_read;
1222 // This signal provides the current value of imu_perf_cnt0_cnt.
1223wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_write;
1224 // data bus for hw loading of imu_perf_cnt1_cnt.
1225wire [`FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC] imu_perf_cnt1_cnt_hw_read;
1226 // This signal provides the current value of imu_perf_cnt1_cnt.
1227wire [`FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_INT_SLC] msi_32_addr_reg_addr_hw_read;
1228 // This signal provides the current value of msi_32_addr_reg_addr.
1229wire [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_INT_SLC] msi_64_addr_reg_addr_hw_read;
1230 // This signal provides the current value of msi_64_addr_reg_addr.
1231wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC] mem_64_pcie_offset_reg_addr_hw_read;
1232 // This signal provides the current value of mem_64_pcie_offset_reg_addr.
1233wire mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load enable
1234 // for
1235 // mem_64_pcie_offset_reg_spare_control_load_7.
1236 // When set, <hw write
1237 // signal> will be
1238 // loaded into
1239 // mem_64_pcie_offset_reg.
1240wire mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw
1241 // loading of
1242 // mem_64_pcie_offset_reg_spare_control_load_7.
1243wire mem_64_pcie_offset_reg_spare_control_load_7_hw_read; // This signal
1244 // provides the
1245 // current value of
1246 // mem_64_pcie_offset_reg_spare_control_load_7.
1247wire mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load enable
1248 // for
1249 // mem_64_pcie_offset_reg_spare_control_load_6.
1250 // When set, <hw write
1251 // signal> will be
1252 // loaded into
1253 // mem_64_pcie_offset_reg.
1254wire mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw
1255 // loading of
1256 // mem_64_pcie_offset_reg_spare_control_load_6.
1257wire mem_64_pcie_offset_reg_spare_control_load_6_hw_read; // This signal
1258 // provides the
1259 // current value of
1260 // mem_64_pcie_offset_reg_spare_control_load_6.
1261wire mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load enable
1262 // for
1263 // mem_64_pcie_offset_reg_spare_control_load_5.
1264 // When set, <hw write
1265 // signal> will be
1266 // loaded into
1267 // mem_64_pcie_offset_reg.
1268wire mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw
1269 // loading of
1270 // mem_64_pcie_offset_reg_spare_control_load_5.
1271wire mem_64_pcie_offset_reg_spare_control_load_5_hw_read; // This signal
1272 // provides the
1273 // current value of
1274 // mem_64_pcie_offset_reg_spare_control_load_5.
1275wire mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load enable
1276 // for
1277 // mem_64_pcie_offset_reg_spare_control_load_4.
1278 // When set, <hw write
1279 // signal> will be
1280 // loaded into
1281 // mem_64_pcie_offset_reg.
1282wire mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw
1283 // loading of
1284 // mem_64_pcie_offset_reg_spare_control_load_4.
1285wire mem_64_pcie_offset_reg_spare_control_load_4_hw_read; // This signal
1286 // provides the
1287 // current value of
1288 // mem_64_pcie_offset_reg_spare_control_load_4.
1289wire mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load enable
1290 // for
1291 // mem_64_pcie_offset_reg_spare_control_load_3.
1292 // When set, <hw write
1293 // signal> will be
1294 // loaded into
1295 // mem_64_pcie_offset_reg.
1296wire mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw
1297 // loading of
1298 // mem_64_pcie_offset_reg_spare_control_load_3.
1299wire mem_64_pcie_offset_reg_spare_control_load_3_hw_read; // This signal
1300 // provides the
1301 // current value of
1302 // mem_64_pcie_offset_reg_spare_control_load_3.
1303wire mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load enable
1304 // for
1305 // mem_64_pcie_offset_reg_spare_control_load_2.
1306 // When set, <hw write
1307 // signal> will be
1308 // loaded into
1309 // mem_64_pcie_offset_reg.
1310wire mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw
1311 // loading of
1312 // mem_64_pcie_offset_reg_spare_control_load_2.
1313wire mem_64_pcie_offset_reg_spare_control_load_2_hw_read; // This signal
1314 // provides the
1315 // current value of
1316 // mem_64_pcie_offset_reg_spare_control_load_2.
1317wire mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load enable
1318 // for
1319 // mem_64_pcie_offset_reg_spare_control_load_1.
1320 // When set, <hw write
1321 // signal> will be
1322 // loaded into
1323 // mem_64_pcie_offset_reg.
1324wire mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw
1325 // loading of
1326 // mem_64_pcie_offset_reg_spare_control_load_1.
1327wire mem_64_pcie_offset_reg_spare_control_load_1_hw_read; // This signal
1328 // provides the
1329 // current value of
1330 // mem_64_pcie_offset_reg_spare_control_load_1.
1331wire mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load enable
1332 // for
1333 // mem_64_pcie_offset_reg_spare_control_load_0.
1334 // When set, <hw write
1335 // signal> will be
1336 // loaded into
1337 // mem_64_pcie_offset_reg.
1338wire mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw
1339 // loading of
1340 // mem_64_pcie_offset_reg_spare_control_load_0.
1341wire mem_64_pcie_offset_reg_spare_control_load_0_hw_read; // This signal
1342 // provides the
1343 // current value of
1344 // mem_64_pcie_offset_reg_spare_control_load_0.
1345wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_write;
1346 // data bus for hw loading of mem_64_pcie_offset_reg_spare_control.
1347wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_read;
1348 // This signal provides the current value of
1349 // mem_64_pcie_offset_reg_spare_control.
1350wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC] mem_64_pcie_offset_reg_spare_status_hw_read;
1351 // This signal provides the current value of
1352 // mem_64_pcie_offset_reg_spare_status.
1353
1354//====================================================
1355// Logic
1356//====================================================
1357wire daemon_transaction_in_progress;
1358wire daemon_csrbus_mapped;
1359wire daemon_csrbus_valid;
1360// vlint flag_dangling_net_within_module off
1361// vlint flag_net_has_no_load off
1362wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp;
1363wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data;
1364// vlint flag_dangling_net_within_module on
1365// vlint flag_net_has_no_load on
1366wire daemon_csrbus_done;
1367wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr;
1368wire daemon_csrbus_wr_tmp;
1369wire daemon_csrbus_wr;
1370
1371//summit modcovoff -bepgnv
1372pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon (
1373 .daemon_csrbus_valid (daemon_csrbus_valid),
1374 .daemon_csrbus_mapped (daemon_csrbus_mapped),
1375 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
1376 .daemon_csrbus_done (daemon_csrbus_done),
1377 .daemon_csrbus_addr (daemon_csrbus_addr),
1378 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
1379 .daemon_transaction_in_progress (daemon_transaction_in_progress),
1380// synopsys translate_off
1381 .clk(clk),
1382 .csrbus_read_data (csrbus_read_data),
1383 .rst_l (rst_l),
1384// synopsys translate_on
1385 .csrbus_valid (csrbus_valid),
1386 .csrbus_mapped (csrbus_mapped),
1387 .csrbus_wr_data (csrbus_wr_data),
1388 .csrbus_done (csrbus_done),
1389 .csrbus_addr (csrbus_addr),
1390 .csrbus_wr (csrbus_wr)
1391 );
1392//summit modcovon -bepgnv
1393
1394//====================================================================
1395// Address decode
1396//====================================================================
1397wire imu_error_log_en_reg_select_pulse;
1398wire imu_int_en_reg_select_pulse;
1399wire imu_enabled_error_status_reg_select;
1400wire imu_logged_error_status_reg_select_pulse;
1401wire imu_rds_error_log_reg_select_pulse;
1402wire imu_scs_error_log_reg_select_pulse;
1403wire imu_eqs_error_log_reg_select_pulse;
1404wire dmc_interrupt_mask_reg_select_pulse;
1405wire dmc_interrupt_status_reg_select;
1406wire imu_perf_cntrl_select_pulse;
1407wire imu_perf_cnt0_select_pulse;
1408wire imu_perf_cnt1_select_pulse;
1409wire msi_32_addr_reg_select_pulse;
1410wire msi_64_addr_reg_select_pulse;
1411wire mem_64_pcie_offset_reg_select_pulse;
1412wire imu_logged_error_status_reg_rw1c_alias;
1413wire imu_logged_error_status_reg_rw1s_alias;
1414
1415dmu_imu_ics_addr_decode dmu_imu_ics_addr_decode
1416 (
1417 .clk (clk),
1418 .rst_l (rst_l),
1419 .daemon_csrbus_valid (daemon_csrbus_valid),
1420 .daemon_csrbus_addr (daemon_csrbus_addr),
1421 .csrbus_src_bus (csrbus_src_bus),
1422 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
1423 .daemon_csrbus_wr_out (daemon_csrbus_wr),
1424 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
1425 .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data),
1426 .daemon_csrbus_mapped (daemon_csrbus_mapped),
1427 .csrbus_acc_vio (csrbus_acc_vio),
1428 .daemon_transaction_in_progress (daemon_transaction_in_progress),
1429 .instance_id (instance_id),
1430 .daemon_csrbus_done (daemon_csrbus_done),
1431 .imu_error_log_en_reg_select_pulse (imu_error_log_en_reg_select_pulse),
1432 .imu_int_en_reg_select_pulse (imu_int_en_reg_select_pulse),
1433 .imu_enabled_error_status_reg_select (imu_enabled_error_status_reg_select),
1434 .imu_logged_error_status_reg_select_pulse (imu_logged_error_status_reg_select_pulse),
1435 .imu_logged_error_status_reg_rw1c_alias (imu_logged_error_status_reg_rw1c_alias),
1436 .imu_logged_error_status_reg_rw1s_alias (imu_logged_error_status_reg_rw1s_alias),
1437 .imu_rds_error_log_reg_select_pulse (imu_rds_error_log_reg_select_pulse),
1438 .imu_scs_error_log_reg_select_pulse (imu_scs_error_log_reg_select_pulse),
1439 .imu_eqs_error_log_reg_select_pulse (imu_eqs_error_log_reg_select_pulse),
1440 .dmc_interrupt_mask_reg_select_pulse (dmc_interrupt_mask_reg_select_pulse),
1441 .dmc_interrupt_status_reg_select (dmc_interrupt_status_reg_select),
1442 .imu_perf_cntrl_select_pulse (imu_perf_cntrl_select_pulse),
1443 .imu_perf_cnt0_select_pulse (imu_perf_cnt0_select_pulse),
1444 .imu_perf_cnt1_select_pulse (imu_perf_cnt1_select_pulse),
1445 .msi_32_addr_reg_select_pulse (msi_32_addr_reg_select_pulse),
1446 .msi_64_addr_reg_select_pulse (msi_64_addr_reg_select_pulse),
1447 .mem_64_pcie_offset_reg_select_pulse (mem_64_pcie_offset_reg_select_pulse)
1448 );
1449
1450//====================================================================
1451// OUTPUT: csrbus_read_data (pipelining)
1452//====================================================================
1453//----- connecting wires
1454wire stage_mux_only_rst_l;
1455wire stage_mux_only_por_l;
1456wire stage_mux_only_imu_logged_error_status_reg_rw1c_alias;
1457wire stage_mux_only_imu_logged_error_status_reg_rw1s_alias;
1458wire stage_mux_only_daemon_csrbus_wr;
1459wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data;
1460
1461//----- Stage: 1 / Grp: default_grp (15 inputs / 1 outputs)
1462wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out;
1463wire default_grp_imu_error_log_en_reg_select_pulse;
1464wire default_grp_imu_int_en_reg_select_pulse;
1465wire default_grp_imu_enabled_error_status_reg_select;
1466wire default_grp_imu_logged_error_status_reg_select_pulse;
1467wire default_grp_imu_rds_error_log_reg_select_pulse;
1468wire default_grp_imu_scs_error_log_reg_select_pulse;
1469wire default_grp_imu_eqs_error_log_reg_select_pulse;
1470wire default_grp_dmc_interrupt_mask_reg_select_pulse;
1471wire default_grp_dmc_interrupt_status_reg_select;
1472wire default_grp_imu_perf_cntrl_select_pulse;
1473wire default_grp_imu_perf_cnt0_select_pulse;
1474wire default_grp_imu_perf_cnt1_select_pulse;
1475wire default_grp_msi_32_addr_reg_select_pulse;
1476wire default_grp_msi_64_addr_reg_select_pulse;
1477wire default_grp_mem_64_pcie_offset_reg_select_pulse;
1478
1479dmu_imu_ics_default_grp dmu_imu_ics_default_grp
1480 (
1481 .clk (clk),
1482 .imu_error_log_en_reg_spare_log_en_hw_read (imu_error_log_en_reg_spare_log_en_hw_read),
1483 .imu_error_log_en_reg_eq_over_log_en_hw_read (imu_error_log_en_reg_eq_over_log_en_hw_read),
1484 .imu_error_log_en_reg_eq_not_en_log_en_hw_read (imu_error_log_en_reg_eq_not_en_log_en_hw_read),
1485 .imu_error_log_en_reg_msi_mal_err_log_en_hw_read (imu_error_log_en_reg_msi_mal_err_log_en_hw_read),
1486 .imu_error_log_en_reg_msi_par_err_log_en_hw_read (imu_error_log_en_reg_msi_par_err_log_en_hw_read),
1487 .imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read (imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read),
1488 .imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read (imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read),
1489 .imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read (imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read),
1490 .imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read (imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read),
1491 .imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read (imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read),
1492 .imu_error_log_en_reg_msi_not_en_log_en_hw_read (imu_error_log_en_reg_msi_not_en_log_en_hw_read),
1493 .imu_error_log_en_reg_select_pulse (default_grp_imu_error_log_en_reg_select_pulse),
1494 .imu_int_en_reg_spare_s_int_en_hw_read (imu_int_en_reg_spare_s_int_en_hw_read),
1495 .imu_int_en_reg_eq_over_s_int_en_hw_read (imu_int_en_reg_eq_over_s_int_en_hw_read),
1496 .imu_int_en_reg_eq_not_en_s_int_en_hw_read (imu_int_en_reg_eq_not_en_s_int_en_hw_read),
1497 .imu_int_en_reg_msi_mal_err_s_int_en_hw_read (imu_int_en_reg_msi_mal_err_s_int_en_hw_read),
1498 .imu_int_en_reg_msi_par_err_s_int_en_hw_read (imu_int_en_reg_msi_par_err_s_int_en_hw_read),
1499 .imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read (imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read),
1500 .imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read (imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read),
1501 .imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read (imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read),
1502 .imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read (imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read),
1503 .imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read (imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read),
1504 .imu_int_en_reg_msi_not_en_s_int_en_hw_read (imu_int_en_reg_msi_not_en_s_int_en_hw_read),
1505 .imu_int_en_reg_spare_p_int_en_hw_read (imu_int_en_reg_spare_p_int_en_hw_read),
1506 .imu_int_en_reg_eq_over_p_int_en_hw_read (imu_int_en_reg_eq_over_p_int_en_hw_read),
1507 .imu_int_en_reg_eq_not_en_p_int_en_hw_read (imu_int_en_reg_eq_not_en_p_int_en_hw_read),
1508 .imu_int_en_reg_msi_mal_err_p_int_en_hw_read (imu_int_en_reg_msi_mal_err_p_int_en_hw_read),
1509 .imu_int_en_reg_msi_par_err_p_int_en_hw_read (imu_int_en_reg_msi_par_err_p_int_en_hw_read),
1510 .imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read (imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read),
1511 .imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read (imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read),
1512 .imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read (imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read),
1513 .imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read (imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read),
1514 .imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read (imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read),
1515 .imu_int_en_reg_msi_not_en_p_int_en_hw_read (imu_int_en_reg_msi_not_en_p_int_en_hw_read),
1516 .imu_int_en_reg_select_pulse (default_grp_imu_int_en_reg_select_pulse),
1517 .imu_enabled_error_status_reg_select (default_grp_imu_enabled_error_status_reg_select),
1518 .imu_enabled_error_status_reg_ext_read_data
1519 (
1520 {
1521 17'b0,
1522 imu_enabled_error_status_reg_spare_s_ext_read_data,
1523 imu_enabled_error_status_reg_eq_over_s_ext_read_data,
1524 imu_enabled_error_status_reg_eq_not_en_s_ext_read_data,
1525 imu_enabled_error_status_reg_msi_mal_err_s_ext_read_data,
1526 imu_enabled_error_status_reg_msi_par_err_s_ext_read_data,
1527 imu_enabled_error_status_reg_pmeack_mes_not_en_s_ext_read_data,
1528 imu_enabled_error_status_reg_pmpme_mes_not_en_s_ext_read_data,
1529 imu_enabled_error_status_reg_fatal_mes_not_en_s_ext_read_data,
1530 imu_enabled_error_status_reg_nonfatal_mes_not_en_s_ext_read_data,
1531 imu_enabled_error_status_reg_cor_mes_not_en_s_ext_read_data,
1532 imu_enabled_error_status_reg_msi_not_en_s_ext_read_data,
1533 17'b0,
1534 imu_enabled_error_status_reg_spare_p_ext_read_data,
1535 imu_enabled_error_status_reg_eq_over_p_ext_read_data,
1536 imu_enabled_error_status_reg_eq_not_en_p_ext_read_data,
1537 imu_enabled_error_status_reg_msi_mal_err_p_ext_read_data,
1538 imu_enabled_error_status_reg_msi_par_err_p_ext_read_data,
1539 imu_enabled_error_status_reg_pmeack_mes_not_en_p_ext_read_data,
1540 imu_enabled_error_status_reg_pmpme_mes_not_en_p_ext_read_data,
1541 imu_enabled_error_status_reg_fatal_mes_not_en_p_ext_read_data,
1542 imu_enabled_error_status_reg_nonfatal_mes_not_en_p_ext_read_data,
1543 imu_enabled_error_status_reg_cor_mes_not_en_p_ext_read_data,
1544 imu_enabled_error_status_reg_msi_not_en_p_ext_read_data
1545 }),
1546 .imu_logged_error_status_reg_spare_s_hw_set (imu_logged_error_status_reg_spare_s_hw_set),
1547 .imu_logged_error_status_reg_spare_s_hw_read (imu_logged_error_status_reg_spare_s_hw_read),
1548 .imu_logged_error_status_reg_eq_over_s_hw_set (imu_logged_error_status_reg_eq_over_s_hw_set),
1549 .imu_logged_error_status_reg_eq_over_s_hw_read (imu_logged_error_status_reg_eq_over_s_hw_read),
1550 .imu_logged_error_status_reg_eq_not_en_s_hw_set (imu_logged_error_status_reg_eq_not_en_s_hw_set),
1551 .imu_logged_error_status_reg_eq_not_en_s_hw_read (imu_logged_error_status_reg_eq_not_en_s_hw_read),
1552 .imu_logged_error_status_reg_msi_mal_err_s_hw_set (imu_logged_error_status_reg_msi_mal_err_s_hw_set),
1553 .imu_logged_error_status_reg_msi_mal_err_s_hw_read (imu_logged_error_status_reg_msi_mal_err_s_hw_read),
1554 .imu_logged_error_status_reg_msi_par_err_s_hw_set (imu_logged_error_status_reg_msi_par_err_s_hw_set),
1555 .imu_logged_error_status_reg_msi_par_err_s_hw_read (imu_logged_error_status_reg_msi_par_err_s_hw_read),
1556 .imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set (imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set),
1557 .imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read (imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_read),
1558 .imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set (imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set),
1559 .imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read (imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_read),
1560 .imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set (imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set),
1561 .imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read (imu_logged_error_status_reg_fatal_mes_not_en_s_hw_read),
1562 .imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set (imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set),
1563 .imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read (imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_read),
1564 .imu_logged_error_status_reg_cor_mes_not_en_s_hw_set (imu_logged_error_status_reg_cor_mes_not_en_s_hw_set),
1565 .imu_logged_error_status_reg_cor_mes_not_en_s_hw_read (imu_logged_error_status_reg_cor_mes_not_en_s_hw_read),
1566 .imu_logged_error_status_reg_msi_not_en_s_hw_set (imu_logged_error_status_reg_msi_not_en_s_hw_set),
1567 .imu_logged_error_status_reg_msi_not_en_s_hw_read (imu_logged_error_status_reg_msi_not_en_s_hw_read),
1568 .imu_logged_error_status_reg_spare_p_hw_set (imu_logged_error_status_reg_spare_p_hw_set),
1569 .imu_logged_error_status_reg_spare_p_hw_read (imu_logged_error_status_reg_spare_p_hw_read),
1570 .imu_logged_error_status_reg_eq_over_p_hw_set (imu_logged_error_status_reg_eq_over_p_hw_set),
1571 .imu_logged_error_status_reg_eq_over_p_hw_read (imu_logged_error_status_reg_eq_over_p_hw_read),
1572 .imu_logged_error_status_reg_eq_not_en_p_hw_set (imu_logged_error_status_reg_eq_not_en_p_hw_set),
1573 .imu_logged_error_status_reg_eq_not_en_p_hw_read (imu_logged_error_status_reg_eq_not_en_p_hw_read),
1574 .imu_logged_error_status_reg_msi_mal_err_p_hw_set (imu_logged_error_status_reg_msi_mal_err_p_hw_set),
1575 .imu_logged_error_status_reg_msi_mal_err_p_hw_read (imu_logged_error_status_reg_msi_mal_err_p_hw_read),
1576 .imu_logged_error_status_reg_msi_par_err_p_hw_set (imu_logged_error_status_reg_msi_par_err_p_hw_set),
1577 .imu_logged_error_status_reg_msi_par_err_p_hw_read (imu_logged_error_status_reg_msi_par_err_p_hw_read),
1578 .imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set (imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set),
1579 .imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read (imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_read),
1580 .imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set (imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set),
1581 .imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read (imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_read),
1582 .imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set (imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set),
1583 .imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read (imu_logged_error_status_reg_fatal_mes_not_en_p_hw_read),
1584 .imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set (imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set),
1585 .imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read (imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_read),
1586 .imu_logged_error_status_reg_cor_mes_not_en_p_hw_set (imu_logged_error_status_reg_cor_mes_not_en_p_hw_set),
1587 .imu_logged_error_status_reg_cor_mes_not_en_p_hw_read (imu_logged_error_status_reg_cor_mes_not_en_p_hw_read),
1588 .imu_logged_error_status_reg_msi_not_en_p_hw_set (imu_logged_error_status_reg_msi_not_en_p_hw_set),
1589 .imu_logged_error_status_reg_msi_not_en_p_hw_read (imu_logged_error_status_reg_msi_not_en_p_hw_read),
1590 .imu_logged_error_status_reg_select_pulse (default_grp_imu_logged_error_status_reg_select_pulse),
1591 .imu_rds_error_log_reg_hw_ld (imu_rds_error_log_reg_hw_ld),
1592 .imu_rds_error_log_reg_hw_write (imu_rds_error_log_reg_hw_write),
1593 .imu_rds_error_log_reg_select_pulse (default_grp_imu_rds_error_log_reg_select_pulse),
1594 .imu_scs_error_log_reg_hw_ld (imu_scs_error_log_reg_hw_ld),
1595 .imu_scs_error_log_reg_hw_write (imu_scs_error_log_reg_hw_write),
1596 .imu_scs_error_log_reg_select_pulse (default_grp_imu_scs_error_log_reg_select_pulse),
1597 .imu_eqs_error_log_reg_hw_ld (imu_eqs_error_log_reg_hw_ld),
1598 .imu_eqs_error_log_reg_hw_write (imu_eqs_error_log_reg_hw_write),
1599 .imu_eqs_error_log_reg_select_pulse (default_grp_imu_eqs_error_log_reg_select_pulse),
1600 .dmc_interrupt_mask_reg_dmc_hw_read (dmc_interrupt_mask_reg_dmc_hw_read),
1601 .dmc_interrupt_mask_reg_debug_trig_en_hw_read (dmc_interrupt_mask_reg_debug_trig_en_hw_read),
1602 .dmc_interrupt_mask_reg_mmu_hw_read (dmc_interrupt_mask_reg_mmu_hw_read),
1603 .dmc_interrupt_mask_reg_imu_hw_read (dmc_interrupt_mask_reg_imu_hw_read),
1604 .dmc_interrupt_mask_reg_select_pulse (default_grp_dmc_interrupt_mask_reg_select_pulse),
1605 .dmc_interrupt_status_reg_select (default_grp_dmc_interrupt_status_reg_select),
1606 .dmc_interrupt_status_reg_ext_read_data
1607 (
1608 {
1609 62'b0,
1610 dmc_interrupt_status_reg_mmu_ext_read_data,
1611 dmc_interrupt_status_reg_imu_ext_read_data
1612 }),
1613 .imu_perf_cntrl_sel1_hw_read (imu_perf_cntrl_sel1_hw_read),
1614 .imu_perf_cntrl_sel0_hw_read (imu_perf_cntrl_sel0_hw_read),
1615 .imu_perf_cntrl_select_pulse (default_grp_imu_perf_cntrl_select_pulse),
1616 .imu_perf_cnt0_cnt_hw_write (imu_perf_cnt0_cnt_hw_write),
1617 .imu_perf_cnt0_cnt_hw_read (imu_perf_cnt0_cnt_hw_read),
1618 .imu_perf_cnt0_select_pulse (default_grp_imu_perf_cnt0_select_pulse),
1619 .imu_perf_cnt1_cnt_hw_write (imu_perf_cnt1_cnt_hw_write),
1620 .imu_perf_cnt1_cnt_hw_read (imu_perf_cnt1_cnt_hw_read),
1621 .imu_perf_cnt1_select_pulse (default_grp_imu_perf_cnt1_select_pulse),
1622 .msi_32_addr_reg_addr_hw_read (msi_32_addr_reg_addr_hw_read),
1623 .msi_32_addr_reg_select_pulse (default_grp_msi_32_addr_reg_select_pulse),
1624 .msi_64_addr_reg_addr_hw_read (msi_64_addr_reg_addr_hw_read),
1625 .msi_64_addr_reg_select_pulse (default_grp_msi_64_addr_reg_select_pulse),
1626 .mem_64_pcie_offset_reg_addr_hw_read (mem_64_pcie_offset_reg_addr_hw_read),
1627 .mem_64_pcie_offset_reg_spare_control_load_7_hw_ld (mem_64_pcie_offset_reg_spare_control_load_7_hw_ld),
1628 .mem_64_pcie_offset_reg_spare_control_load_7_hw_write (mem_64_pcie_offset_reg_spare_control_load_7_hw_write),
1629 .mem_64_pcie_offset_reg_spare_control_load_7_hw_read (mem_64_pcie_offset_reg_spare_control_load_7_hw_read),
1630 .mem_64_pcie_offset_reg_spare_control_load_6_hw_ld (mem_64_pcie_offset_reg_spare_control_load_6_hw_ld),
1631 .mem_64_pcie_offset_reg_spare_control_load_6_hw_write (mem_64_pcie_offset_reg_spare_control_load_6_hw_write),
1632 .mem_64_pcie_offset_reg_spare_control_load_6_hw_read (mem_64_pcie_offset_reg_spare_control_load_6_hw_read),
1633 .mem_64_pcie_offset_reg_spare_control_load_5_hw_ld (mem_64_pcie_offset_reg_spare_control_load_5_hw_ld),
1634 .mem_64_pcie_offset_reg_spare_control_load_5_hw_write (mem_64_pcie_offset_reg_spare_control_load_5_hw_write),
1635 .mem_64_pcie_offset_reg_spare_control_load_5_hw_read (mem_64_pcie_offset_reg_spare_control_load_5_hw_read),
1636 .mem_64_pcie_offset_reg_spare_control_load_4_hw_ld (mem_64_pcie_offset_reg_spare_control_load_4_hw_ld),
1637 .mem_64_pcie_offset_reg_spare_control_load_4_hw_write (mem_64_pcie_offset_reg_spare_control_load_4_hw_write),
1638 .mem_64_pcie_offset_reg_spare_control_load_4_hw_read (mem_64_pcie_offset_reg_spare_control_load_4_hw_read),
1639 .mem_64_pcie_offset_reg_spare_control_load_3_hw_ld (mem_64_pcie_offset_reg_spare_control_load_3_hw_ld),
1640 .mem_64_pcie_offset_reg_spare_control_load_3_hw_write (mem_64_pcie_offset_reg_spare_control_load_3_hw_write),
1641 .mem_64_pcie_offset_reg_spare_control_load_3_hw_read (mem_64_pcie_offset_reg_spare_control_load_3_hw_read),
1642 .mem_64_pcie_offset_reg_spare_control_load_2_hw_ld (mem_64_pcie_offset_reg_spare_control_load_2_hw_ld),
1643 .mem_64_pcie_offset_reg_spare_control_load_2_hw_write (mem_64_pcie_offset_reg_spare_control_load_2_hw_write),
1644 .mem_64_pcie_offset_reg_spare_control_load_2_hw_read (mem_64_pcie_offset_reg_spare_control_load_2_hw_read),
1645 .mem_64_pcie_offset_reg_spare_control_load_1_hw_ld (mem_64_pcie_offset_reg_spare_control_load_1_hw_ld),
1646 .mem_64_pcie_offset_reg_spare_control_load_1_hw_write (mem_64_pcie_offset_reg_spare_control_load_1_hw_write),
1647 .mem_64_pcie_offset_reg_spare_control_load_1_hw_read (mem_64_pcie_offset_reg_spare_control_load_1_hw_read),
1648 .mem_64_pcie_offset_reg_spare_control_load_0_hw_ld (mem_64_pcie_offset_reg_spare_control_load_0_hw_ld),
1649 .mem_64_pcie_offset_reg_spare_control_load_0_hw_write (mem_64_pcie_offset_reg_spare_control_load_0_hw_write),
1650 .mem_64_pcie_offset_reg_spare_control_load_0_hw_read (mem_64_pcie_offset_reg_spare_control_load_0_hw_read),
1651 .mem_64_pcie_offset_reg_spare_control_hw_write (mem_64_pcie_offset_reg_spare_control_hw_write),
1652 .mem_64_pcie_offset_reg_spare_control_hw_read (mem_64_pcie_offset_reg_spare_control_hw_read),
1653 .mem_64_pcie_offset_reg_spare_status_hw_read (mem_64_pcie_offset_reg_spare_status_hw_read),
1654 .mem_64_pcie_offset_reg_select_pulse (default_grp_mem_64_pcie_offset_reg_select_pulse),
1655 .imu_logged_error_status_reg_rw1c_alias (stage_mux_only_imu_logged_error_status_reg_rw1c_alias),
1656 .imu_logged_error_status_reg_rw1s_alias (stage_mux_only_imu_logged_error_status_reg_rw1s_alias),
1657 .rst_l (stage_mux_only_rst_l),
1658 .por_l (stage_mux_only_por_l),
1659 .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr),
1660 .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data),
1661 .read_data_0_out (default_grp_read_data_0_out)
1662 );
1663
1664//----- Stage: 2 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only)
1665wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out;
1666
1667dmu_imu_ics_stage_mux_only dmu_imu_ics_stage_mux_only
1668 (
1669 .clk (clk),
1670 .read_data_0 (default_grp_read_data_0_out),
1671 .imu_error_log_en_reg_select_pulse (imu_error_log_en_reg_select_pulse),
1672 .imu_error_log_en_reg_select_pulse_out (default_grp_imu_error_log_en_reg_select_pulse),
1673 .imu_int_en_reg_select_pulse (imu_int_en_reg_select_pulse),
1674 .imu_int_en_reg_select_pulse_out (default_grp_imu_int_en_reg_select_pulse),
1675 .imu_enabled_error_status_reg_select (imu_enabled_error_status_reg_select),
1676 .imu_enabled_error_status_reg_select_out (default_grp_imu_enabled_error_status_reg_select),
1677 .imu_logged_error_status_reg_select_pulse (imu_logged_error_status_reg_select_pulse),
1678 .imu_logged_error_status_reg_select_pulse_out (default_grp_imu_logged_error_status_reg_select_pulse),
1679 .imu_rds_error_log_reg_select_pulse (imu_rds_error_log_reg_select_pulse),
1680 .imu_rds_error_log_reg_select_pulse_out (default_grp_imu_rds_error_log_reg_select_pulse),
1681 .imu_scs_error_log_reg_select_pulse (imu_scs_error_log_reg_select_pulse),
1682 .imu_scs_error_log_reg_select_pulse_out (default_grp_imu_scs_error_log_reg_select_pulse),
1683 .imu_eqs_error_log_reg_select_pulse (imu_eqs_error_log_reg_select_pulse),
1684 .imu_eqs_error_log_reg_select_pulse_out (default_grp_imu_eqs_error_log_reg_select_pulse),
1685 .dmc_interrupt_mask_reg_select_pulse (dmc_interrupt_mask_reg_select_pulse),
1686 .dmc_interrupt_mask_reg_select_pulse_out (default_grp_dmc_interrupt_mask_reg_select_pulse),
1687 .dmc_interrupt_status_reg_select (dmc_interrupt_status_reg_select),
1688 .dmc_interrupt_status_reg_select_out (default_grp_dmc_interrupt_status_reg_select),
1689 .imu_perf_cntrl_select_pulse (imu_perf_cntrl_select_pulse),
1690 .imu_perf_cntrl_select_pulse_out (default_grp_imu_perf_cntrl_select_pulse),
1691 .imu_perf_cnt0_select_pulse (imu_perf_cnt0_select_pulse),
1692 .imu_perf_cnt0_select_pulse_out (default_grp_imu_perf_cnt0_select_pulse),
1693 .imu_perf_cnt1_select_pulse (imu_perf_cnt1_select_pulse),
1694 .imu_perf_cnt1_select_pulse_out (default_grp_imu_perf_cnt1_select_pulse),
1695 .msi_32_addr_reg_select_pulse (msi_32_addr_reg_select_pulse),
1696 .msi_32_addr_reg_select_pulse_out (default_grp_msi_32_addr_reg_select_pulse),
1697 .msi_64_addr_reg_select_pulse (msi_64_addr_reg_select_pulse),
1698 .msi_64_addr_reg_select_pulse_out (default_grp_msi_64_addr_reg_select_pulse),
1699 .mem_64_pcie_offset_reg_select_pulse (mem_64_pcie_offset_reg_select_pulse),
1700 .mem_64_pcie_offset_reg_select_pulse_out (default_grp_mem_64_pcie_offset_reg_select_pulse),
1701 .imu_logged_error_status_reg_rw1c_alias (imu_logged_error_status_reg_rw1c_alias),
1702 .imu_logged_error_status_reg_rw1c_alias_out (stage_mux_only_imu_logged_error_status_reg_rw1c_alias),
1703 .imu_logged_error_status_reg_rw1s_alias (imu_logged_error_status_reg_rw1s_alias),
1704 .imu_logged_error_status_reg_rw1s_alias_out (stage_mux_only_imu_logged_error_status_reg_rw1s_alias),
1705 .daemon_csrbus_wr_in (daemon_csrbus_wr),
1706 .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr),
1707 .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data),
1708 .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data),
1709 .read_data_0_out (stage_mux_only_read_data_0_out),
1710 .rst_l (rst_l),
1711 .rst_l_out (stage_mux_only_rst_l),
1712 .por_l (por_l),
1713 .por_l_out (stage_mux_only_por_l)
1714 );
1715
1716//----- OUTPUT: csrbus_read_data
1717assign csrbus_read_data = stage_mux_only_read_data_0_out;
1718
1719endmodule // dmu_imu_ics_csr
Full OpenSPARC design & verification tarball including full HDL.