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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_error_log_en_reg.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csr_imu_error_log_en_reg | |
36 | ( | |
37 | clk, | |
38 | por_l, | |
39 | imu_error_log_en_reg_w_ld, | |
40 | csrbus_wr_data, | |
41 | imu_error_log_en_reg_csrbus_read_data, | |
42 | imu_error_log_en_reg_spare_log_en_hw_read, | |
43 | imu_error_log_en_reg_eq_over_log_en_hw_read, | |
44 | imu_error_log_en_reg_eq_not_en_log_en_hw_read, | |
45 | imu_error_log_en_reg_msi_mal_err_log_en_hw_read, | |
46 | imu_error_log_en_reg_msi_par_err_log_en_hw_read, | |
47 | imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read, | |
48 | imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read, | |
49 | imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read, | |
50 | imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read, | |
51 | imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read, | |
52 | imu_error_log_en_reg_msi_not_en_log_en_hw_read | |
53 | ); | |
54 | ||
55 | //==================================================================== | |
56 | // Polarity declarations | |
57 | //==================================================================== | |
58 | input clk; // Clock | |
59 | input por_l; // Reset signal | |
60 | input imu_error_log_en_reg_w_ld; // SW load bus | |
61 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
62 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] imu_error_log_en_reg_csrbus_read_data; | |
63 | // SW read data | |
64 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read; | |
65 | // This signal provides the current value of | |
66 | // imu_error_log_en_reg_spare_log_en. | |
67 | output imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the | |
68 | // current value of | |
69 | // imu_error_log_en_reg_eq_over_log_en. | |
70 | output imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides | |
71 | // the current value of | |
72 | // imu_error_log_en_reg_eq_not_en_log_en. | |
73 | output imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides | |
74 | // the current value of | |
75 | // imu_error_log_en_reg_msi_mal_err_log_en. | |
76 | output imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides | |
77 | // the current value of | |
78 | // imu_error_log_en_reg_msi_par_err_log_en. | |
79 | output imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal | |
80 | // provides the | |
81 | // current value | |
82 | // of | |
83 | // imu_error_log_en_reg_pmeack_mes_not_en_log_en. | |
84 | output imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal | |
85 | // provides the | |
86 | // current value | |
87 | // of | |
88 | // imu_error_log_en_reg_pmpme_mes_not_en_log_en. | |
89 | output imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal | |
90 | // provides the | |
91 | // current value | |
92 | // of | |
93 | // imu_error_log_en_reg_fatal_mes_not_en_log_en. | |
94 | output imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal | |
95 | // provides the | |
96 | // current | |
97 | // value of | |
98 | // imu_error_log_en_reg_nonfatal_mes_not_en_log_en. | |
99 | output imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal | |
100 | // provides the | |
101 | // current value of | |
102 | // imu_error_log_en_reg_cor_mes_not_en_log_en. | |
103 | output imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides | |
104 | // the current value of | |
105 | // imu_error_log_en_reg_msi_not_en_log_en. | |
106 | ||
107 | //==================================================================== | |
108 | // Type declarations | |
109 | //==================================================================== | |
110 | wire clk; // Clock | |
111 | wire por_l; // Reset signal | |
112 | wire imu_error_log_en_reg_w_ld; // SW load bus | |
113 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
114 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] imu_error_log_en_reg_csrbus_read_data; | |
115 | // SW read data | |
116 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read; | |
117 | // This signal provides the current value of | |
118 | // imu_error_log_en_reg_spare_log_en. | |
119 | wire imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the | |
120 | // current value of | |
121 | // imu_error_log_en_reg_eq_over_log_en. | |
122 | wire imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides the | |
123 | // current value of | |
124 | // imu_error_log_en_reg_eq_not_en_log_en. | |
125 | wire imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides | |
126 | // the current value of | |
127 | // imu_error_log_en_reg_msi_mal_err_log_en. | |
128 | wire imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides | |
129 | // the current value of | |
130 | // imu_error_log_en_reg_msi_par_err_log_en. | |
131 | wire imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal | |
132 | // provides the | |
133 | // current value of | |
134 | // imu_error_log_en_reg_pmeack_mes_not_en_log_en. | |
135 | wire imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal | |
136 | // provides the | |
137 | // current value of | |
138 | // imu_error_log_en_reg_pmpme_mes_not_en_log_en. | |
139 | wire imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal | |
140 | // provides the | |
141 | // current value of | |
142 | // imu_error_log_en_reg_fatal_mes_not_en_log_en. | |
143 | wire imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal | |
144 | // provides the | |
145 | // current value | |
146 | // of | |
147 | // imu_error_log_en_reg_nonfatal_mes_not_en_log_en. | |
148 | wire imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal | |
149 | // provides the | |
150 | // current value of | |
151 | // imu_error_log_en_reg_cor_mes_not_en_log_en. | |
152 | wire imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides | |
153 | // the current value of | |
154 | // imu_error_log_en_reg_msi_not_en_log_en. | |
155 | ||
156 | //==================================================================== | |
157 | // Logic | |
158 | //==================================================================== | |
159 | ||
160 | // synopsys translate_off | |
161 | // verilint 123 off | |
162 | // verilint 498 off | |
163 | reg omni_ld; | |
164 | reg [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] omni_data; | |
165 | ||
166 | // vlint flag_unsynthesizable_initial off | |
167 | initial | |
168 | begin | |
169 | omni_ld = 1'b0; | |
170 | omni_data = `FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH'b0; | |
171 | end// vlint flag_unsynthesizable_initial on | |
172 | ||
173 | // verilint 123 on | |
174 | // verilint 498 on | |
175 | // synopsys translate_on | |
176 | ||
177 | //----- Hardware Data Out Mux Assignments | |
178 | assign imu_error_log_en_reg_spare_log_en_hw_read= | |
179 | imu_error_log_en_reg_csrbus_read_data | |
180 | [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_SLC]; | |
181 | assign imu_error_log_en_reg_eq_over_log_en_hw_read= | |
182 | imu_error_log_en_reg_csrbus_read_data [9]; | |
183 | assign imu_error_log_en_reg_eq_not_en_log_en_hw_read= | |
184 | imu_error_log_en_reg_csrbus_read_data [8]; | |
185 | assign imu_error_log_en_reg_msi_mal_err_log_en_hw_read= | |
186 | imu_error_log_en_reg_csrbus_read_data [7]; | |
187 | assign imu_error_log_en_reg_msi_par_err_log_en_hw_read= | |
188 | imu_error_log_en_reg_csrbus_read_data [6]; | |
189 | assign imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read= | |
190 | imu_error_log_en_reg_csrbus_read_data [5]; | |
191 | assign imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read= | |
192 | imu_error_log_en_reg_csrbus_read_data [4]; | |
193 | assign imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read= | |
194 | imu_error_log_en_reg_csrbus_read_data [3]; | |
195 | assign imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read= | |
196 | imu_error_log_en_reg_csrbus_read_data [2]; | |
197 | assign imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read= | |
198 | imu_error_log_en_reg_csrbus_read_data [1]; | |
199 | assign imu_error_log_en_reg_msi_not_en_log_en_hw_read= | |
200 | imu_error_log_en_reg_csrbus_read_data [0]; | |
201 | ||
202 | //==================================================================== | |
203 | // Instantiation of entries | |
204 | //==================================================================== | |
205 | ||
206 | //----- Entry 0 | |
207 | dmu_imu_ics_csr_imu_error_log_en_reg_entry imu_error_log_en_reg_0 | |
208 | ( | |
209 | // synopsys translate_off | |
210 | .omni_ld (omni_ld), | |
211 | .omni_data (omni_data), | |
212 | // synopsys translate_on | |
213 | .clk (clk), | |
214 | .por_l (por_l), | |
215 | .w_ld (imu_error_log_en_reg_w_ld), | |
216 | .csrbus_wr_data (csrbus_wr_data), | |
217 | .imu_error_log_en_reg_csrbus_read_data (imu_error_log_en_reg_csrbus_read_data) | |
218 | ); | |
219 | ||
220 | endmodule // dmu_imu_ics_csr_imu_error_log_en_reg |