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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_ics_csr_imu_int_en_reg.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_int_en_reg.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_ics_csr_imu_int_en_reg
36 (
37 clk,
38 rst_l,
39 imu_int_en_reg_w_ld,
40 csrbus_wr_data,
41 imu_int_en_reg_csrbus_read_data,
42 imu_int_en_reg_spare_s_int_en_hw_read,
43 imu_int_en_reg_eq_over_s_int_en_hw_read,
44 imu_int_en_reg_eq_not_en_s_int_en_hw_read,
45 imu_int_en_reg_msi_mal_err_s_int_en_hw_read,
46 imu_int_en_reg_msi_par_err_s_int_en_hw_read,
47 imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read,
48 imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read,
49 imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read,
50 imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read,
51 imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read,
52 imu_int_en_reg_msi_not_en_s_int_en_hw_read,
53 imu_int_en_reg_spare_p_int_en_hw_read,
54 imu_int_en_reg_eq_over_p_int_en_hw_read,
55 imu_int_en_reg_eq_not_en_p_int_en_hw_read,
56 imu_int_en_reg_msi_mal_err_p_int_en_hw_read,
57 imu_int_en_reg_msi_par_err_p_int_en_hw_read,
58 imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read,
59 imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read,
60 imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read,
61 imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read,
62 imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read,
63 imu_int_en_reg_msi_not_en_p_int_en_hw_read
64 );
65
66//====================================================================
67// Polarity declarations
68//====================================================================
69input clk; // Clock
70input rst_l; // Reset signal
71input imu_int_en_reg_w_ld; // SW load bus
72input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
73output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH-1:0] imu_int_en_reg_csrbus_read_data;
74 // SW read data
75output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC] imu_int_en_reg_spare_s_int_en_hw_read;
76 // This signal provides the current value of imu_int_en_reg_spare_s_int_en.
77output imu_int_en_reg_eq_over_s_int_en_hw_read; // This signal provides the
78 // current value of
79 // imu_int_en_reg_eq_over_s_int_en.
80output imu_int_en_reg_eq_not_en_s_int_en_hw_read; // This signal provides the
81 // current value of
82 // imu_int_en_reg_eq_not_en_s_int_en.
83output imu_int_en_reg_msi_mal_err_s_int_en_hw_read; // This signal provides the
84 // current value of
85 // imu_int_en_reg_msi_mal_err_s_int_en.
86output imu_int_en_reg_msi_par_err_s_int_en_hw_read; // This signal provides the
87 // current value of
88 // imu_int_en_reg_msi_par_err_s_int_en.
89output imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read; // This signal
90 // provides the
91 // current value of
92 // imu_int_en_reg_pmeack_mes_not_en_s_int_en.
93output imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read; // This signal
94 // provides the
95 // current value of
96 // imu_int_en_reg_pmpme_mes_not_en_s_int_en.
97output imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read; // This signal
98 // provides the
99 // current value of
100 // imu_int_en_reg_fatal_mes_not_en_s_int_en.
101output imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read; // This signal
102 // provides the
103 // current value of
104 // imu_int_en_reg_nonfatal_mes_not_en_s_int_en.
105output imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read; // This signal provides
106 // the current value of
107 // imu_int_en_reg_cor_mes_not_en_s_int_en.
108output imu_int_en_reg_msi_not_en_s_int_en_hw_read; // This signal provides the
109 // current value of
110 // imu_int_en_reg_msi_not_en_s_int_en.
111output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC] imu_int_en_reg_spare_p_int_en_hw_read;
112 // This signal provides the current value of imu_int_en_reg_spare_p_int_en.
113output imu_int_en_reg_eq_over_p_int_en_hw_read; // This signal provides the
114 // current value of
115 // imu_int_en_reg_eq_over_p_int_en.
116output imu_int_en_reg_eq_not_en_p_int_en_hw_read; // This signal provides the
117 // current value of
118 // imu_int_en_reg_eq_not_en_p_int_en.
119output imu_int_en_reg_msi_mal_err_p_int_en_hw_read; // This signal provides the
120 // current value of
121 // imu_int_en_reg_msi_mal_err_p_int_en.
122output imu_int_en_reg_msi_par_err_p_int_en_hw_read; // This signal provides the
123 // current value of
124 // imu_int_en_reg_msi_par_err_p_int_en.
125output imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read; // This signal
126 // provides the
127 // current value of
128 // imu_int_en_reg_pmeack_mes_not_en_p_int_en.
129output imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read; // This signal
130 // provides the
131 // current value of
132 // imu_int_en_reg_pmpme_mes_not_en_p_int_en.
133output imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read; // This signal
134 // provides the
135 // current value of
136 // imu_int_en_reg_fatal_mes_not_en_p_int_en.
137output imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read; // This signal
138 // provides the
139 // current value of
140 // imu_int_en_reg_nonfatal_mes_not_en_p_int_en.
141output imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read; // This signal provides
142 // the current value of
143 // imu_int_en_reg_cor_mes_not_en_p_int_en.
144output imu_int_en_reg_msi_not_en_p_int_en_hw_read; // This signal provides the
145 // current value of
146 // imu_int_en_reg_msi_not_en_p_int_en.
147
148//====================================================================
149// Type declarations
150//====================================================================
151wire clk; // Clock
152wire rst_l; // Reset signal
153wire imu_int_en_reg_w_ld; // SW load bus
154wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
155wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH-1:0] imu_int_en_reg_csrbus_read_data;
156 // SW read data
157wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC] imu_int_en_reg_spare_s_int_en_hw_read;
158 // This signal provides the current value of imu_int_en_reg_spare_s_int_en.
159wire imu_int_en_reg_eq_over_s_int_en_hw_read; // This signal provides the
160 // current value of
161 // imu_int_en_reg_eq_over_s_int_en.
162wire imu_int_en_reg_eq_not_en_s_int_en_hw_read; // This signal provides the
163 // current value of
164 // imu_int_en_reg_eq_not_en_s_int_en.
165wire imu_int_en_reg_msi_mal_err_s_int_en_hw_read; // This signal provides the
166 // current value of
167 // imu_int_en_reg_msi_mal_err_s_int_en.
168wire imu_int_en_reg_msi_par_err_s_int_en_hw_read; // This signal provides the
169 // current value of
170 // imu_int_en_reg_msi_par_err_s_int_en.
171wire imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read; // This signal provides
172 // the current value of
173 // imu_int_en_reg_pmeack_mes_not_en_s_int_en.
174wire imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read; // This signal provides
175 // the current value of
176 // imu_int_en_reg_pmpme_mes_not_en_s_int_en.
177wire imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read; // This signal provides
178 // the current value of
179 // imu_int_en_reg_fatal_mes_not_en_s_int_en.
180wire imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read; // This signal
181 // provides the
182 // current value of
183 // imu_int_en_reg_nonfatal_mes_not_en_s_int_en.
184wire imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read; // This signal provides
185 // the current value of
186 // imu_int_en_reg_cor_mes_not_en_s_int_en.
187wire imu_int_en_reg_msi_not_en_s_int_en_hw_read; // This signal provides the
188 // current value of
189 // imu_int_en_reg_msi_not_en_s_int_en.
190wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC] imu_int_en_reg_spare_p_int_en_hw_read;
191 // This signal provides the current value of imu_int_en_reg_spare_p_int_en.
192wire imu_int_en_reg_eq_over_p_int_en_hw_read; // This signal provides the
193 // current value of
194 // imu_int_en_reg_eq_over_p_int_en.
195wire imu_int_en_reg_eq_not_en_p_int_en_hw_read; // This signal provides the
196 // current value of
197 // imu_int_en_reg_eq_not_en_p_int_en.
198wire imu_int_en_reg_msi_mal_err_p_int_en_hw_read; // This signal provides the
199 // current value of
200 // imu_int_en_reg_msi_mal_err_p_int_en.
201wire imu_int_en_reg_msi_par_err_p_int_en_hw_read; // This signal provides the
202 // current value of
203 // imu_int_en_reg_msi_par_err_p_int_en.
204wire imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read; // This signal provides
205 // the current value of
206 // imu_int_en_reg_pmeack_mes_not_en_p_int_en.
207wire imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read; // This signal provides
208 // the current value of
209 // imu_int_en_reg_pmpme_mes_not_en_p_int_en.
210wire imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read; // This signal provides
211 // the current value of
212 // imu_int_en_reg_fatal_mes_not_en_p_int_en.
213wire imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read; // This signal
214 // provides the
215 // current value of
216 // imu_int_en_reg_nonfatal_mes_not_en_p_int_en.
217wire imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read; // This signal provides
218 // the current value of
219 // imu_int_en_reg_cor_mes_not_en_p_int_en.
220wire imu_int_en_reg_msi_not_en_p_int_en_hw_read; // This signal provides the
221 // current value of
222 // imu_int_en_reg_msi_not_en_p_int_en.
223
224//====================================================================
225// Logic
226//====================================================================
227
228// synopsys translate_off
229// verilint 123 off
230// verilint 498 off
231reg omni_ld;
232reg [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH-1:0] omni_data;
233
234// vlint flag_unsynthesizable_initial off
235initial
236 begin
237 omni_ld = 1'b0;
238 omni_data = `FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH'b0;
239 end// vlint flag_unsynthesizable_initial on
240
241// verilint 123 on
242// verilint 498 on
243// synopsys translate_on
244
245//----- Hardware Data Out Mux Assignments
246assign imu_int_en_reg_spare_s_int_en_hw_read=
247 imu_int_en_reg_csrbus_read_data
248 [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_SLC];
249assign imu_int_en_reg_eq_over_s_int_en_hw_read=
250 imu_int_en_reg_csrbus_read_data [41];
251assign imu_int_en_reg_eq_not_en_s_int_en_hw_read=
252 imu_int_en_reg_csrbus_read_data [40];
253assign imu_int_en_reg_msi_mal_err_s_int_en_hw_read=
254 imu_int_en_reg_csrbus_read_data [39];
255assign imu_int_en_reg_msi_par_err_s_int_en_hw_read=
256 imu_int_en_reg_csrbus_read_data [38];
257assign imu_int_en_reg_pmeack_mes_not_en_s_int_en_hw_read=
258 imu_int_en_reg_csrbus_read_data [37];
259assign imu_int_en_reg_pmpme_mes_not_en_s_int_en_hw_read=
260 imu_int_en_reg_csrbus_read_data [36];
261assign imu_int_en_reg_fatal_mes_not_en_s_int_en_hw_read=
262 imu_int_en_reg_csrbus_read_data [35];
263assign imu_int_en_reg_nonfatal_mes_not_en_s_int_en_hw_read=
264 imu_int_en_reg_csrbus_read_data [34];
265assign imu_int_en_reg_cor_mes_not_en_s_int_en_hw_read=
266 imu_int_en_reg_csrbus_read_data [33];
267assign imu_int_en_reg_msi_not_en_s_int_en_hw_read=
268 imu_int_en_reg_csrbus_read_data [32];
269assign imu_int_en_reg_spare_p_int_en_hw_read=
270 imu_int_en_reg_csrbus_read_data
271 [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_SLC];
272assign imu_int_en_reg_eq_over_p_int_en_hw_read=
273 imu_int_en_reg_csrbus_read_data [9];
274assign imu_int_en_reg_eq_not_en_p_int_en_hw_read=
275 imu_int_en_reg_csrbus_read_data [8];
276assign imu_int_en_reg_msi_mal_err_p_int_en_hw_read=
277 imu_int_en_reg_csrbus_read_data [7];
278assign imu_int_en_reg_msi_par_err_p_int_en_hw_read=
279 imu_int_en_reg_csrbus_read_data [6];
280assign imu_int_en_reg_pmeack_mes_not_en_p_int_en_hw_read=
281 imu_int_en_reg_csrbus_read_data [5];
282assign imu_int_en_reg_pmpme_mes_not_en_p_int_en_hw_read=
283 imu_int_en_reg_csrbus_read_data [4];
284assign imu_int_en_reg_fatal_mes_not_en_p_int_en_hw_read=
285 imu_int_en_reg_csrbus_read_data [3];
286assign imu_int_en_reg_nonfatal_mes_not_en_p_int_en_hw_read=
287 imu_int_en_reg_csrbus_read_data [2];
288assign imu_int_en_reg_cor_mes_not_en_p_int_en_hw_read=
289 imu_int_en_reg_csrbus_read_data [1];
290assign imu_int_en_reg_msi_not_en_p_int_en_hw_read=
291 imu_int_en_reg_csrbus_read_data [0];
292
293//====================================================================
294// Instantiation of entries
295//====================================================================
296
297//----- Entry 0
298dmu_imu_ics_csr_imu_int_en_reg_entry imu_int_en_reg_0
299 (
300 // synopsys translate_off
301 .omni_ld (omni_ld),
302 .omni_data (omni_data),
303 // synopsys translate_on
304 .clk (clk),
305 .rst_l (rst_l),
306 .w_ld (imu_int_en_reg_w_ld),
307 .csrbus_wr_data (csrbus_wr_data),
308 .imu_int_en_reg_csrbus_read_data (imu_int_en_reg_csrbus_read_data)
309 );
310
311endmodule // dmu_imu_ics_csr_imu_int_en_reg
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