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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_int_en_reg_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csr_imu_int_en_reg_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | imu_int_en_reg_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH - 1:0] omni_data; | |
55 | // Omni write data | |
56 | // synopsys translate_on | |
57 | // vlint flag_input_port_not_connected on | |
58 | input clk; // Clock signal | |
59 | input rst_l; // Reset signal | |
60 | input w_ld; // SW load | |
61 | // vlint flag_input_port_not_connected off | |
62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
63 | // vlint flag_input_port_not_connected on | |
64 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH-1:0] imu_int_en_reg_csrbus_read_data; | |
65 | // SW read data | |
66 | ||
67 | //==================================================================== | |
68 | // Type declarations | |
69 | //==================================================================== | |
70 | // synopsys translate_off | |
71 | wire omni_ld; // Omni load | |
72 | // vlint flag_dangling_net_within_module off | |
73 | // vlint flag_net_has_no_load off | |
74 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH - 1:0] omni_data; | |
75 | // Omni write data | |
76 | // synopsys translate_on | |
77 | // vlint flag_dangling_net_within_module on | |
78 | // vlint flag_net_has_no_load on | |
79 | wire clk; // Clock signal | |
80 | wire rst_l; // Reset signal | |
81 | wire w_ld; // SW load | |
82 | // vlint flag_dangling_net_within_module off | |
83 | // vlint flag_net_has_no_load off | |
84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
85 | // vlint flag_dangling_net_within_module on | |
86 | // vlint flag_net_has_no_load on | |
87 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH-1:0] imu_int_en_reg_csrbus_read_data; | |
88 | // SW read data | |
89 | ||
90 | //==================================================================== | |
91 | // Logic | |
92 | //==================================================================== | |
93 | ||
94 | //----- Reset values | |
95 | // verilint 531 off | |
96 | wire [4:0] reset_spare_s_int_en = 5'h0; | |
97 | wire [0:0] reset_eq_over_s_int_en = 1'h0; | |
98 | wire [0:0] reset_eq_not_en_s_int_en = 1'h0; | |
99 | wire [0:0] reset_msi_mal_err_s_int_en = 1'h0; | |
100 | wire [0:0] reset_msi_par_err_s_int_en = 1'h0; | |
101 | wire [0:0] reset_pmeack_mes_not_en_s_int_en = 1'h0; | |
102 | wire [0:0] reset_pmpme_mes_not_en_s_int_en = 1'h0; | |
103 | wire [0:0] reset_fatal_mes_not_en_s_int_en = 1'h0; | |
104 | wire [0:0] reset_nonfatal_mes_not_en_s_int_en = 1'h0; | |
105 | wire [0:0] reset_cor_mes_not_en_s_int_en = 1'h0; | |
106 | wire [0:0] reset_msi_not_en_s_int_en = 1'h0; | |
107 | wire [4:0] reset_spare_p_int_en = 5'h0; | |
108 | wire [0:0] reset_eq_over_p_int_en = 1'h0; | |
109 | wire [0:0] reset_eq_not_en_p_int_en = 1'h0; | |
110 | wire [0:0] reset_msi_mal_err_p_int_en = 1'h0; | |
111 | wire [0:0] reset_msi_par_err_p_int_en = 1'h0; | |
112 | wire [0:0] reset_pmeack_mes_not_en_p_int_en = 1'h0; | |
113 | wire [0:0] reset_pmpme_mes_not_en_p_int_en = 1'h0; | |
114 | wire [0:0] reset_fatal_mes_not_en_p_int_en = 1'h0; | |
115 | wire [0:0] reset_nonfatal_mes_not_en_p_int_en = 1'h0; | |
116 | wire [0:0] reset_cor_mes_not_en_p_int_en = 1'h0; | |
117 | wire [0:0] reset_msi_not_en_p_int_en = 1'h0; | |
118 | // verilint 531 on | |
119 | ||
120 | //----- Active high reset wires | |
121 | wire rst_l_active_high = ~rst_l; | |
122 | ||
123 | //==================================================== | |
124 | // Instantiation of flops | |
125 | //==================================================== | |
126 | ||
127 | // bit 0 | |
128 | csr_sw csr_sw_0 | |
129 | ( | |
130 | // synopsys translate_off | |
131 | .omni_ld (omni_ld), | |
132 | .omni_data (omni_data[0]), | |
133 | .omni_rw_alias (1'b1), | |
134 | .omni_rw1c_alias (1'b0), | |
135 | .omni_rw1s_alias (1'b0), | |
136 | // synopsys translate_on | |
137 | .rst (rst_l_active_high), | |
138 | .rst_val (reset_msi_not_en_p_int_en[0]), | |
139 | .csr_ld (w_ld), | |
140 | .csr_data (csrbus_wr_data[0]), | |
141 | .rw_alias (1'b1), | |
142 | .rw1c_alias (1'b0), | |
143 | .rw1s_alias (1'b0), | |
144 | .hw_ld (1'b0), | |
145 | .hw_data (1'b0), | |
146 | .cp (clk), | |
147 | .q (imu_int_en_reg_csrbus_read_data[0]) | |
148 | ); | |
149 | ||
150 | // bit 1 | |
151 | csr_sw csr_sw_1 | |
152 | ( | |
153 | // synopsys translate_off | |
154 | .omni_ld (omni_ld), | |
155 | .omni_data (omni_data[1]), | |
156 | .omni_rw_alias (1'b1), | |
157 | .omni_rw1c_alias (1'b0), | |
158 | .omni_rw1s_alias (1'b0), | |
159 | // synopsys translate_on | |
160 | .rst (rst_l_active_high), | |
161 | .rst_val (reset_cor_mes_not_en_p_int_en[0]), | |
162 | .csr_ld (w_ld), | |
163 | .csr_data (csrbus_wr_data[1]), | |
164 | .rw_alias (1'b1), | |
165 | .rw1c_alias (1'b0), | |
166 | .rw1s_alias (1'b0), | |
167 | .hw_ld (1'b0), | |
168 | .hw_data (1'b0), | |
169 | .cp (clk), | |
170 | .q (imu_int_en_reg_csrbus_read_data[1]) | |
171 | ); | |
172 | ||
173 | // bit 2 | |
174 | csr_sw csr_sw_2 | |
175 | ( | |
176 | // synopsys translate_off | |
177 | .omni_ld (omni_ld), | |
178 | .omni_data (omni_data[2]), | |
179 | .omni_rw_alias (1'b1), | |
180 | .omni_rw1c_alias (1'b0), | |
181 | .omni_rw1s_alias (1'b0), | |
182 | // synopsys translate_on | |
183 | .rst (rst_l_active_high), | |
184 | .rst_val (reset_nonfatal_mes_not_en_p_int_en[0]), | |
185 | .csr_ld (w_ld), | |
186 | .csr_data (csrbus_wr_data[2]), | |
187 | .rw_alias (1'b1), | |
188 | .rw1c_alias (1'b0), | |
189 | .rw1s_alias (1'b0), | |
190 | .hw_ld (1'b0), | |
191 | .hw_data (1'b0), | |
192 | .cp (clk), | |
193 | .q (imu_int_en_reg_csrbus_read_data[2]) | |
194 | ); | |
195 | ||
196 | // bit 3 | |
197 | csr_sw csr_sw_3 | |
198 | ( | |
199 | // synopsys translate_off | |
200 | .omni_ld (omni_ld), | |
201 | .omni_data (omni_data[3]), | |
202 | .omni_rw_alias (1'b1), | |
203 | .omni_rw1c_alias (1'b0), | |
204 | .omni_rw1s_alias (1'b0), | |
205 | // synopsys translate_on | |
206 | .rst (rst_l_active_high), | |
207 | .rst_val (reset_fatal_mes_not_en_p_int_en[0]), | |
208 | .csr_ld (w_ld), | |
209 | .csr_data (csrbus_wr_data[3]), | |
210 | .rw_alias (1'b1), | |
211 | .rw1c_alias (1'b0), | |
212 | .rw1s_alias (1'b0), | |
213 | .hw_ld (1'b0), | |
214 | .hw_data (1'b0), | |
215 | .cp (clk), | |
216 | .q (imu_int_en_reg_csrbus_read_data[3]) | |
217 | ); | |
218 | ||
219 | // bit 4 | |
220 | csr_sw csr_sw_4 | |
221 | ( | |
222 | // synopsys translate_off | |
223 | .omni_ld (omni_ld), | |
224 | .omni_data (omni_data[4]), | |
225 | .omni_rw_alias (1'b1), | |
226 | .omni_rw1c_alias (1'b0), | |
227 | .omni_rw1s_alias (1'b0), | |
228 | // synopsys translate_on | |
229 | .rst (rst_l_active_high), | |
230 | .rst_val (reset_pmpme_mes_not_en_p_int_en[0]), | |
231 | .csr_ld (w_ld), | |
232 | .csr_data (csrbus_wr_data[4]), | |
233 | .rw_alias (1'b1), | |
234 | .rw1c_alias (1'b0), | |
235 | .rw1s_alias (1'b0), | |
236 | .hw_ld (1'b0), | |
237 | .hw_data (1'b0), | |
238 | .cp (clk), | |
239 | .q (imu_int_en_reg_csrbus_read_data[4]) | |
240 | ); | |
241 | ||
242 | // bit 5 | |
243 | csr_sw csr_sw_5 | |
244 | ( | |
245 | // synopsys translate_off | |
246 | .omni_ld (omni_ld), | |
247 | .omni_data (omni_data[5]), | |
248 | .omni_rw_alias (1'b1), | |
249 | .omni_rw1c_alias (1'b0), | |
250 | .omni_rw1s_alias (1'b0), | |
251 | // synopsys translate_on | |
252 | .rst (rst_l_active_high), | |
253 | .rst_val (reset_pmeack_mes_not_en_p_int_en[0]), | |
254 | .csr_ld (w_ld), | |
255 | .csr_data (csrbus_wr_data[5]), | |
256 | .rw_alias (1'b1), | |
257 | .rw1c_alias (1'b0), | |
258 | .rw1s_alias (1'b0), | |
259 | .hw_ld (1'b0), | |
260 | .hw_data (1'b0), | |
261 | .cp (clk), | |
262 | .q (imu_int_en_reg_csrbus_read_data[5]) | |
263 | ); | |
264 | ||
265 | // bit 6 | |
266 | csr_sw csr_sw_6 | |
267 | ( | |
268 | // synopsys translate_off | |
269 | .omni_ld (omni_ld), | |
270 | .omni_data (omni_data[6]), | |
271 | .omni_rw_alias (1'b1), | |
272 | .omni_rw1c_alias (1'b0), | |
273 | .omni_rw1s_alias (1'b0), | |
274 | // synopsys translate_on | |
275 | .rst (rst_l_active_high), | |
276 | .rst_val (reset_msi_par_err_p_int_en[0]), | |
277 | .csr_ld (w_ld), | |
278 | .csr_data (csrbus_wr_data[6]), | |
279 | .rw_alias (1'b1), | |
280 | .rw1c_alias (1'b0), | |
281 | .rw1s_alias (1'b0), | |
282 | .hw_ld (1'b0), | |
283 | .hw_data (1'b0), | |
284 | .cp (clk), | |
285 | .q (imu_int_en_reg_csrbus_read_data[6]) | |
286 | ); | |
287 | ||
288 | // bit 7 | |
289 | csr_sw csr_sw_7 | |
290 | ( | |
291 | // synopsys translate_off | |
292 | .omni_ld (omni_ld), | |
293 | .omni_data (omni_data[7]), | |
294 | .omni_rw_alias (1'b1), | |
295 | .omni_rw1c_alias (1'b0), | |
296 | .omni_rw1s_alias (1'b0), | |
297 | // synopsys translate_on | |
298 | .rst (rst_l_active_high), | |
299 | .rst_val (reset_msi_mal_err_p_int_en[0]), | |
300 | .csr_ld (w_ld), | |
301 | .csr_data (csrbus_wr_data[7]), | |
302 | .rw_alias (1'b1), | |
303 | .rw1c_alias (1'b0), | |
304 | .rw1s_alias (1'b0), | |
305 | .hw_ld (1'b0), | |
306 | .hw_data (1'b0), | |
307 | .cp (clk), | |
308 | .q (imu_int_en_reg_csrbus_read_data[7]) | |
309 | ); | |
310 | ||
311 | // bit 8 | |
312 | csr_sw csr_sw_8 | |
313 | ( | |
314 | // synopsys translate_off | |
315 | .omni_ld (omni_ld), | |
316 | .omni_data (omni_data[8]), | |
317 | .omni_rw_alias (1'b1), | |
318 | .omni_rw1c_alias (1'b0), | |
319 | .omni_rw1s_alias (1'b0), | |
320 | // synopsys translate_on | |
321 | .rst (rst_l_active_high), | |
322 | .rst_val (reset_eq_not_en_p_int_en[0]), | |
323 | .csr_ld (w_ld), | |
324 | .csr_data (csrbus_wr_data[8]), | |
325 | .rw_alias (1'b1), | |
326 | .rw1c_alias (1'b0), | |
327 | .rw1s_alias (1'b0), | |
328 | .hw_ld (1'b0), | |
329 | .hw_data (1'b0), | |
330 | .cp (clk), | |
331 | .q (imu_int_en_reg_csrbus_read_data[8]) | |
332 | ); | |
333 | ||
334 | // bit 9 | |
335 | csr_sw csr_sw_9 | |
336 | ( | |
337 | // synopsys translate_off | |
338 | .omni_ld (omni_ld), | |
339 | .omni_data (omni_data[9]), | |
340 | .omni_rw_alias (1'b1), | |
341 | .omni_rw1c_alias (1'b0), | |
342 | .omni_rw1s_alias (1'b0), | |
343 | // synopsys translate_on | |
344 | .rst (rst_l_active_high), | |
345 | .rst_val (reset_eq_over_p_int_en[0]), | |
346 | .csr_ld (w_ld), | |
347 | .csr_data (csrbus_wr_data[9]), | |
348 | .rw_alias (1'b1), | |
349 | .rw1c_alias (1'b0), | |
350 | .rw1s_alias (1'b0), | |
351 | .hw_ld (1'b0), | |
352 | .hw_data (1'b0), | |
353 | .cp (clk), | |
354 | .q (imu_int_en_reg_csrbus_read_data[9]) | |
355 | ); | |
356 | ||
357 | // bit 10 | |
358 | csr_sw csr_sw_10 | |
359 | ( | |
360 | // synopsys translate_off | |
361 | .omni_ld (omni_ld), | |
362 | .omni_data (omni_data[10]), | |
363 | .omni_rw_alias (1'b1), | |
364 | .omni_rw1c_alias (1'b0), | |
365 | .omni_rw1s_alias (1'b0), | |
366 | // synopsys translate_on | |
367 | .rst (rst_l_active_high), | |
368 | .rst_val (reset_spare_p_int_en[0]), | |
369 | .csr_ld (w_ld), | |
370 | .csr_data (csrbus_wr_data[10]), | |
371 | .rw_alias (1'b1), | |
372 | .rw1c_alias (1'b0), | |
373 | .rw1s_alias (1'b0), | |
374 | .hw_ld (1'b0), | |
375 | .hw_data (1'b0), | |
376 | .cp (clk), | |
377 | .q (imu_int_en_reg_csrbus_read_data[10]) | |
378 | ); | |
379 | ||
380 | // bit 11 | |
381 | csr_sw csr_sw_11 | |
382 | ( | |
383 | // synopsys translate_off | |
384 | .omni_ld (omni_ld), | |
385 | .omni_data (omni_data[11]), | |
386 | .omni_rw_alias (1'b1), | |
387 | .omni_rw1c_alias (1'b0), | |
388 | .omni_rw1s_alias (1'b0), | |
389 | // synopsys translate_on | |
390 | .rst (rst_l_active_high), | |
391 | .rst_val (reset_spare_p_int_en[1]), | |
392 | .csr_ld (w_ld), | |
393 | .csr_data (csrbus_wr_data[11]), | |
394 | .rw_alias (1'b1), | |
395 | .rw1c_alias (1'b0), | |
396 | .rw1s_alias (1'b0), | |
397 | .hw_ld (1'b0), | |
398 | .hw_data (1'b0), | |
399 | .cp (clk), | |
400 | .q (imu_int_en_reg_csrbus_read_data[11]) | |
401 | ); | |
402 | ||
403 | // bit 12 | |
404 | csr_sw csr_sw_12 | |
405 | ( | |
406 | // synopsys translate_off | |
407 | .omni_ld (omni_ld), | |
408 | .omni_data (omni_data[12]), | |
409 | .omni_rw_alias (1'b1), | |
410 | .omni_rw1c_alias (1'b0), | |
411 | .omni_rw1s_alias (1'b0), | |
412 | // synopsys translate_on | |
413 | .rst (rst_l_active_high), | |
414 | .rst_val (reset_spare_p_int_en[2]), | |
415 | .csr_ld (w_ld), | |
416 | .csr_data (csrbus_wr_data[12]), | |
417 | .rw_alias (1'b1), | |
418 | .rw1c_alias (1'b0), | |
419 | .rw1s_alias (1'b0), | |
420 | .hw_ld (1'b0), | |
421 | .hw_data (1'b0), | |
422 | .cp (clk), | |
423 | .q (imu_int_en_reg_csrbus_read_data[12]) | |
424 | ); | |
425 | ||
426 | // bit 13 | |
427 | csr_sw csr_sw_13 | |
428 | ( | |
429 | // synopsys translate_off | |
430 | .omni_ld (omni_ld), | |
431 | .omni_data (omni_data[13]), | |
432 | .omni_rw_alias (1'b1), | |
433 | .omni_rw1c_alias (1'b0), | |
434 | .omni_rw1s_alias (1'b0), | |
435 | // synopsys translate_on | |
436 | .rst (rst_l_active_high), | |
437 | .rst_val (reset_spare_p_int_en[3]), | |
438 | .csr_ld (w_ld), | |
439 | .csr_data (csrbus_wr_data[13]), | |
440 | .rw_alias (1'b1), | |
441 | .rw1c_alias (1'b0), | |
442 | .rw1s_alias (1'b0), | |
443 | .hw_ld (1'b0), | |
444 | .hw_data (1'b0), | |
445 | .cp (clk), | |
446 | .q (imu_int_en_reg_csrbus_read_data[13]) | |
447 | ); | |
448 | ||
449 | // bit 14 | |
450 | csr_sw csr_sw_14 | |
451 | ( | |
452 | // synopsys translate_off | |
453 | .omni_ld (omni_ld), | |
454 | .omni_data (omni_data[14]), | |
455 | .omni_rw_alias (1'b1), | |
456 | .omni_rw1c_alias (1'b0), | |
457 | .omni_rw1s_alias (1'b0), | |
458 | // synopsys translate_on | |
459 | .rst (rst_l_active_high), | |
460 | .rst_val (reset_spare_p_int_en[4]), | |
461 | .csr_ld (w_ld), | |
462 | .csr_data (csrbus_wr_data[14]), | |
463 | .rw_alias (1'b1), | |
464 | .rw1c_alias (1'b0), | |
465 | .rw1s_alias (1'b0), | |
466 | .hw_ld (1'b0), | |
467 | .hw_data (1'b0), | |
468 | .cp (clk), | |
469 | .q (imu_int_en_reg_csrbus_read_data[14]) | |
470 | ); | |
471 | ||
472 | assign imu_int_en_reg_csrbus_read_data[15] = 1'b0; // bit 15 | |
473 | assign imu_int_en_reg_csrbus_read_data[16] = 1'b0; // bit 16 | |
474 | assign imu_int_en_reg_csrbus_read_data[17] = 1'b0; // bit 17 | |
475 | assign imu_int_en_reg_csrbus_read_data[18] = 1'b0; // bit 18 | |
476 | assign imu_int_en_reg_csrbus_read_data[19] = 1'b0; // bit 19 | |
477 | assign imu_int_en_reg_csrbus_read_data[20] = 1'b0; // bit 20 | |
478 | assign imu_int_en_reg_csrbus_read_data[21] = 1'b0; // bit 21 | |
479 | assign imu_int_en_reg_csrbus_read_data[22] = 1'b0; // bit 22 | |
480 | assign imu_int_en_reg_csrbus_read_data[23] = 1'b0; // bit 23 | |
481 | assign imu_int_en_reg_csrbus_read_data[24] = 1'b0; // bit 24 | |
482 | assign imu_int_en_reg_csrbus_read_data[25] = 1'b0; // bit 25 | |
483 | assign imu_int_en_reg_csrbus_read_data[26] = 1'b0; // bit 26 | |
484 | assign imu_int_en_reg_csrbus_read_data[27] = 1'b0; // bit 27 | |
485 | assign imu_int_en_reg_csrbus_read_data[28] = 1'b0; // bit 28 | |
486 | assign imu_int_en_reg_csrbus_read_data[29] = 1'b0; // bit 29 | |
487 | assign imu_int_en_reg_csrbus_read_data[30] = 1'b0; // bit 30 | |
488 | assign imu_int_en_reg_csrbus_read_data[31] = 1'b0; // bit 31 | |
489 | // bit 32 | |
490 | csr_sw csr_sw_32 | |
491 | ( | |
492 | // synopsys translate_off | |
493 | .omni_ld (omni_ld), | |
494 | .omni_data (omni_data[32]), | |
495 | .omni_rw_alias (1'b1), | |
496 | .omni_rw1c_alias (1'b0), | |
497 | .omni_rw1s_alias (1'b0), | |
498 | // synopsys translate_on | |
499 | .rst (rst_l_active_high), | |
500 | .rst_val (reset_msi_not_en_s_int_en[0]), | |
501 | .csr_ld (w_ld), | |
502 | .csr_data (csrbus_wr_data[32]), | |
503 | .rw_alias (1'b1), | |
504 | .rw1c_alias (1'b0), | |
505 | .rw1s_alias (1'b0), | |
506 | .hw_ld (1'b0), | |
507 | .hw_data (1'b0), | |
508 | .cp (clk), | |
509 | .q (imu_int_en_reg_csrbus_read_data[32]) | |
510 | ); | |
511 | ||
512 | // bit 33 | |
513 | csr_sw csr_sw_33 | |
514 | ( | |
515 | // synopsys translate_off | |
516 | .omni_ld (omni_ld), | |
517 | .omni_data (omni_data[33]), | |
518 | .omni_rw_alias (1'b1), | |
519 | .omni_rw1c_alias (1'b0), | |
520 | .omni_rw1s_alias (1'b0), | |
521 | // synopsys translate_on | |
522 | .rst (rst_l_active_high), | |
523 | .rst_val (reset_cor_mes_not_en_s_int_en[0]), | |
524 | .csr_ld (w_ld), | |
525 | .csr_data (csrbus_wr_data[33]), | |
526 | .rw_alias (1'b1), | |
527 | .rw1c_alias (1'b0), | |
528 | .rw1s_alias (1'b0), | |
529 | .hw_ld (1'b0), | |
530 | .hw_data (1'b0), | |
531 | .cp (clk), | |
532 | .q (imu_int_en_reg_csrbus_read_data[33]) | |
533 | ); | |
534 | ||
535 | // bit 34 | |
536 | csr_sw csr_sw_34 | |
537 | ( | |
538 | // synopsys translate_off | |
539 | .omni_ld (omni_ld), | |
540 | .omni_data (omni_data[34]), | |
541 | .omni_rw_alias (1'b1), | |
542 | .omni_rw1c_alias (1'b0), | |
543 | .omni_rw1s_alias (1'b0), | |
544 | // synopsys translate_on | |
545 | .rst (rst_l_active_high), | |
546 | .rst_val (reset_nonfatal_mes_not_en_s_int_en[0]), | |
547 | .csr_ld (w_ld), | |
548 | .csr_data (csrbus_wr_data[34]), | |
549 | .rw_alias (1'b1), | |
550 | .rw1c_alias (1'b0), | |
551 | .rw1s_alias (1'b0), | |
552 | .hw_ld (1'b0), | |
553 | .hw_data (1'b0), | |
554 | .cp (clk), | |
555 | .q (imu_int_en_reg_csrbus_read_data[34]) | |
556 | ); | |
557 | ||
558 | // bit 35 | |
559 | csr_sw csr_sw_35 | |
560 | ( | |
561 | // synopsys translate_off | |
562 | .omni_ld (omni_ld), | |
563 | .omni_data (omni_data[35]), | |
564 | .omni_rw_alias (1'b1), | |
565 | .omni_rw1c_alias (1'b0), | |
566 | .omni_rw1s_alias (1'b0), | |
567 | // synopsys translate_on | |
568 | .rst (rst_l_active_high), | |
569 | .rst_val (reset_fatal_mes_not_en_s_int_en[0]), | |
570 | .csr_ld (w_ld), | |
571 | .csr_data (csrbus_wr_data[35]), | |
572 | .rw_alias (1'b1), | |
573 | .rw1c_alias (1'b0), | |
574 | .rw1s_alias (1'b0), | |
575 | .hw_ld (1'b0), | |
576 | .hw_data (1'b0), | |
577 | .cp (clk), | |
578 | .q (imu_int_en_reg_csrbus_read_data[35]) | |
579 | ); | |
580 | ||
581 | // bit 36 | |
582 | csr_sw csr_sw_36 | |
583 | ( | |
584 | // synopsys translate_off | |
585 | .omni_ld (omni_ld), | |
586 | .omni_data (omni_data[36]), | |
587 | .omni_rw_alias (1'b1), | |
588 | .omni_rw1c_alias (1'b0), | |
589 | .omni_rw1s_alias (1'b0), | |
590 | // synopsys translate_on | |
591 | .rst (rst_l_active_high), | |
592 | .rst_val (reset_pmpme_mes_not_en_s_int_en[0]), | |
593 | .csr_ld (w_ld), | |
594 | .csr_data (csrbus_wr_data[36]), | |
595 | .rw_alias (1'b1), | |
596 | .rw1c_alias (1'b0), | |
597 | .rw1s_alias (1'b0), | |
598 | .hw_ld (1'b0), | |
599 | .hw_data (1'b0), | |
600 | .cp (clk), | |
601 | .q (imu_int_en_reg_csrbus_read_data[36]) | |
602 | ); | |
603 | ||
604 | // bit 37 | |
605 | csr_sw csr_sw_37 | |
606 | ( | |
607 | // synopsys translate_off | |
608 | .omni_ld (omni_ld), | |
609 | .omni_data (omni_data[37]), | |
610 | .omni_rw_alias (1'b1), | |
611 | .omni_rw1c_alias (1'b0), | |
612 | .omni_rw1s_alias (1'b0), | |
613 | // synopsys translate_on | |
614 | .rst (rst_l_active_high), | |
615 | .rst_val (reset_pmeack_mes_not_en_s_int_en[0]), | |
616 | .csr_ld (w_ld), | |
617 | .csr_data (csrbus_wr_data[37]), | |
618 | .rw_alias (1'b1), | |
619 | .rw1c_alias (1'b0), | |
620 | .rw1s_alias (1'b0), | |
621 | .hw_ld (1'b0), | |
622 | .hw_data (1'b0), | |
623 | .cp (clk), | |
624 | .q (imu_int_en_reg_csrbus_read_data[37]) | |
625 | ); | |
626 | ||
627 | // bit 38 | |
628 | csr_sw csr_sw_38 | |
629 | ( | |
630 | // synopsys translate_off | |
631 | .omni_ld (omni_ld), | |
632 | .omni_data (omni_data[38]), | |
633 | .omni_rw_alias (1'b1), | |
634 | .omni_rw1c_alias (1'b0), | |
635 | .omni_rw1s_alias (1'b0), | |
636 | // synopsys translate_on | |
637 | .rst (rst_l_active_high), | |
638 | .rst_val (reset_msi_par_err_s_int_en[0]), | |
639 | .csr_ld (w_ld), | |
640 | .csr_data (csrbus_wr_data[38]), | |
641 | .rw_alias (1'b1), | |
642 | .rw1c_alias (1'b0), | |
643 | .rw1s_alias (1'b0), | |
644 | .hw_ld (1'b0), | |
645 | .hw_data (1'b0), | |
646 | .cp (clk), | |
647 | .q (imu_int_en_reg_csrbus_read_data[38]) | |
648 | ); | |
649 | ||
650 | // bit 39 | |
651 | csr_sw csr_sw_39 | |
652 | ( | |
653 | // synopsys translate_off | |
654 | .omni_ld (omni_ld), | |
655 | .omni_data (omni_data[39]), | |
656 | .omni_rw_alias (1'b1), | |
657 | .omni_rw1c_alias (1'b0), | |
658 | .omni_rw1s_alias (1'b0), | |
659 | // synopsys translate_on | |
660 | .rst (rst_l_active_high), | |
661 | .rst_val (reset_msi_mal_err_s_int_en[0]), | |
662 | .csr_ld (w_ld), | |
663 | .csr_data (csrbus_wr_data[39]), | |
664 | .rw_alias (1'b1), | |
665 | .rw1c_alias (1'b0), | |
666 | .rw1s_alias (1'b0), | |
667 | .hw_ld (1'b0), | |
668 | .hw_data (1'b0), | |
669 | .cp (clk), | |
670 | .q (imu_int_en_reg_csrbus_read_data[39]) | |
671 | ); | |
672 | ||
673 | // bit 40 | |
674 | csr_sw csr_sw_40 | |
675 | ( | |
676 | // synopsys translate_off | |
677 | .omni_ld (omni_ld), | |
678 | .omni_data (omni_data[40]), | |
679 | .omni_rw_alias (1'b1), | |
680 | .omni_rw1c_alias (1'b0), | |
681 | .omni_rw1s_alias (1'b0), | |
682 | // synopsys translate_on | |
683 | .rst (rst_l_active_high), | |
684 | .rst_val (reset_eq_not_en_s_int_en[0]), | |
685 | .csr_ld (w_ld), | |
686 | .csr_data (csrbus_wr_data[40]), | |
687 | .rw_alias (1'b1), | |
688 | .rw1c_alias (1'b0), | |
689 | .rw1s_alias (1'b0), | |
690 | .hw_ld (1'b0), | |
691 | .hw_data (1'b0), | |
692 | .cp (clk), | |
693 | .q (imu_int_en_reg_csrbus_read_data[40]) | |
694 | ); | |
695 | ||
696 | // bit 41 | |
697 | csr_sw csr_sw_41 | |
698 | ( | |
699 | // synopsys translate_off | |
700 | .omni_ld (omni_ld), | |
701 | .omni_data (omni_data[41]), | |
702 | .omni_rw_alias (1'b1), | |
703 | .omni_rw1c_alias (1'b0), | |
704 | .omni_rw1s_alias (1'b0), | |
705 | // synopsys translate_on | |
706 | .rst (rst_l_active_high), | |
707 | .rst_val (reset_eq_over_s_int_en[0]), | |
708 | .csr_ld (w_ld), | |
709 | .csr_data (csrbus_wr_data[41]), | |
710 | .rw_alias (1'b1), | |
711 | .rw1c_alias (1'b0), | |
712 | .rw1s_alias (1'b0), | |
713 | .hw_ld (1'b0), | |
714 | .hw_data (1'b0), | |
715 | .cp (clk), | |
716 | .q (imu_int_en_reg_csrbus_read_data[41]) | |
717 | ); | |
718 | ||
719 | // bit 42 | |
720 | csr_sw csr_sw_42 | |
721 | ( | |
722 | // synopsys translate_off | |
723 | .omni_ld (omni_ld), | |
724 | .omni_data (omni_data[42]), | |
725 | .omni_rw_alias (1'b1), | |
726 | .omni_rw1c_alias (1'b0), | |
727 | .omni_rw1s_alias (1'b0), | |
728 | // synopsys translate_on | |
729 | .rst (rst_l_active_high), | |
730 | .rst_val (reset_spare_s_int_en[0]), | |
731 | .csr_ld (w_ld), | |
732 | .csr_data (csrbus_wr_data[42]), | |
733 | .rw_alias (1'b1), | |
734 | .rw1c_alias (1'b0), | |
735 | .rw1s_alias (1'b0), | |
736 | .hw_ld (1'b0), | |
737 | .hw_data (1'b0), | |
738 | .cp (clk), | |
739 | .q (imu_int_en_reg_csrbus_read_data[42]) | |
740 | ); | |
741 | ||
742 | // bit 43 | |
743 | csr_sw csr_sw_43 | |
744 | ( | |
745 | // synopsys translate_off | |
746 | .omni_ld (omni_ld), | |
747 | .omni_data (omni_data[43]), | |
748 | .omni_rw_alias (1'b1), | |
749 | .omni_rw1c_alias (1'b0), | |
750 | .omni_rw1s_alias (1'b0), | |
751 | // synopsys translate_on | |
752 | .rst (rst_l_active_high), | |
753 | .rst_val (reset_spare_s_int_en[1]), | |
754 | .csr_ld (w_ld), | |
755 | .csr_data (csrbus_wr_data[43]), | |
756 | .rw_alias (1'b1), | |
757 | .rw1c_alias (1'b0), | |
758 | .rw1s_alias (1'b0), | |
759 | .hw_ld (1'b0), | |
760 | .hw_data (1'b0), | |
761 | .cp (clk), | |
762 | .q (imu_int_en_reg_csrbus_read_data[43]) | |
763 | ); | |
764 | ||
765 | // bit 44 | |
766 | csr_sw csr_sw_44 | |
767 | ( | |
768 | // synopsys translate_off | |
769 | .omni_ld (omni_ld), | |
770 | .omni_data (omni_data[44]), | |
771 | .omni_rw_alias (1'b1), | |
772 | .omni_rw1c_alias (1'b0), | |
773 | .omni_rw1s_alias (1'b0), | |
774 | // synopsys translate_on | |
775 | .rst (rst_l_active_high), | |
776 | .rst_val (reset_spare_s_int_en[2]), | |
777 | .csr_ld (w_ld), | |
778 | .csr_data (csrbus_wr_data[44]), | |
779 | .rw_alias (1'b1), | |
780 | .rw1c_alias (1'b0), | |
781 | .rw1s_alias (1'b0), | |
782 | .hw_ld (1'b0), | |
783 | .hw_data (1'b0), | |
784 | .cp (clk), | |
785 | .q (imu_int_en_reg_csrbus_read_data[44]) | |
786 | ); | |
787 | ||
788 | // bit 45 | |
789 | csr_sw csr_sw_45 | |
790 | ( | |
791 | // synopsys translate_off | |
792 | .omni_ld (omni_ld), | |
793 | .omni_data (omni_data[45]), | |
794 | .omni_rw_alias (1'b1), | |
795 | .omni_rw1c_alias (1'b0), | |
796 | .omni_rw1s_alias (1'b0), | |
797 | // synopsys translate_on | |
798 | .rst (rst_l_active_high), | |
799 | .rst_val (reset_spare_s_int_en[3]), | |
800 | .csr_ld (w_ld), | |
801 | .csr_data (csrbus_wr_data[45]), | |
802 | .rw_alias (1'b1), | |
803 | .rw1c_alias (1'b0), | |
804 | .rw1s_alias (1'b0), | |
805 | .hw_ld (1'b0), | |
806 | .hw_data (1'b0), | |
807 | .cp (clk), | |
808 | .q (imu_int_en_reg_csrbus_read_data[45]) | |
809 | ); | |
810 | ||
811 | // bit 46 | |
812 | csr_sw csr_sw_46 | |
813 | ( | |
814 | // synopsys translate_off | |
815 | .omni_ld (omni_ld), | |
816 | .omni_data (omni_data[46]), | |
817 | .omni_rw_alias (1'b1), | |
818 | .omni_rw1c_alias (1'b0), | |
819 | .omni_rw1s_alias (1'b0), | |
820 | // synopsys translate_on | |
821 | .rst (rst_l_active_high), | |
822 | .rst_val (reset_spare_s_int_en[4]), | |
823 | .csr_ld (w_ld), | |
824 | .csr_data (csrbus_wr_data[46]), | |
825 | .rw_alias (1'b1), | |
826 | .rw1c_alias (1'b0), | |
827 | .rw1s_alias (1'b0), | |
828 | .hw_ld (1'b0), | |
829 | .hw_data (1'b0), | |
830 | .cp (clk), | |
831 | .q (imu_int_en_reg_csrbus_read_data[46]) | |
832 | ); | |
833 | ||
834 | assign imu_int_en_reg_csrbus_read_data[47] = 1'b0; // bit 47 | |
835 | assign imu_int_en_reg_csrbus_read_data[48] = 1'b0; // bit 48 | |
836 | assign imu_int_en_reg_csrbus_read_data[49] = 1'b0; // bit 49 | |
837 | assign imu_int_en_reg_csrbus_read_data[50] = 1'b0; // bit 50 | |
838 | assign imu_int_en_reg_csrbus_read_data[51] = 1'b0; // bit 51 | |
839 | assign imu_int_en_reg_csrbus_read_data[52] = 1'b0; // bit 52 | |
840 | assign imu_int_en_reg_csrbus_read_data[53] = 1'b0; // bit 53 | |
841 | assign imu_int_en_reg_csrbus_read_data[54] = 1'b0; // bit 54 | |
842 | assign imu_int_en_reg_csrbus_read_data[55] = 1'b0; // bit 55 | |
843 | assign imu_int_en_reg_csrbus_read_data[56] = 1'b0; // bit 56 | |
844 | assign imu_int_en_reg_csrbus_read_data[57] = 1'b0; // bit 57 | |
845 | assign imu_int_en_reg_csrbus_read_data[58] = 1'b0; // bit 58 | |
846 | assign imu_int_en_reg_csrbus_read_data[59] = 1'b0; // bit 59 | |
847 | assign imu_int_en_reg_csrbus_read_data[60] = 1'b0; // bit 60 | |
848 | assign imu_int_en_reg_csrbus_read_data[61] = 1'b0; // bit 61 | |
849 | assign imu_int_en_reg_csrbus_read_data[62] = 1'b0; // bit 62 | |
850 | assign imu_int_en_reg_csrbus_read_data[63] = 1'b0; // bit 63 | |
851 | ||
852 | endmodule // dmu_imu_ics_csr_imu_int_en_reg_entry |