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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_scs_error_log_reg.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csr_imu_scs_error_log_reg | |
36 | ( | |
37 | clk, | |
38 | por_l, | |
39 | imu_scs_error_log_reg_w_ld, | |
40 | csrbus_wr_data, | |
41 | imu_scs_error_log_reg_csrbus_read_data, | |
42 | imu_scs_error_log_reg_hw_ld, | |
43 | imu_scs_error_log_reg_hw_write | |
44 | ); | |
45 | ||
46 | //==================================================================== | |
47 | // Polarity declarations | |
48 | //==================================================================== | |
49 | input clk; // Clock | |
50 | input por_l; // Reset signal | |
51 | input imu_scs_error_log_reg_w_ld; // SW load bus | |
52 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
53 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_csrbus_read_data; | |
54 | // SW read data | |
55 | input imu_scs_error_log_reg_hw_ld; // Hardware load enable for | |
56 | // imu_scs_error_log_reg. When set, <hw | |
57 | // write signal> will be loaded into | |
58 | // imu_scs_error_log_reg. | |
59 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_hw_write; | |
60 | // data bus for hw loading of imu_scs_error_log_reg. | |
61 | ||
62 | //==================================================================== | |
63 | // Type declarations | |
64 | //==================================================================== | |
65 | wire clk; // Clock | |
66 | wire por_l; // Reset signal | |
67 | wire imu_scs_error_log_reg_w_ld; // SW load bus | |
68 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
69 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_csrbus_read_data; | |
70 | // SW read data | |
71 | wire imu_scs_error_log_reg_hw_ld; // Hardware load enable for | |
72 | // imu_scs_error_log_reg. When set, <hw write | |
73 | // signal> will be loaded into | |
74 | // imu_scs_error_log_reg. | |
75 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_hw_write; | |
76 | // data bus for hw loading of imu_scs_error_log_reg. | |
77 | ||
78 | //==================================================================== | |
79 | // Logic | |
80 | //==================================================================== | |
81 | ||
82 | // synopsys translate_off | |
83 | // verilint 123 off | |
84 | // verilint 498 off | |
85 | reg omni_ld; | |
86 | reg [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] omni_data; | |
87 | ||
88 | // vlint flag_unsynthesizable_initial off | |
89 | initial | |
90 | begin | |
91 | omni_ld = 1'b0; | |
92 | omni_data = `FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH'b0; | |
93 | end// vlint flag_unsynthesizable_initial on | |
94 | ||
95 | // verilint 123 on | |
96 | // verilint 498 on | |
97 | // synopsys translate_on | |
98 | ||
99 | //----- Hardware Data Out Mux Assignments | |
100 | ||
101 | //==================================================================== | |
102 | // Instantiation of entries | |
103 | //==================================================================== | |
104 | ||
105 | //----- Entry 0 | |
106 | dmu_imu_ics_csr_imu_scs_error_log_reg_entry imu_scs_error_log_reg_0 | |
107 | ( | |
108 | // synopsys translate_off | |
109 | .omni_ld (omni_ld), | |
110 | .omni_data (omni_data), | |
111 | // synopsys translate_on | |
112 | .clk (clk), | |
113 | .por_l (por_l), | |
114 | .w_ld (imu_scs_error_log_reg_w_ld), | |
115 | .csrbus_wr_data (csrbus_wr_data), | |
116 | .imu_scs_error_log_reg_csrbus_read_data (imu_scs_error_log_reg_csrbus_read_data), | |
117 | .imu_scs_error_log_reg_hw_ld (imu_scs_error_log_reg_hw_ld), | |
118 | .imu_scs_error_log_reg_hw_write (imu_scs_error_log_reg_hw_write) | |
119 | ); | |
120 | ||
121 | endmodule // dmu_imu_ics_csr_imu_scs_error_log_reg |