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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_scs_error_log_reg_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csr_imu_scs_error_log_reg_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | por_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | imu_scs_error_log_reg_csrbus_read_data, | |
46 | imu_scs_error_log_reg_hw_ld, | |
47 | imu_scs_error_log_reg_hw_write | |
48 | ); | |
49 | ||
50 | //==================================================================== | |
51 | // Polarity declarations | |
52 | //==================================================================== | |
53 | // synopsys translate_off | |
54 | input omni_ld; // Omni load | |
55 | // vlint flag_input_port_not_connected off | |
56 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH - 1:0] omni_data; | |
57 | // Omni write data | |
58 | // synopsys translate_on | |
59 | // vlint flag_input_port_not_connected on | |
60 | input clk; // Clock signal | |
61 | input por_l; // Reset signal | |
62 | input w_ld; // SW load | |
63 | // vlint flag_input_port_not_connected off | |
64 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
65 | // vlint flag_input_port_not_connected on | |
66 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_csrbus_read_data; | |
67 | // SW read data | |
68 | input imu_scs_error_log_reg_hw_ld; // Hardware load enable for | |
69 | // imu_scs_error_log_reg. When set, <hw | |
70 | // write signal> will be loaded into | |
71 | // imu_scs_error_log_reg. | |
72 | // vlint flag_input_port_not_connected off | |
73 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH -1:0] imu_scs_error_log_reg_hw_write; | |
74 | // data bus for hw loading of imu_scs_error_log_reg. | |
75 | // vlint flag_input_port_not_connected on | |
76 | ||
77 | //==================================================================== | |
78 | // Type declarations | |
79 | //==================================================================== | |
80 | // synopsys translate_off | |
81 | wire omni_ld; // Omni load | |
82 | // vlint flag_dangling_net_within_module off | |
83 | // vlint flag_net_has_no_load off | |
84 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH - 1:0] omni_data; | |
85 | // Omni write data | |
86 | // synopsys translate_on | |
87 | // vlint flag_dangling_net_within_module on | |
88 | // vlint flag_net_has_no_load on | |
89 | wire clk; // Clock signal | |
90 | wire por_l; // Reset signal | |
91 | wire w_ld; // SW load | |
92 | // vlint flag_dangling_net_within_module off | |
93 | // vlint flag_net_has_no_load off | |
94 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
95 | // vlint flag_dangling_net_within_module on | |
96 | // vlint flag_net_has_no_load on | |
97 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH-1:0] imu_scs_error_log_reg_csrbus_read_data; | |
98 | // SW read data | |
99 | wire imu_scs_error_log_reg_hw_ld; // Hardware load enable for | |
100 | // imu_scs_error_log_reg. When set, <hw write | |
101 | // signal> will be loaded into | |
102 | // imu_scs_error_log_reg. | |
103 | // vlint flag_dangling_net_within_module off | |
104 | // vlint flag_net_has_no_load off | |
105 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH -1:0] imu_scs_error_log_reg_hw_write; | |
106 | // data bus for hw loading of imu_scs_error_log_reg. | |
107 | // vlint flag_dangling_net_within_module on | |
108 | // vlint flag_net_has_no_load on | |
109 | ||
110 | //==================================================================== | |
111 | // Logic | |
112 | //==================================================================== | |
113 | ||
114 | //----- Reset values | |
115 | // verilint 531 off | |
116 | wire [5:0] reset_type = 6'b0; | |
117 | wire [9:0] reset_length = 10'b0; | |
118 | wire [15:0] reset_req_id = 16'b0; | |
119 | wire [7:0] reset_tlp_tag = 8'b0; | |
120 | wire [7:0] reset_be_mess_code = 8'b0; | |
121 | wire [5:0] reset_eq_num = 6'b0; | |
122 | // verilint 531 on | |
123 | ||
124 | //----- Active high reset wires | |
125 | wire por_l_active_high = ~por_l; | |
126 | ||
127 | //==================================================== | |
128 | // Instantiation of flops | |
129 | //==================================================== | |
130 | ||
131 | // bit 0 | |
132 | csr_sw csr_sw_0 | |
133 | ( | |
134 | // synopsys translate_off | |
135 | .omni_ld (omni_ld), | |
136 | .omni_data (omni_data[0]), | |
137 | .omni_rw_alias (1'b1), | |
138 | .omni_rw1c_alias (1'b0), | |
139 | .omni_rw1s_alias (1'b0), | |
140 | // synopsys translate_on | |
141 | .rst (por_l_active_high), | |
142 | .rst_val (reset_eq_num[0]), | |
143 | .csr_ld (w_ld), | |
144 | .csr_data (csrbus_wr_data[0]), | |
145 | .rw_alias (1'b1), | |
146 | .rw1c_alias (1'b0), | |
147 | .rw1s_alias (1'b0), | |
148 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
149 | .hw_data (imu_scs_error_log_reg_hw_write[0]), | |
150 | .cp (clk), | |
151 | .q (imu_scs_error_log_reg_csrbus_read_data[0]) | |
152 | ); | |
153 | ||
154 | // bit 1 | |
155 | csr_sw csr_sw_1 | |
156 | ( | |
157 | // synopsys translate_off | |
158 | .omni_ld (omni_ld), | |
159 | .omni_data (omni_data[1]), | |
160 | .omni_rw_alias (1'b1), | |
161 | .omni_rw1c_alias (1'b0), | |
162 | .omni_rw1s_alias (1'b0), | |
163 | // synopsys translate_on | |
164 | .rst (por_l_active_high), | |
165 | .rst_val (reset_eq_num[1]), | |
166 | .csr_ld (w_ld), | |
167 | .csr_data (csrbus_wr_data[1]), | |
168 | .rw_alias (1'b1), | |
169 | .rw1c_alias (1'b0), | |
170 | .rw1s_alias (1'b0), | |
171 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
172 | .hw_data (imu_scs_error_log_reg_hw_write[1]), | |
173 | .cp (clk), | |
174 | .q (imu_scs_error_log_reg_csrbus_read_data[1]) | |
175 | ); | |
176 | ||
177 | // bit 2 | |
178 | csr_sw csr_sw_2 | |
179 | ( | |
180 | // synopsys translate_off | |
181 | .omni_ld (omni_ld), | |
182 | .omni_data (omni_data[2]), | |
183 | .omni_rw_alias (1'b1), | |
184 | .omni_rw1c_alias (1'b0), | |
185 | .omni_rw1s_alias (1'b0), | |
186 | // synopsys translate_on | |
187 | .rst (por_l_active_high), | |
188 | .rst_val (reset_eq_num[2]), | |
189 | .csr_ld (w_ld), | |
190 | .csr_data (csrbus_wr_data[2]), | |
191 | .rw_alias (1'b1), | |
192 | .rw1c_alias (1'b0), | |
193 | .rw1s_alias (1'b0), | |
194 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
195 | .hw_data (imu_scs_error_log_reg_hw_write[2]), | |
196 | .cp (clk), | |
197 | .q (imu_scs_error_log_reg_csrbus_read_data[2]) | |
198 | ); | |
199 | ||
200 | // bit 3 | |
201 | csr_sw csr_sw_3 | |
202 | ( | |
203 | // synopsys translate_off | |
204 | .omni_ld (omni_ld), | |
205 | .omni_data (omni_data[3]), | |
206 | .omni_rw_alias (1'b1), | |
207 | .omni_rw1c_alias (1'b0), | |
208 | .omni_rw1s_alias (1'b0), | |
209 | // synopsys translate_on | |
210 | .rst (por_l_active_high), | |
211 | .rst_val (reset_eq_num[3]), | |
212 | .csr_ld (w_ld), | |
213 | .csr_data (csrbus_wr_data[3]), | |
214 | .rw_alias (1'b1), | |
215 | .rw1c_alias (1'b0), | |
216 | .rw1s_alias (1'b0), | |
217 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
218 | .hw_data (imu_scs_error_log_reg_hw_write[3]), | |
219 | .cp (clk), | |
220 | .q (imu_scs_error_log_reg_csrbus_read_data[3]) | |
221 | ); | |
222 | ||
223 | // bit 4 | |
224 | csr_sw csr_sw_4 | |
225 | ( | |
226 | // synopsys translate_off | |
227 | .omni_ld (omni_ld), | |
228 | .omni_data (omni_data[4]), | |
229 | .omni_rw_alias (1'b1), | |
230 | .omni_rw1c_alias (1'b0), | |
231 | .omni_rw1s_alias (1'b0), | |
232 | // synopsys translate_on | |
233 | .rst (por_l_active_high), | |
234 | .rst_val (reset_eq_num[4]), | |
235 | .csr_ld (w_ld), | |
236 | .csr_data (csrbus_wr_data[4]), | |
237 | .rw_alias (1'b1), | |
238 | .rw1c_alias (1'b0), | |
239 | .rw1s_alias (1'b0), | |
240 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
241 | .hw_data (imu_scs_error_log_reg_hw_write[4]), | |
242 | .cp (clk), | |
243 | .q (imu_scs_error_log_reg_csrbus_read_data[4]) | |
244 | ); | |
245 | ||
246 | // bit 5 | |
247 | csr_sw csr_sw_5 | |
248 | ( | |
249 | // synopsys translate_off | |
250 | .omni_ld (omni_ld), | |
251 | .omni_data (omni_data[5]), | |
252 | .omni_rw_alias (1'b1), | |
253 | .omni_rw1c_alias (1'b0), | |
254 | .omni_rw1s_alias (1'b0), | |
255 | // synopsys translate_on | |
256 | .rst (por_l_active_high), | |
257 | .rst_val (reset_eq_num[5]), | |
258 | .csr_ld (w_ld), | |
259 | .csr_data (csrbus_wr_data[5]), | |
260 | .rw_alias (1'b1), | |
261 | .rw1c_alias (1'b0), | |
262 | .rw1s_alias (1'b0), | |
263 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
264 | .hw_data (imu_scs_error_log_reg_hw_write[5]), | |
265 | .cp (clk), | |
266 | .q (imu_scs_error_log_reg_csrbus_read_data[5]) | |
267 | ); | |
268 | ||
269 | assign imu_scs_error_log_reg_csrbus_read_data[6] = 1'b0; // bit 6 | |
270 | assign imu_scs_error_log_reg_csrbus_read_data[7] = 1'b0; // bit 7 | |
271 | assign imu_scs_error_log_reg_csrbus_read_data[8] = 1'b0; // bit 8 | |
272 | assign imu_scs_error_log_reg_csrbus_read_data[9] = 1'b0; // bit 9 | |
273 | assign imu_scs_error_log_reg_csrbus_read_data[10] = 1'b0; // bit 10 | |
274 | assign imu_scs_error_log_reg_csrbus_read_data[11] = 1'b0; // bit 11 | |
275 | assign imu_scs_error_log_reg_csrbus_read_data[12] = 1'b0; // bit 12 | |
276 | assign imu_scs_error_log_reg_csrbus_read_data[13] = 1'b0; // bit 13 | |
277 | assign imu_scs_error_log_reg_csrbus_read_data[14] = 1'b0; // bit 14 | |
278 | assign imu_scs_error_log_reg_csrbus_read_data[15] = 1'b0; // bit 15 | |
279 | // bit 16 | |
280 | csr_sw csr_sw_16 | |
281 | ( | |
282 | // synopsys translate_off | |
283 | .omni_ld (omni_ld), | |
284 | .omni_data (omni_data[16]), | |
285 | .omni_rw_alias (1'b1), | |
286 | .omni_rw1c_alias (1'b0), | |
287 | .omni_rw1s_alias (1'b0), | |
288 | // synopsys translate_on | |
289 | .rst (por_l_active_high), | |
290 | .rst_val (reset_be_mess_code[0]), | |
291 | .csr_ld (w_ld), | |
292 | .csr_data (csrbus_wr_data[16]), | |
293 | .rw_alias (1'b1), | |
294 | .rw1c_alias (1'b0), | |
295 | .rw1s_alias (1'b0), | |
296 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
297 | .hw_data (imu_scs_error_log_reg_hw_write[16]), | |
298 | .cp (clk), | |
299 | .q (imu_scs_error_log_reg_csrbus_read_data[16]) | |
300 | ); | |
301 | ||
302 | // bit 17 | |
303 | csr_sw csr_sw_17 | |
304 | ( | |
305 | // synopsys translate_off | |
306 | .omni_ld (omni_ld), | |
307 | .omni_data (omni_data[17]), | |
308 | .omni_rw_alias (1'b1), | |
309 | .omni_rw1c_alias (1'b0), | |
310 | .omni_rw1s_alias (1'b0), | |
311 | // synopsys translate_on | |
312 | .rst (por_l_active_high), | |
313 | .rst_val (reset_be_mess_code[1]), | |
314 | .csr_ld (w_ld), | |
315 | .csr_data (csrbus_wr_data[17]), | |
316 | .rw_alias (1'b1), | |
317 | .rw1c_alias (1'b0), | |
318 | .rw1s_alias (1'b0), | |
319 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
320 | .hw_data (imu_scs_error_log_reg_hw_write[17]), | |
321 | .cp (clk), | |
322 | .q (imu_scs_error_log_reg_csrbus_read_data[17]) | |
323 | ); | |
324 | ||
325 | // bit 18 | |
326 | csr_sw csr_sw_18 | |
327 | ( | |
328 | // synopsys translate_off | |
329 | .omni_ld (omni_ld), | |
330 | .omni_data (omni_data[18]), | |
331 | .omni_rw_alias (1'b1), | |
332 | .omni_rw1c_alias (1'b0), | |
333 | .omni_rw1s_alias (1'b0), | |
334 | // synopsys translate_on | |
335 | .rst (por_l_active_high), | |
336 | .rst_val (reset_be_mess_code[2]), | |
337 | .csr_ld (w_ld), | |
338 | .csr_data (csrbus_wr_data[18]), | |
339 | .rw_alias (1'b1), | |
340 | .rw1c_alias (1'b0), | |
341 | .rw1s_alias (1'b0), | |
342 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
343 | .hw_data (imu_scs_error_log_reg_hw_write[18]), | |
344 | .cp (clk), | |
345 | .q (imu_scs_error_log_reg_csrbus_read_data[18]) | |
346 | ); | |
347 | ||
348 | // bit 19 | |
349 | csr_sw csr_sw_19 | |
350 | ( | |
351 | // synopsys translate_off | |
352 | .omni_ld (omni_ld), | |
353 | .omni_data (omni_data[19]), | |
354 | .omni_rw_alias (1'b1), | |
355 | .omni_rw1c_alias (1'b0), | |
356 | .omni_rw1s_alias (1'b0), | |
357 | // synopsys translate_on | |
358 | .rst (por_l_active_high), | |
359 | .rst_val (reset_be_mess_code[3]), | |
360 | .csr_ld (w_ld), | |
361 | .csr_data (csrbus_wr_data[19]), | |
362 | .rw_alias (1'b1), | |
363 | .rw1c_alias (1'b0), | |
364 | .rw1s_alias (1'b0), | |
365 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
366 | .hw_data (imu_scs_error_log_reg_hw_write[19]), | |
367 | .cp (clk), | |
368 | .q (imu_scs_error_log_reg_csrbus_read_data[19]) | |
369 | ); | |
370 | ||
371 | // bit 20 | |
372 | csr_sw csr_sw_20 | |
373 | ( | |
374 | // synopsys translate_off | |
375 | .omni_ld (omni_ld), | |
376 | .omni_data (omni_data[20]), | |
377 | .omni_rw_alias (1'b1), | |
378 | .omni_rw1c_alias (1'b0), | |
379 | .omni_rw1s_alias (1'b0), | |
380 | // synopsys translate_on | |
381 | .rst (por_l_active_high), | |
382 | .rst_val (reset_be_mess_code[4]), | |
383 | .csr_ld (w_ld), | |
384 | .csr_data (csrbus_wr_data[20]), | |
385 | .rw_alias (1'b1), | |
386 | .rw1c_alias (1'b0), | |
387 | .rw1s_alias (1'b0), | |
388 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
389 | .hw_data (imu_scs_error_log_reg_hw_write[20]), | |
390 | .cp (clk), | |
391 | .q (imu_scs_error_log_reg_csrbus_read_data[20]) | |
392 | ); | |
393 | ||
394 | // bit 21 | |
395 | csr_sw csr_sw_21 | |
396 | ( | |
397 | // synopsys translate_off | |
398 | .omni_ld (omni_ld), | |
399 | .omni_data (omni_data[21]), | |
400 | .omni_rw_alias (1'b1), | |
401 | .omni_rw1c_alias (1'b0), | |
402 | .omni_rw1s_alias (1'b0), | |
403 | // synopsys translate_on | |
404 | .rst (por_l_active_high), | |
405 | .rst_val (reset_be_mess_code[5]), | |
406 | .csr_ld (w_ld), | |
407 | .csr_data (csrbus_wr_data[21]), | |
408 | .rw_alias (1'b1), | |
409 | .rw1c_alias (1'b0), | |
410 | .rw1s_alias (1'b0), | |
411 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
412 | .hw_data (imu_scs_error_log_reg_hw_write[21]), | |
413 | .cp (clk), | |
414 | .q (imu_scs_error_log_reg_csrbus_read_data[21]) | |
415 | ); | |
416 | ||
417 | // bit 22 | |
418 | csr_sw csr_sw_22 | |
419 | ( | |
420 | // synopsys translate_off | |
421 | .omni_ld (omni_ld), | |
422 | .omni_data (omni_data[22]), | |
423 | .omni_rw_alias (1'b1), | |
424 | .omni_rw1c_alias (1'b0), | |
425 | .omni_rw1s_alias (1'b0), | |
426 | // synopsys translate_on | |
427 | .rst (por_l_active_high), | |
428 | .rst_val (reset_be_mess_code[6]), | |
429 | .csr_ld (w_ld), | |
430 | .csr_data (csrbus_wr_data[22]), | |
431 | .rw_alias (1'b1), | |
432 | .rw1c_alias (1'b0), | |
433 | .rw1s_alias (1'b0), | |
434 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
435 | .hw_data (imu_scs_error_log_reg_hw_write[22]), | |
436 | .cp (clk), | |
437 | .q (imu_scs_error_log_reg_csrbus_read_data[22]) | |
438 | ); | |
439 | ||
440 | // bit 23 | |
441 | csr_sw csr_sw_23 | |
442 | ( | |
443 | // synopsys translate_off | |
444 | .omni_ld (omni_ld), | |
445 | .omni_data (omni_data[23]), | |
446 | .omni_rw_alias (1'b1), | |
447 | .omni_rw1c_alias (1'b0), | |
448 | .omni_rw1s_alias (1'b0), | |
449 | // synopsys translate_on | |
450 | .rst (por_l_active_high), | |
451 | .rst_val (reset_be_mess_code[7]), | |
452 | .csr_ld (w_ld), | |
453 | .csr_data (csrbus_wr_data[23]), | |
454 | .rw_alias (1'b1), | |
455 | .rw1c_alias (1'b0), | |
456 | .rw1s_alias (1'b0), | |
457 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
458 | .hw_data (imu_scs_error_log_reg_hw_write[23]), | |
459 | .cp (clk), | |
460 | .q (imu_scs_error_log_reg_csrbus_read_data[23]) | |
461 | ); | |
462 | ||
463 | // bit 24 | |
464 | csr_sw csr_sw_24 | |
465 | ( | |
466 | // synopsys translate_off | |
467 | .omni_ld (omni_ld), | |
468 | .omni_data (omni_data[24]), | |
469 | .omni_rw_alias (1'b1), | |
470 | .omni_rw1c_alias (1'b0), | |
471 | .omni_rw1s_alias (1'b0), | |
472 | // synopsys translate_on | |
473 | .rst (por_l_active_high), | |
474 | .rst_val (reset_tlp_tag[0]), | |
475 | .csr_ld (w_ld), | |
476 | .csr_data (csrbus_wr_data[24]), | |
477 | .rw_alias (1'b1), | |
478 | .rw1c_alias (1'b0), | |
479 | .rw1s_alias (1'b0), | |
480 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
481 | .hw_data (imu_scs_error_log_reg_hw_write[24]), | |
482 | .cp (clk), | |
483 | .q (imu_scs_error_log_reg_csrbus_read_data[24]) | |
484 | ); | |
485 | ||
486 | // bit 25 | |
487 | csr_sw csr_sw_25 | |
488 | ( | |
489 | // synopsys translate_off | |
490 | .omni_ld (omni_ld), | |
491 | .omni_data (omni_data[25]), | |
492 | .omni_rw_alias (1'b1), | |
493 | .omni_rw1c_alias (1'b0), | |
494 | .omni_rw1s_alias (1'b0), | |
495 | // synopsys translate_on | |
496 | .rst (por_l_active_high), | |
497 | .rst_val (reset_tlp_tag[1]), | |
498 | .csr_ld (w_ld), | |
499 | .csr_data (csrbus_wr_data[25]), | |
500 | .rw_alias (1'b1), | |
501 | .rw1c_alias (1'b0), | |
502 | .rw1s_alias (1'b0), | |
503 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
504 | .hw_data (imu_scs_error_log_reg_hw_write[25]), | |
505 | .cp (clk), | |
506 | .q (imu_scs_error_log_reg_csrbus_read_data[25]) | |
507 | ); | |
508 | ||
509 | // bit 26 | |
510 | csr_sw csr_sw_26 | |
511 | ( | |
512 | // synopsys translate_off | |
513 | .omni_ld (omni_ld), | |
514 | .omni_data (omni_data[26]), | |
515 | .omni_rw_alias (1'b1), | |
516 | .omni_rw1c_alias (1'b0), | |
517 | .omni_rw1s_alias (1'b0), | |
518 | // synopsys translate_on | |
519 | .rst (por_l_active_high), | |
520 | .rst_val (reset_tlp_tag[2]), | |
521 | .csr_ld (w_ld), | |
522 | .csr_data (csrbus_wr_data[26]), | |
523 | .rw_alias (1'b1), | |
524 | .rw1c_alias (1'b0), | |
525 | .rw1s_alias (1'b0), | |
526 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
527 | .hw_data (imu_scs_error_log_reg_hw_write[26]), | |
528 | .cp (clk), | |
529 | .q (imu_scs_error_log_reg_csrbus_read_data[26]) | |
530 | ); | |
531 | ||
532 | // bit 27 | |
533 | csr_sw csr_sw_27 | |
534 | ( | |
535 | // synopsys translate_off | |
536 | .omni_ld (omni_ld), | |
537 | .omni_data (omni_data[27]), | |
538 | .omni_rw_alias (1'b1), | |
539 | .omni_rw1c_alias (1'b0), | |
540 | .omni_rw1s_alias (1'b0), | |
541 | // synopsys translate_on | |
542 | .rst (por_l_active_high), | |
543 | .rst_val (reset_tlp_tag[3]), | |
544 | .csr_ld (w_ld), | |
545 | .csr_data (csrbus_wr_data[27]), | |
546 | .rw_alias (1'b1), | |
547 | .rw1c_alias (1'b0), | |
548 | .rw1s_alias (1'b0), | |
549 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
550 | .hw_data (imu_scs_error_log_reg_hw_write[27]), | |
551 | .cp (clk), | |
552 | .q (imu_scs_error_log_reg_csrbus_read_data[27]) | |
553 | ); | |
554 | ||
555 | // bit 28 | |
556 | csr_sw csr_sw_28 | |
557 | ( | |
558 | // synopsys translate_off | |
559 | .omni_ld (omni_ld), | |
560 | .omni_data (omni_data[28]), | |
561 | .omni_rw_alias (1'b1), | |
562 | .omni_rw1c_alias (1'b0), | |
563 | .omni_rw1s_alias (1'b0), | |
564 | // synopsys translate_on | |
565 | .rst (por_l_active_high), | |
566 | .rst_val (reset_tlp_tag[4]), | |
567 | .csr_ld (w_ld), | |
568 | .csr_data (csrbus_wr_data[28]), | |
569 | .rw_alias (1'b1), | |
570 | .rw1c_alias (1'b0), | |
571 | .rw1s_alias (1'b0), | |
572 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
573 | .hw_data (imu_scs_error_log_reg_hw_write[28]), | |
574 | .cp (clk), | |
575 | .q (imu_scs_error_log_reg_csrbus_read_data[28]) | |
576 | ); | |
577 | ||
578 | // bit 29 | |
579 | csr_sw csr_sw_29 | |
580 | ( | |
581 | // synopsys translate_off | |
582 | .omni_ld (omni_ld), | |
583 | .omni_data (omni_data[29]), | |
584 | .omni_rw_alias (1'b1), | |
585 | .omni_rw1c_alias (1'b0), | |
586 | .omni_rw1s_alias (1'b0), | |
587 | // synopsys translate_on | |
588 | .rst (por_l_active_high), | |
589 | .rst_val (reset_tlp_tag[5]), | |
590 | .csr_ld (w_ld), | |
591 | .csr_data (csrbus_wr_data[29]), | |
592 | .rw_alias (1'b1), | |
593 | .rw1c_alias (1'b0), | |
594 | .rw1s_alias (1'b0), | |
595 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
596 | .hw_data (imu_scs_error_log_reg_hw_write[29]), | |
597 | .cp (clk), | |
598 | .q (imu_scs_error_log_reg_csrbus_read_data[29]) | |
599 | ); | |
600 | ||
601 | // bit 30 | |
602 | csr_sw csr_sw_30 | |
603 | ( | |
604 | // synopsys translate_off | |
605 | .omni_ld (omni_ld), | |
606 | .omni_data (omni_data[30]), | |
607 | .omni_rw_alias (1'b1), | |
608 | .omni_rw1c_alias (1'b0), | |
609 | .omni_rw1s_alias (1'b0), | |
610 | // synopsys translate_on | |
611 | .rst (por_l_active_high), | |
612 | .rst_val (reset_tlp_tag[6]), | |
613 | .csr_ld (w_ld), | |
614 | .csr_data (csrbus_wr_data[30]), | |
615 | .rw_alias (1'b1), | |
616 | .rw1c_alias (1'b0), | |
617 | .rw1s_alias (1'b0), | |
618 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
619 | .hw_data (imu_scs_error_log_reg_hw_write[30]), | |
620 | .cp (clk), | |
621 | .q (imu_scs_error_log_reg_csrbus_read_data[30]) | |
622 | ); | |
623 | ||
624 | // bit 31 | |
625 | csr_sw csr_sw_31 | |
626 | ( | |
627 | // synopsys translate_off | |
628 | .omni_ld (omni_ld), | |
629 | .omni_data (omni_data[31]), | |
630 | .omni_rw_alias (1'b1), | |
631 | .omni_rw1c_alias (1'b0), | |
632 | .omni_rw1s_alias (1'b0), | |
633 | // synopsys translate_on | |
634 | .rst (por_l_active_high), | |
635 | .rst_val (reset_tlp_tag[7]), | |
636 | .csr_ld (w_ld), | |
637 | .csr_data (csrbus_wr_data[31]), | |
638 | .rw_alias (1'b1), | |
639 | .rw1c_alias (1'b0), | |
640 | .rw1s_alias (1'b0), | |
641 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
642 | .hw_data (imu_scs_error_log_reg_hw_write[31]), | |
643 | .cp (clk), | |
644 | .q (imu_scs_error_log_reg_csrbus_read_data[31]) | |
645 | ); | |
646 | ||
647 | // bit 32 | |
648 | csr_sw csr_sw_32 | |
649 | ( | |
650 | // synopsys translate_off | |
651 | .omni_ld (omni_ld), | |
652 | .omni_data (omni_data[32]), | |
653 | .omni_rw_alias (1'b1), | |
654 | .omni_rw1c_alias (1'b0), | |
655 | .omni_rw1s_alias (1'b0), | |
656 | // synopsys translate_on | |
657 | .rst (por_l_active_high), | |
658 | .rst_val (reset_req_id[0]), | |
659 | .csr_ld (w_ld), | |
660 | .csr_data (csrbus_wr_data[32]), | |
661 | .rw_alias (1'b1), | |
662 | .rw1c_alias (1'b0), | |
663 | .rw1s_alias (1'b0), | |
664 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
665 | .hw_data (imu_scs_error_log_reg_hw_write[32]), | |
666 | .cp (clk), | |
667 | .q (imu_scs_error_log_reg_csrbus_read_data[32]) | |
668 | ); | |
669 | ||
670 | // bit 33 | |
671 | csr_sw csr_sw_33 | |
672 | ( | |
673 | // synopsys translate_off | |
674 | .omni_ld (omni_ld), | |
675 | .omni_data (omni_data[33]), | |
676 | .omni_rw_alias (1'b1), | |
677 | .omni_rw1c_alias (1'b0), | |
678 | .omni_rw1s_alias (1'b0), | |
679 | // synopsys translate_on | |
680 | .rst (por_l_active_high), | |
681 | .rst_val (reset_req_id[1]), | |
682 | .csr_ld (w_ld), | |
683 | .csr_data (csrbus_wr_data[33]), | |
684 | .rw_alias (1'b1), | |
685 | .rw1c_alias (1'b0), | |
686 | .rw1s_alias (1'b0), | |
687 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
688 | .hw_data (imu_scs_error_log_reg_hw_write[33]), | |
689 | .cp (clk), | |
690 | .q (imu_scs_error_log_reg_csrbus_read_data[33]) | |
691 | ); | |
692 | ||
693 | // bit 34 | |
694 | csr_sw csr_sw_34 | |
695 | ( | |
696 | // synopsys translate_off | |
697 | .omni_ld (omni_ld), | |
698 | .omni_data (omni_data[34]), | |
699 | .omni_rw_alias (1'b1), | |
700 | .omni_rw1c_alias (1'b0), | |
701 | .omni_rw1s_alias (1'b0), | |
702 | // synopsys translate_on | |
703 | .rst (por_l_active_high), | |
704 | .rst_val (reset_req_id[2]), | |
705 | .csr_ld (w_ld), | |
706 | .csr_data (csrbus_wr_data[34]), | |
707 | .rw_alias (1'b1), | |
708 | .rw1c_alias (1'b0), | |
709 | .rw1s_alias (1'b0), | |
710 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
711 | .hw_data (imu_scs_error_log_reg_hw_write[34]), | |
712 | .cp (clk), | |
713 | .q (imu_scs_error_log_reg_csrbus_read_data[34]) | |
714 | ); | |
715 | ||
716 | // bit 35 | |
717 | csr_sw csr_sw_35 | |
718 | ( | |
719 | // synopsys translate_off | |
720 | .omni_ld (omni_ld), | |
721 | .omni_data (omni_data[35]), | |
722 | .omni_rw_alias (1'b1), | |
723 | .omni_rw1c_alias (1'b0), | |
724 | .omni_rw1s_alias (1'b0), | |
725 | // synopsys translate_on | |
726 | .rst (por_l_active_high), | |
727 | .rst_val (reset_req_id[3]), | |
728 | .csr_ld (w_ld), | |
729 | .csr_data (csrbus_wr_data[35]), | |
730 | .rw_alias (1'b1), | |
731 | .rw1c_alias (1'b0), | |
732 | .rw1s_alias (1'b0), | |
733 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
734 | .hw_data (imu_scs_error_log_reg_hw_write[35]), | |
735 | .cp (clk), | |
736 | .q (imu_scs_error_log_reg_csrbus_read_data[35]) | |
737 | ); | |
738 | ||
739 | // bit 36 | |
740 | csr_sw csr_sw_36 | |
741 | ( | |
742 | // synopsys translate_off | |
743 | .omni_ld (omni_ld), | |
744 | .omni_data (omni_data[36]), | |
745 | .omni_rw_alias (1'b1), | |
746 | .omni_rw1c_alias (1'b0), | |
747 | .omni_rw1s_alias (1'b0), | |
748 | // synopsys translate_on | |
749 | .rst (por_l_active_high), | |
750 | .rst_val (reset_req_id[4]), | |
751 | .csr_ld (w_ld), | |
752 | .csr_data (csrbus_wr_data[36]), | |
753 | .rw_alias (1'b1), | |
754 | .rw1c_alias (1'b0), | |
755 | .rw1s_alias (1'b0), | |
756 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
757 | .hw_data (imu_scs_error_log_reg_hw_write[36]), | |
758 | .cp (clk), | |
759 | .q (imu_scs_error_log_reg_csrbus_read_data[36]) | |
760 | ); | |
761 | ||
762 | // bit 37 | |
763 | csr_sw csr_sw_37 | |
764 | ( | |
765 | // synopsys translate_off | |
766 | .omni_ld (omni_ld), | |
767 | .omni_data (omni_data[37]), | |
768 | .omni_rw_alias (1'b1), | |
769 | .omni_rw1c_alias (1'b0), | |
770 | .omni_rw1s_alias (1'b0), | |
771 | // synopsys translate_on | |
772 | .rst (por_l_active_high), | |
773 | .rst_val (reset_req_id[5]), | |
774 | .csr_ld (w_ld), | |
775 | .csr_data (csrbus_wr_data[37]), | |
776 | .rw_alias (1'b1), | |
777 | .rw1c_alias (1'b0), | |
778 | .rw1s_alias (1'b0), | |
779 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
780 | .hw_data (imu_scs_error_log_reg_hw_write[37]), | |
781 | .cp (clk), | |
782 | .q (imu_scs_error_log_reg_csrbus_read_data[37]) | |
783 | ); | |
784 | ||
785 | // bit 38 | |
786 | csr_sw csr_sw_38 | |
787 | ( | |
788 | // synopsys translate_off | |
789 | .omni_ld (omni_ld), | |
790 | .omni_data (omni_data[38]), | |
791 | .omni_rw_alias (1'b1), | |
792 | .omni_rw1c_alias (1'b0), | |
793 | .omni_rw1s_alias (1'b0), | |
794 | // synopsys translate_on | |
795 | .rst (por_l_active_high), | |
796 | .rst_val (reset_req_id[6]), | |
797 | .csr_ld (w_ld), | |
798 | .csr_data (csrbus_wr_data[38]), | |
799 | .rw_alias (1'b1), | |
800 | .rw1c_alias (1'b0), | |
801 | .rw1s_alias (1'b0), | |
802 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
803 | .hw_data (imu_scs_error_log_reg_hw_write[38]), | |
804 | .cp (clk), | |
805 | .q (imu_scs_error_log_reg_csrbus_read_data[38]) | |
806 | ); | |
807 | ||
808 | // bit 39 | |
809 | csr_sw csr_sw_39 | |
810 | ( | |
811 | // synopsys translate_off | |
812 | .omni_ld (omni_ld), | |
813 | .omni_data (omni_data[39]), | |
814 | .omni_rw_alias (1'b1), | |
815 | .omni_rw1c_alias (1'b0), | |
816 | .omni_rw1s_alias (1'b0), | |
817 | // synopsys translate_on | |
818 | .rst (por_l_active_high), | |
819 | .rst_val (reset_req_id[7]), | |
820 | .csr_ld (w_ld), | |
821 | .csr_data (csrbus_wr_data[39]), | |
822 | .rw_alias (1'b1), | |
823 | .rw1c_alias (1'b0), | |
824 | .rw1s_alias (1'b0), | |
825 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
826 | .hw_data (imu_scs_error_log_reg_hw_write[39]), | |
827 | .cp (clk), | |
828 | .q (imu_scs_error_log_reg_csrbus_read_data[39]) | |
829 | ); | |
830 | ||
831 | // bit 40 | |
832 | csr_sw csr_sw_40 | |
833 | ( | |
834 | // synopsys translate_off | |
835 | .omni_ld (omni_ld), | |
836 | .omni_data (omni_data[40]), | |
837 | .omni_rw_alias (1'b1), | |
838 | .omni_rw1c_alias (1'b0), | |
839 | .omni_rw1s_alias (1'b0), | |
840 | // synopsys translate_on | |
841 | .rst (por_l_active_high), | |
842 | .rst_val (reset_req_id[8]), | |
843 | .csr_ld (w_ld), | |
844 | .csr_data (csrbus_wr_data[40]), | |
845 | .rw_alias (1'b1), | |
846 | .rw1c_alias (1'b0), | |
847 | .rw1s_alias (1'b0), | |
848 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
849 | .hw_data (imu_scs_error_log_reg_hw_write[40]), | |
850 | .cp (clk), | |
851 | .q (imu_scs_error_log_reg_csrbus_read_data[40]) | |
852 | ); | |
853 | ||
854 | // bit 41 | |
855 | csr_sw csr_sw_41 | |
856 | ( | |
857 | // synopsys translate_off | |
858 | .omni_ld (omni_ld), | |
859 | .omni_data (omni_data[41]), | |
860 | .omni_rw_alias (1'b1), | |
861 | .omni_rw1c_alias (1'b0), | |
862 | .omni_rw1s_alias (1'b0), | |
863 | // synopsys translate_on | |
864 | .rst (por_l_active_high), | |
865 | .rst_val (reset_req_id[9]), | |
866 | .csr_ld (w_ld), | |
867 | .csr_data (csrbus_wr_data[41]), | |
868 | .rw_alias (1'b1), | |
869 | .rw1c_alias (1'b0), | |
870 | .rw1s_alias (1'b0), | |
871 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
872 | .hw_data (imu_scs_error_log_reg_hw_write[41]), | |
873 | .cp (clk), | |
874 | .q (imu_scs_error_log_reg_csrbus_read_data[41]) | |
875 | ); | |
876 | ||
877 | // bit 42 | |
878 | csr_sw csr_sw_42 | |
879 | ( | |
880 | // synopsys translate_off | |
881 | .omni_ld (omni_ld), | |
882 | .omni_data (omni_data[42]), | |
883 | .omni_rw_alias (1'b1), | |
884 | .omni_rw1c_alias (1'b0), | |
885 | .omni_rw1s_alias (1'b0), | |
886 | // synopsys translate_on | |
887 | .rst (por_l_active_high), | |
888 | .rst_val (reset_req_id[10]), | |
889 | .csr_ld (w_ld), | |
890 | .csr_data (csrbus_wr_data[42]), | |
891 | .rw_alias (1'b1), | |
892 | .rw1c_alias (1'b0), | |
893 | .rw1s_alias (1'b0), | |
894 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
895 | .hw_data (imu_scs_error_log_reg_hw_write[42]), | |
896 | .cp (clk), | |
897 | .q (imu_scs_error_log_reg_csrbus_read_data[42]) | |
898 | ); | |
899 | ||
900 | // bit 43 | |
901 | csr_sw csr_sw_43 | |
902 | ( | |
903 | // synopsys translate_off | |
904 | .omni_ld (omni_ld), | |
905 | .omni_data (omni_data[43]), | |
906 | .omni_rw_alias (1'b1), | |
907 | .omni_rw1c_alias (1'b0), | |
908 | .omni_rw1s_alias (1'b0), | |
909 | // synopsys translate_on | |
910 | .rst (por_l_active_high), | |
911 | .rst_val (reset_req_id[11]), | |
912 | .csr_ld (w_ld), | |
913 | .csr_data (csrbus_wr_data[43]), | |
914 | .rw_alias (1'b1), | |
915 | .rw1c_alias (1'b0), | |
916 | .rw1s_alias (1'b0), | |
917 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
918 | .hw_data (imu_scs_error_log_reg_hw_write[43]), | |
919 | .cp (clk), | |
920 | .q (imu_scs_error_log_reg_csrbus_read_data[43]) | |
921 | ); | |
922 | ||
923 | // bit 44 | |
924 | csr_sw csr_sw_44 | |
925 | ( | |
926 | // synopsys translate_off | |
927 | .omni_ld (omni_ld), | |
928 | .omni_data (omni_data[44]), | |
929 | .omni_rw_alias (1'b1), | |
930 | .omni_rw1c_alias (1'b0), | |
931 | .omni_rw1s_alias (1'b0), | |
932 | // synopsys translate_on | |
933 | .rst (por_l_active_high), | |
934 | .rst_val (reset_req_id[12]), | |
935 | .csr_ld (w_ld), | |
936 | .csr_data (csrbus_wr_data[44]), | |
937 | .rw_alias (1'b1), | |
938 | .rw1c_alias (1'b0), | |
939 | .rw1s_alias (1'b0), | |
940 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
941 | .hw_data (imu_scs_error_log_reg_hw_write[44]), | |
942 | .cp (clk), | |
943 | .q (imu_scs_error_log_reg_csrbus_read_data[44]) | |
944 | ); | |
945 | ||
946 | // bit 45 | |
947 | csr_sw csr_sw_45 | |
948 | ( | |
949 | // synopsys translate_off | |
950 | .omni_ld (omni_ld), | |
951 | .omni_data (omni_data[45]), | |
952 | .omni_rw_alias (1'b1), | |
953 | .omni_rw1c_alias (1'b0), | |
954 | .omni_rw1s_alias (1'b0), | |
955 | // synopsys translate_on | |
956 | .rst (por_l_active_high), | |
957 | .rst_val (reset_req_id[13]), | |
958 | .csr_ld (w_ld), | |
959 | .csr_data (csrbus_wr_data[45]), | |
960 | .rw_alias (1'b1), | |
961 | .rw1c_alias (1'b0), | |
962 | .rw1s_alias (1'b0), | |
963 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
964 | .hw_data (imu_scs_error_log_reg_hw_write[45]), | |
965 | .cp (clk), | |
966 | .q (imu_scs_error_log_reg_csrbus_read_data[45]) | |
967 | ); | |
968 | ||
969 | // bit 46 | |
970 | csr_sw csr_sw_46 | |
971 | ( | |
972 | // synopsys translate_off | |
973 | .omni_ld (omni_ld), | |
974 | .omni_data (omni_data[46]), | |
975 | .omni_rw_alias (1'b1), | |
976 | .omni_rw1c_alias (1'b0), | |
977 | .omni_rw1s_alias (1'b0), | |
978 | // synopsys translate_on | |
979 | .rst (por_l_active_high), | |
980 | .rst_val (reset_req_id[14]), | |
981 | .csr_ld (w_ld), | |
982 | .csr_data (csrbus_wr_data[46]), | |
983 | .rw_alias (1'b1), | |
984 | .rw1c_alias (1'b0), | |
985 | .rw1s_alias (1'b0), | |
986 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
987 | .hw_data (imu_scs_error_log_reg_hw_write[46]), | |
988 | .cp (clk), | |
989 | .q (imu_scs_error_log_reg_csrbus_read_data[46]) | |
990 | ); | |
991 | ||
992 | // bit 47 | |
993 | csr_sw csr_sw_47 | |
994 | ( | |
995 | // synopsys translate_off | |
996 | .omni_ld (omni_ld), | |
997 | .omni_data (omni_data[47]), | |
998 | .omni_rw_alias (1'b1), | |
999 | .omni_rw1c_alias (1'b0), | |
1000 | .omni_rw1s_alias (1'b0), | |
1001 | // synopsys translate_on | |
1002 | .rst (por_l_active_high), | |
1003 | .rst_val (reset_req_id[15]), | |
1004 | .csr_ld (w_ld), | |
1005 | .csr_data (csrbus_wr_data[47]), | |
1006 | .rw_alias (1'b1), | |
1007 | .rw1c_alias (1'b0), | |
1008 | .rw1s_alias (1'b0), | |
1009 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1010 | .hw_data (imu_scs_error_log_reg_hw_write[47]), | |
1011 | .cp (clk), | |
1012 | .q (imu_scs_error_log_reg_csrbus_read_data[47]) | |
1013 | ); | |
1014 | ||
1015 | // bit 48 | |
1016 | csr_sw csr_sw_48 | |
1017 | ( | |
1018 | // synopsys translate_off | |
1019 | .omni_ld (omni_ld), | |
1020 | .omni_data (omni_data[48]), | |
1021 | .omni_rw_alias (1'b1), | |
1022 | .omni_rw1c_alias (1'b0), | |
1023 | .omni_rw1s_alias (1'b0), | |
1024 | // synopsys translate_on | |
1025 | .rst (por_l_active_high), | |
1026 | .rst_val (reset_length[0]), | |
1027 | .csr_ld (w_ld), | |
1028 | .csr_data (csrbus_wr_data[48]), | |
1029 | .rw_alias (1'b1), | |
1030 | .rw1c_alias (1'b0), | |
1031 | .rw1s_alias (1'b0), | |
1032 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1033 | .hw_data (imu_scs_error_log_reg_hw_write[48]), | |
1034 | .cp (clk), | |
1035 | .q (imu_scs_error_log_reg_csrbus_read_data[48]) | |
1036 | ); | |
1037 | ||
1038 | // bit 49 | |
1039 | csr_sw csr_sw_49 | |
1040 | ( | |
1041 | // synopsys translate_off | |
1042 | .omni_ld (omni_ld), | |
1043 | .omni_data (omni_data[49]), | |
1044 | .omni_rw_alias (1'b1), | |
1045 | .omni_rw1c_alias (1'b0), | |
1046 | .omni_rw1s_alias (1'b0), | |
1047 | // synopsys translate_on | |
1048 | .rst (por_l_active_high), | |
1049 | .rst_val (reset_length[1]), | |
1050 | .csr_ld (w_ld), | |
1051 | .csr_data (csrbus_wr_data[49]), | |
1052 | .rw_alias (1'b1), | |
1053 | .rw1c_alias (1'b0), | |
1054 | .rw1s_alias (1'b0), | |
1055 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1056 | .hw_data (imu_scs_error_log_reg_hw_write[49]), | |
1057 | .cp (clk), | |
1058 | .q (imu_scs_error_log_reg_csrbus_read_data[49]) | |
1059 | ); | |
1060 | ||
1061 | // bit 50 | |
1062 | csr_sw csr_sw_50 | |
1063 | ( | |
1064 | // synopsys translate_off | |
1065 | .omni_ld (omni_ld), | |
1066 | .omni_data (omni_data[50]), | |
1067 | .omni_rw_alias (1'b1), | |
1068 | .omni_rw1c_alias (1'b0), | |
1069 | .omni_rw1s_alias (1'b0), | |
1070 | // synopsys translate_on | |
1071 | .rst (por_l_active_high), | |
1072 | .rst_val (reset_length[2]), | |
1073 | .csr_ld (w_ld), | |
1074 | .csr_data (csrbus_wr_data[50]), | |
1075 | .rw_alias (1'b1), | |
1076 | .rw1c_alias (1'b0), | |
1077 | .rw1s_alias (1'b0), | |
1078 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1079 | .hw_data (imu_scs_error_log_reg_hw_write[50]), | |
1080 | .cp (clk), | |
1081 | .q (imu_scs_error_log_reg_csrbus_read_data[50]) | |
1082 | ); | |
1083 | ||
1084 | // bit 51 | |
1085 | csr_sw csr_sw_51 | |
1086 | ( | |
1087 | // synopsys translate_off | |
1088 | .omni_ld (omni_ld), | |
1089 | .omni_data (omni_data[51]), | |
1090 | .omni_rw_alias (1'b1), | |
1091 | .omni_rw1c_alias (1'b0), | |
1092 | .omni_rw1s_alias (1'b0), | |
1093 | // synopsys translate_on | |
1094 | .rst (por_l_active_high), | |
1095 | .rst_val (reset_length[3]), | |
1096 | .csr_ld (w_ld), | |
1097 | .csr_data (csrbus_wr_data[51]), | |
1098 | .rw_alias (1'b1), | |
1099 | .rw1c_alias (1'b0), | |
1100 | .rw1s_alias (1'b0), | |
1101 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1102 | .hw_data (imu_scs_error_log_reg_hw_write[51]), | |
1103 | .cp (clk), | |
1104 | .q (imu_scs_error_log_reg_csrbus_read_data[51]) | |
1105 | ); | |
1106 | ||
1107 | // bit 52 | |
1108 | csr_sw csr_sw_52 | |
1109 | ( | |
1110 | // synopsys translate_off | |
1111 | .omni_ld (omni_ld), | |
1112 | .omni_data (omni_data[52]), | |
1113 | .omni_rw_alias (1'b1), | |
1114 | .omni_rw1c_alias (1'b0), | |
1115 | .omni_rw1s_alias (1'b0), | |
1116 | // synopsys translate_on | |
1117 | .rst (por_l_active_high), | |
1118 | .rst_val (reset_length[4]), | |
1119 | .csr_ld (w_ld), | |
1120 | .csr_data (csrbus_wr_data[52]), | |
1121 | .rw_alias (1'b1), | |
1122 | .rw1c_alias (1'b0), | |
1123 | .rw1s_alias (1'b0), | |
1124 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1125 | .hw_data (imu_scs_error_log_reg_hw_write[52]), | |
1126 | .cp (clk), | |
1127 | .q (imu_scs_error_log_reg_csrbus_read_data[52]) | |
1128 | ); | |
1129 | ||
1130 | // bit 53 | |
1131 | csr_sw csr_sw_53 | |
1132 | ( | |
1133 | // synopsys translate_off | |
1134 | .omni_ld (omni_ld), | |
1135 | .omni_data (omni_data[53]), | |
1136 | .omni_rw_alias (1'b1), | |
1137 | .omni_rw1c_alias (1'b0), | |
1138 | .omni_rw1s_alias (1'b0), | |
1139 | // synopsys translate_on | |
1140 | .rst (por_l_active_high), | |
1141 | .rst_val (reset_length[5]), | |
1142 | .csr_ld (w_ld), | |
1143 | .csr_data (csrbus_wr_data[53]), | |
1144 | .rw_alias (1'b1), | |
1145 | .rw1c_alias (1'b0), | |
1146 | .rw1s_alias (1'b0), | |
1147 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1148 | .hw_data (imu_scs_error_log_reg_hw_write[53]), | |
1149 | .cp (clk), | |
1150 | .q (imu_scs_error_log_reg_csrbus_read_data[53]) | |
1151 | ); | |
1152 | ||
1153 | // bit 54 | |
1154 | csr_sw csr_sw_54 | |
1155 | ( | |
1156 | // synopsys translate_off | |
1157 | .omni_ld (omni_ld), | |
1158 | .omni_data (omni_data[54]), | |
1159 | .omni_rw_alias (1'b1), | |
1160 | .omni_rw1c_alias (1'b0), | |
1161 | .omni_rw1s_alias (1'b0), | |
1162 | // synopsys translate_on | |
1163 | .rst (por_l_active_high), | |
1164 | .rst_val (reset_length[6]), | |
1165 | .csr_ld (w_ld), | |
1166 | .csr_data (csrbus_wr_data[54]), | |
1167 | .rw_alias (1'b1), | |
1168 | .rw1c_alias (1'b0), | |
1169 | .rw1s_alias (1'b0), | |
1170 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1171 | .hw_data (imu_scs_error_log_reg_hw_write[54]), | |
1172 | .cp (clk), | |
1173 | .q (imu_scs_error_log_reg_csrbus_read_data[54]) | |
1174 | ); | |
1175 | ||
1176 | // bit 55 | |
1177 | csr_sw csr_sw_55 | |
1178 | ( | |
1179 | // synopsys translate_off | |
1180 | .omni_ld (omni_ld), | |
1181 | .omni_data (omni_data[55]), | |
1182 | .omni_rw_alias (1'b1), | |
1183 | .omni_rw1c_alias (1'b0), | |
1184 | .omni_rw1s_alias (1'b0), | |
1185 | // synopsys translate_on | |
1186 | .rst (por_l_active_high), | |
1187 | .rst_val (reset_length[7]), | |
1188 | .csr_ld (w_ld), | |
1189 | .csr_data (csrbus_wr_data[55]), | |
1190 | .rw_alias (1'b1), | |
1191 | .rw1c_alias (1'b0), | |
1192 | .rw1s_alias (1'b0), | |
1193 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1194 | .hw_data (imu_scs_error_log_reg_hw_write[55]), | |
1195 | .cp (clk), | |
1196 | .q (imu_scs_error_log_reg_csrbus_read_data[55]) | |
1197 | ); | |
1198 | ||
1199 | // bit 56 | |
1200 | csr_sw csr_sw_56 | |
1201 | ( | |
1202 | // synopsys translate_off | |
1203 | .omni_ld (omni_ld), | |
1204 | .omni_data (omni_data[56]), | |
1205 | .omni_rw_alias (1'b1), | |
1206 | .omni_rw1c_alias (1'b0), | |
1207 | .omni_rw1s_alias (1'b0), | |
1208 | // synopsys translate_on | |
1209 | .rst (por_l_active_high), | |
1210 | .rst_val (reset_length[8]), | |
1211 | .csr_ld (w_ld), | |
1212 | .csr_data (csrbus_wr_data[56]), | |
1213 | .rw_alias (1'b1), | |
1214 | .rw1c_alias (1'b0), | |
1215 | .rw1s_alias (1'b0), | |
1216 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1217 | .hw_data (imu_scs_error_log_reg_hw_write[56]), | |
1218 | .cp (clk), | |
1219 | .q (imu_scs_error_log_reg_csrbus_read_data[56]) | |
1220 | ); | |
1221 | ||
1222 | // bit 57 | |
1223 | csr_sw csr_sw_57 | |
1224 | ( | |
1225 | // synopsys translate_off | |
1226 | .omni_ld (omni_ld), | |
1227 | .omni_data (omni_data[57]), | |
1228 | .omni_rw_alias (1'b1), | |
1229 | .omni_rw1c_alias (1'b0), | |
1230 | .omni_rw1s_alias (1'b0), | |
1231 | // synopsys translate_on | |
1232 | .rst (por_l_active_high), | |
1233 | .rst_val (reset_length[9]), | |
1234 | .csr_ld (w_ld), | |
1235 | .csr_data (csrbus_wr_data[57]), | |
1236 | .rw_alias (1'b1), | |
1237 | .rw1c_alias (1'b0), | |
1238 | .rw1s_alias (1'b0), | |
1239 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1240 | .hw_data (imu_scs_error_log_reg_hw_write[57]), | |
1241 | .cp (clk), | |
1242 | .q (imu_scs_error_log_reg_csrbus_read_data[57]) | |
1243 | ); | |
1244 | ||
1245 | // bit 58 | |
1246 | csr_sw csr_sw_58 | |
1247 | ( | |
1248 | // synopsys translate_off | |
1249 | .omni_ld (omni_ld), | |
1250 | .omni_data (omni_data[58]), | |
1251 | .omni_rw_alias (1'b1), | |
1252 | .omni_rw1c_alias (1'b0), | |
1253 | .omni_rw1s_alias (1'b0), | |
1254 | // synopsys translate_on | |
1255 | .rst (por_l_active_high), | |
1256 | .rst_val (reset_type[0]), | |
1257 | .csr_ld (w_ld), | |
1258 | .csr_data (csrbus_wr_data[58]), | |
1259 | .rw_alias (1'b1), | |
1260 | .rw1c_alias (1'b0), | |
1261 | .rw1s_alias (1'b0), | |
1262 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1263 | .hw_data (imu_scs_error_log_reg_hw_write[58]), | |
1264 | .cp (clk), | |
1265 | .q (imu_scs_error_log_reg_csrbus_read_data[58]) | |
1266 | ); | |
1267 | ||
1268 | // bit 59 | |
1269 | csr_sw csr_sw_59 | |
1270 | ( | |
1271 | // synopsys translate_off | |
1272 | .omni_ld (omni_ld), | |
1273 | .omni_data (omni_data[59]), | |
1274 | .omni_rw_alias (1'b1), | |
1275 | .omni_rw1c_alias (1'b0), | |
1276 | .omni_rw1s_alias (1'b0), | |
1277 | // synopsys translate_on | |
1278 | .rst (por_l_active_high), | |
1279 | .rst_val (reset_type[1]), | |
1280 | .csr_ld (w_ld), | |
1281 | .csr_data (csrbus_wr_data[59]), | |
1282 | .rw_alias (1'b1), | |
1283 | .rw1c_alias (1'b0), | |
1284 | .rw1s_alias (1'b0), | |
1285 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1286 | .hw_data (imu_scs_error_log_reg_hw_write[59]), | |
1287 | .cp (clk), | |
1288 | .q (imu_scs_error_log_reg_csrbus_read_data[59]) | |
1289 | ); | |
1290 | ||
1291 | // bit 60 | |
1292 | csr_sw csr_sw_60 | |
1293 | ( | |
1294 | // synopsys translate_off | |
1295 | .omni_ld (omni_ld), | |
1296 | .omni_data (omni_data[60]), | |
1297 | .omni_rw_alias (1'b1), | |
1298 | .omni_rw1c_alias (1'b0), | |
1299 | .omni_rw1s_alias (1'b0), | |
1300 | // synopsys translate_on | |
1301 | .rst (por_l_active_high), | |
1302 | .rst_val (reset_type[2]), | |
1303 | .csr_ld (w_ld), | |
1304 | .csr_data (csrbus_wr_data[60]), | |
1305 | .rw_alias (1'b1), | |
1306 | .rw1c_alias (1'b0), | |
1307 | .rw1s_alias (1'b0), | |
1308 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1309 | .hw_data (imu_scs_error_log_reg_hw_write[60]), | |
1310 | .cp (clk), | |
1311 | .q (imu_scs_error_log_reg_csrbus_read_data[60]) | |
1312 | ); | |
1313 | ||
1314 | // bit 61 | |
1315 | csr_sw csr_sw_61 | |
1316 | ( | |
1317 | // synopsys translate_off | |
1318 | .omni_ld (omni_ld), | |
1319 | .omni_data (omni_data[61]), | |
1320 | .omni_rw_alias (1'b1), | |
1321 | .omni_rw1c_alias (1'b0), | |
1322 | .omni_rw1s_alias (1'b0), | |
1323 | // synopsys translate_on | |
1324 | .rst (por_l_active_high), | |
1325 | .rst_val (reset_type[3]), | |
1326 | .csr_ld (w_ld), | |
1327 | .csr_data (csrbus_wr_data[61]), | |
1328 | .rw_alias (1'b1), | |
1329 | .rw1c_alias (1'b0), | |
1330 | .rw1s_alias (1'b0), | |
1331 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1332 | .hw_data (imu_scs_error_log_reg_hw_write[61]), | |
1333 | .cp (clk), | |
1334 | .q (imu_scs_error_log_reg_csrbus_read_data[61]) | |
1335 | ); | |
1336 | ||
1337 | // bit 62 | |
1338 | csr_sw csr_sw_62 | |
1339 | ( | |
1340 | // synopsys translate_off | |
1341 | .omni_ld (omni_ld), | |
1342 | .omni_data (omni_data[62]), | |
1343 | .omni_rw_alias (1'b1), | |
1344 | .omni_rw1c_alias (1'b0), | |
1345 | .omni_rw1s_alias (1'b0), | |
1346 | // synopsys translate_on | |
1347 | .rst (por_l_active_high), | |
1348 | .rst_val (reset_type[4]), | |
1349 | .csr_ld (w_ld), | |
1350 | .csr_data (csrbus_wr_data[62]), | |
1351 | .rw_alias (1'b1), | |
1352 | .rw1c_alias (1'b0), | |
1353 | .rw1s_alias (1'b0), | |
1354 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1355 | .hw_data (imu_scs_error_log_reg_hw_write[62]), | |
1356 | .cp (clk), | |
1357 | .q (imu_scs_error_log_reg_csrbus_read_data[62]) | |
1358 | ); | |
1359 | ||
1360 | // bit 63 | |
1361 | csr_sw csr_sw_63 | |
1362 | ( | |
1363 | // synopsys translate_off | |
1364 | .omni_ld (omni_ld), | |
1365 | .omni_data (omni_data[63]), | |
1366 | .omni_rw_alias (1'b1), | |
1367 | .omni_rw1c_alias (1'b0), | |
1368 | .omni_rw1s_alias (1'b0), | |
1369 | // synopsys translate_on | |
1370 | .rst (por_l_active_high), | |
1371 | .rst_val (reset_type[5]), | |
1372 | .csr_ld (w_ld), | |
1373 | .csr_data (csrbus_wr_data[63]), | |
1374 | .rw_alias (1'b1), | |
1375 | .rw1c_alias (1'b0), | |
1376 | .rw1s_alias (1'b0), | |
1377 | .hw_ld (imu_scs_error_log_reg_hw_ld), | |
1378 | .hw_data (imu_scs_error_log_reg_hw_write[63]), | |
1379 | .cp (clk), | |
1380 | .q (imu_scs_error_log_reg_csrbus_read_data[63]) | |
1381 | ); | |
1382 | ||
1383 | ||
1384 | endmodule // dmu_imu_ics_csr_imu_scs_error_log_reg_entry |