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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csrpipe_15.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ics_csrpipe_15 | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | reg_in, | |
40 | reg_out, | |
41 | data0, | |
42 | data1, | |
43 | data2, | |
44 | data3, | |
45 | data4, | |
46 | data5, | |
47 | data6, | |
48 | data7, | |
49 | data8, | |
50 | data9, | |
51 | data10, | |
52 | data11, | |
53 | data12, | |
54 | data13, | |
55 | data14, | |
56 | sel0, | |
57 | sel1, | |
58 | sel2, | |
59 | sel3, | |
60 | sel4, | |
61 | sel5, | |
62 | sel6, | |
63 | sel7, | |
64 | sel8, | |
65 | sel9, | |
66 | sel10, | |
67 | sel11, | |
68 | sel12, | |
69 | sel13, | |
70 | sel14, | |
71 | out | |
72 | ); | |
73 | ||
74 | //==================================================================== | |
75 | // Polarity declarations | |
76 | //==================================================================== | |
77 | input clk; // Clock signal | |
78 | input rst_l; // Reset signal | |
79 | input reg_in; // Set to constant. 0: sel* non-reg 1: sel* reg | |
80 | input reg_out; // Set to constant. 0: out non-reg 1: out registered | |
81 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data0; // Read data | |
82 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data1; // Read data | |
83 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data2; // Read data | |
84 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data3; // Read data | |
85 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data4; // Read data | |
86 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data5; // Read data | |
87 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data6; // Read data | |
88 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data7; // Read data | |
89 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data8; // Read data | |
90 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data9; // Read data | |
91 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data10; // Read data | |
92 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data11; // Read data | |
93 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data12; // Read data | |
94 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data13; // Read data | |
95 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] data14; // Read data | |
96 | input sel0; // Set to 1 if reg_in==0 | |
97 | input sel1; // Set to 1 if reg_in==0 | |
98 | input sel2; // Set to 1 if reg_in==0 | |
99 | input sel3; // Set to 1 if reg_in==0 | |
100 | input sel4; // Set to 1 if reg_in==0 | |
101 | input sel5; // Set to 1 if reg_in==0 | |
102 | input sel6; // Set to 1 if reg_in==0 | |
103 | input sel7; // Set to 1 if reg_in==0 | |
104 | input sel8; // Set to 1 if reg_in==0 | |
105 | input sel9; // Set to 1 if reg_in==0 | |
106 | input sel10; // Set to 1 if reg_in==0 | |
107 | input sel11; // Set to 1 if reg_in==0 | |
108 | input sel12; // Set to 1 if reg_in==0 | |
109 | input sel13; // Set to 1 if reg_in==0 | |
110 | input sel14; // Set to 1 if reg_in==0 | |
111 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] out; // Read data out | |
112 | ||
113 | //==================================================================== | |
114 | // Type declarations | |
115 | //==================================================================== | |
116 | wire clk; // Clock signal | |
117 | wire rst_l; // Reset signal | |
118 | wire reg_in; // Set to constant. 0: sel* non-reg 1: sel* reg | |
119 | wire reg_out; // Set to constant. 0: out non-reg 1: out registered | |
120 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data0; // Read data | |
121 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data1; // Read data | |
122 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data2; // Read data | |
123 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data3; // Read data | |
124 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data4; // Read data | |
125 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data5; // Read data | |
126 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data6; // Read data | |
127 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data7; // Read data | |
128 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data8; // Read data | |
129 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data9; // Read data | |
130 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data10; // Read data | |
131 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data11; // Read data | |
132 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data12; // Read data | |
133 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data13; // Read data | |
134 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data14; // Read data | |
135 | wire sel0; // Set to 1 if reg_in==0 | |
136 | wire sel1; // Set to 1 if reg_in==0 | |
137 | wire sel2; // Set to 1 if reg_in==0 | |
138 | wire sel3; // Set to 1 if reg_in==0 | |
139 | wire sel4; // Set to 1 if reg_in==0 | |
140 | wire sel5; // Set to 1 if reg_in==0 | |
141 | wire sel6; // Set to 1 if reg_in==0 | |
142 | wire sel7; // Set to 1 if reg_in==0 | |
143 | wire sel8; // Set to 1 if reg_in==0 | |
144 | wire sel9; // Set to 1 if reg_in==0 | |
145 | wire sel10; // Set to 1 if reg_in==0 | |
146 | wire sel11; // Set to 1 if reg_in==0 | |
147 | wire sel12; // Set to 1 if reg_in==0 | |
148 | wire sel13; // Set to 1 if reg_in==0 | |
149 | wire sel14; // Set to 1 if reg_in==0 | |
150 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] out; // Read data out | |
151 | ||
152 | //==================================================================== | |
153 | // Local variables | |
154 | //==================================================================== | |
155 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] out_p1; | |
156 | reg sel0_p1; | |
157 | reg sel1_p1; | |
158 | reg sel2_p1; | |
159 | reg sel3_p1; | |
160 | reg sel4_p1; | |
161 | reg sel5_p1; | |
162 | reg sel6_p1; | |
163 | reg sel7_p1; | |
164 | reg sel8_p1; | |
165 | reg sel9_p1; | |
166 | reg sel10_p1; | |
167 | reg sel11_p1; | |
168 | reg sel12_p1; | |
169 | reg sel13_p1; | |
170 | reg sel14_p1; | |
171 | ||
172 | //==================================================================== | |
173 | // Logic | |
174 | //==================================================================== | |
175 | //select required ? | |
176 | wire sel0_int=reg_in?sel0_p1:sel0; | |
177 | wire sel1_int=reg_in?sel1_p1:sel1; | |
178 | wire sel2_int=reg_in?sel2_p1:sel2; | |
179 | wire sel3_int=reg_in?sel3_p1:sel3; | |
180 | wire sel4_int=reg_in?sel4_p1:sel4; | |
181 | wire sel5_int=reg_in?sel5_p1:sel5; | |
182 | wire sel6_int=reg_in?sel6_p1:sel6; | |
183 | wire sel7_int=reg_in?sel7_p1:sel7; | |
184 | wire sel8_int=reg_in?sel8_p1:sel8; | |
185 | wire sel9_int=reg_in?sel9_p1:sel9; | |
186 | wire sel10_int=reg_in?sel10_p1:sel10; | |
187 | wire sel11_int=reg_in?sel11_p1:sel11; | |
188 | wire sel12_int=reg_in?sel12_p1:sel12; | |
189 | wire sel13_int=reg_in?sel13_p1:sel13; | |
190 | wire sel14_int=reg_in?sel14_p1:sel14; | |
191 | ||
192 | //generate AND/OR | |
193 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] out_d = | |
194 | {`FIRE_CSRBUS_DATA_WIDTH { sel0_int } } & data0 | | |
195 | {`FIRE_CSRBUS_DATA_WIDTH { sel1_int } } & data1 | | |
196 | {`FIRE_CSRBUS_DATA_WIDTH { sel2_int } } & data2 | | |
197 | {`FIRE_CSRBUS_DATA_WIDTH { sel3_int } } & data3 | | |
198 | {`FIRE_CSRBUS_DATA_WIDTH { sel4_int } } & data4 | | |
199 | {`FIRE_CSRBUS_DATA_WIDTH { sel5_int } } & data5 | | |
200 | {`FIRE_CSRBUS_DATA_WIDTH { sel6_int } } & data6 | | |
201 | {`FIRE_CSRBUS_DATA_WIDTH { sel7_int } } & data7 | | |
202 | {`FIRE_CSRBUS_DATA_WIDTH { sel8_int } } & data8 | | |
203 | {`FIRE_CSRBUS_DATA_WIDTH { sel9_int } } & data9 | | |
204 | {`FIRE_CSRBUS_DATA_WIDTH { sel10_int } } & data10 | | |
205 | {`FIRE_CSRBUS_DATA_WIDTH { sel11_int } } & data11 | | |
206 | {`FIRE_CSRBUS_DATA_WIDTH { sel12_int } } & data12 | | |
207 | {`FIRE_CSRBUS_DATA_WIDTH { sel13_int } } & data13 | | |
208 | {`FIRE_CSRBUS_DATA_WIDTH { sel14_int } } & data14; | |
209 | ||
210 | //reg out or combo | |
211 | assign out=reg_out?out_p1:out_d; | |
212 | ||
213 | //pipe control/data | |
214 | always @(posedge clk) | |
215 | begin | |
216 | if(~rst_l) | |
217 | begin | |
218 | sel0_p1<=1'b0; | |
219 | sel1_p1<=1'b0; | |
220 | sel2_p1<=1'b0; | |
221 | sel3_p1<=1'b0; | |
222 | sel4_p1<=1'b0; | |
223 | sel5_p1<=1'b0; | |
224 | sel6_p1<=1'b0; | |
225 | sel7_p1<=1'b0; | |
226 | sel8_p1<=1'b0; | |
227 | sel9_p1<=1'b0; | |
228 | sel10_p1<=1'b0; | |
229 | sel11_p1<=1'b0; | |
230 | sel12_p1<=1'b0; | |
231 | sel13_p1<=1'b0; | |
232 | sel14_p1<=1'b0; | |
233 | out_p1<=`FIRE_CSRBUS_DATA_WIDTH'b0; | |
234 | end | |
235 | else | |
236 | begin | |
237 | sel0_p1<=sel0; | |
238 | sel1_p1<=sel1; | |
239 | sel2_p1<=sel2; | |
240 | sel3_p1<=sel3; | |
241 | sel4_p1<=sel4; | |
242 | sel5_p1<=sel5; | |
243 | sel6_p1<=sel6; | |
244 | sel7_p1<=sel7; | |
245 | sel8_p1<=sel8; | |
246 | sel9_p1<=sel9; | |
247 | sel10_p1<=sel10; | |
248 | sel11_p1<=sel11; | |
249 | sel12_p1<=sel12; | |
250 | sel13_p1<=sel13; | |
251 | sel14_p1<=sel14; | |
252 | out_p1<=out_d; | |
253 | end | |
254 | end | |
255 | ||
256 | endmodule // dmu_imu_ics_csrpipe_15 |