[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_iss_csr_interrupt_retry_timer_entry.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_iss_csr_interrupt_retry_timer_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_imu_iss_csr_interrupt_retry_timer_entry 
	(
	// synopsys translate_off
	  omni_ld,
	  omni_data,
	// synopsys translate_on
	clk,
	rst_l,
	w_ld,
	csrbus_wr_data,
	interrupt_retry_timer_csrbus_read_data
	);

//====================================================================
//     Polarity declarations
//====================================================================
// synopsys translate_off
  input  omni_ld;  // Omni load
// vlint flag_input_port_not_connected off
  input  [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH - 1:0] omni_data;
    // Omni write data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input  clk;  // Clock signal
input  rst_l;  // Reset signal
input  w_ld;  // SW load
// vlint flag_input_port_not_connected off
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH-1:0] interrupt_retry_timer_csrbus_read_data;
    // SW read data

//====================================================================
//     Type declarations
//====================================================================
// synopsys translate_off
  wire omni_ld;  // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
  wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH - 1:0] omni_data;
    // Omni write data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk;  // Clock signal
wire rst_l;  // Reset signal
wire w_ld;  // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH-1:0] interrupt_retry_timer_csrbus_read_data;
    // SW read data

//====================================================================
//     Logic     
//====================================================================

//----- Reset values
// verilint 531 off
wire [24:0] reset_limit = 25'h0;
// verilint 531 on

//----- Active high reset wires 
wire rst_l_active_high = ~rst_l;

//====================================================
//     Instantiation of flops
//====================================================

// bit 0
csr_sw csr_sw_0
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[0]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[0]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[0])
	);

// bit 1
csr_sw csr_sw_1
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[1]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[1]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[1])
	);

// bit 2
csr_sw csr_sw_2
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[2]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[2]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[2])
	);

// bit 3
csr_sw csr_sw_3
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[3]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[3]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[3])
	);

// bit 4
csr_sw csr_sw_4
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[4]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[4]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[4])
	);

// bit 5
csr_sw csr_sw_5
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[5]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[5]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[5])
	);

// bit 6
csr_sw csr_sw_6
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[6]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[6]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[6]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[6])
	);

// bit 7
csr_sw csr_sw_7
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[7]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[7]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[7]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[7])
	);

// bit 8
csr_sw csr_sw_8
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[8]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[8]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[8]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[8])
	);

// bit 9
csr_sw csr_sw_9
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[9]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[9]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[9]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[9])
	);

// bit 10
csr_sw csr_sw_10
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[10]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[10]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[10]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[10])
	);

// bit 11
csr_sw csr_sw_11
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[11]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[11]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[11]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[11])
	);

// bit 12
csr_sw csr_sw_12
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[12]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[12]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[12]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[12])
	);

// bit 13
csr_sw csr_sw_13
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[13]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[13]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[13]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[13])
	);

// bit 14
csr_sw csr_sw_14
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[14]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[14]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[14]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[14])
	);

// bit 15
csr_sw csr_sw_15
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[15]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[15]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[15]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[15])
	);

// bit 16
csr_sw csr_sw_16
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[16]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[16]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[16]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[16])
	);

// bit 17
csr_sw csr_sw_17
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[17]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[17]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[17]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[17])
	);

// bit 18
csr_sw csr_sw_18
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[18]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[18]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[18]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[18])
	);

// bit 19
csr_sw csr_sw_19
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[19]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[19]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[19]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[19])
	);

// bit 20
csr_sw csr_sw_20
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[20]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[20]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[20]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[20])
	);

// bit 21
csr_sw csr_sw_21
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[21]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[21]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[21]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[21])
	);

// bit 22
csr_sw csr_sw_22
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[22]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[22]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[22]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[22])
	);

// bit 23
csr_sw csr_sw_23
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[23]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[23]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[23]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[23])
	);

// bit 24
csr_sw csr_sw_24
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[24]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_limit[24]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[24]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (interrupt_retry_timer_csrbus_read_data[24])
	);

assign  interrupt_retry_timer_csrbus_read_data[25] = 1'b0;  // bit 25
assign  interrupt_retry_timer_csrbus_read_data[26] = 1'b0;  // bit 26
assign  interrupt_retry_timer_csrbus_read_data[27] = 1'b0;  // bit 27
assign  interrupt_retry_timer_csrbus_read_data[28] = 1'b0;  // bit 28
assign  interrupt_retry_timer_csrbus_read_data[29] = 1'b0;  // bit 29
assign  interrupt_retry_timer_csrbus_read_data[30] = 1'b0;  // bit 30
assign  interrupt_retry_timer_csrbus_read_data[31] = 1'b0;  // bit 31
assign  interrupt_retry_timer_csrbus_read_data[32] = 1'b0;  // bit 32
assign  interrupt_retry_timer_csrbus_read_data[33] = 1'b0;  // bit 33
assign  interrupt_retry_timer_csrbus_read_data[34] = 1'b0;  // bit 34
assign  interrupt_retry_timer_csrbus_read_data[35] = 1'b0;  // bit 35
assign  interrupt_retry_timer_csrbus_read_data[36] = 1'b0;  // bit 36
assign  interrupt_retry_timer_csrbus_read_data[37] = 1'b0;  // bit 37
assign  interrupt_retry_timer_csrbus_read_data[38] = 1'b0;  // bit 38
assign  interrupt_retry_timer_csrbus_read_data[39] = 1'b0;  // bit 39
assign  interrupt_retry_timer_csrbus_read_data[40] = 1'b0;  // bit 40
assign  interrupt_retry_timer_csrbus_read_data[41] = 1'b0;  // bit 41
assign  interrupt_retry_timer_csrbus_read_data[42] = 1'b0;  // bit 42
assign  interrupt_retry_timer_csrbus_read_data[43] = 1'b0;  // bit 43
assign  interrupt_retry_timer_csrbus_read_data[44] = 1'b0;  // bit 44
assign  interrupt_retry_timer_csrbus_read_data[45] = 1'b0;  // bit 45
assign  interrupt_retry_timer_csrbus_read_data[46] = 1'b0;  // bit 46
assign  interrupt_retry_timer_csrbus_read_data[47] = 1'b0;  // bit 47
assign  interrupt_retry_timer_csrbus_read_data[48] = 1'b0;  // bit 48
assign  interrupt_retry_timer_csrbus_read_data[49] = 1'b0;  // bit 49
assign  interrupt_retry_timer_csrbus_read_data[50] = 1'b0;  // bit 50
assign  interrupt_retry_timer_csrbus_read_data[51] = 1'b0;  // bit 51
assign  interrupt_retry_timer_csrbus_read_data[52] = 1'b0;  // bit 52
assign  interrupt_retry_timer_csrbus_read_data[53] = 1'b0;  // bit 53
assign  interrupt_retry_timer_csrbus_read_data[54] = 1'b0;  // bit 54
assign  interrupt_retry_timer_csrbus_read_data[55] = 1'b0;  // bit 55
assign  interrupt_retry_timer_csrbus_read_data[56] = 1'b0;  // bit 56
assign  interrupt_retry_timer_csrbus_read_data[57] = 1'b0;  // bit 57
assign  interrupt_retry_timer_csrbus_read_data[58] = 1'b0;  // bit 58
assign  interrupt_retry_timer_csrbus_read_data[59] = 1'b0;  // bit 59
assign  interrupt_retry_timer_csrbus_read_data[60] = 1'b0;  // bit 60
assign  interrupt_retry_timer_csrbus_read_data[61] = 1'b0;  // bit 61
assign  interrupt_retry_timer_csrbus_read_data[62] = 1'b0;  // bit 62
assign  interrupt_retry_timer_csrbus_read_data[63] = 1'b0;  // bit 63

endmodule // dmu_imu_iss_csr_interrupt_retry_timer_entry
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_imu_iss_csr_interrupt_retry_timer_entry.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_imu_iss_csr_interrupt_retry_timer_entry
	36	(
	37	// synopsys translate_off
	38	omni_ld,
	39	omni_data,
	40	// synopsys translate_on
	41	clk,
	42	rst_l,
	43	w_ld,
	44	csrbus_wr_data,
	45	interrupt_retry_timer_csrbus_read_data
	46	);
	47
	48	//====================================================================
	49	// Polarity declarations
	50	//====================================================================
	51	// synopsys translate_off
	52	input omni_ld; // Omni load
	53	// vlint flag_input_port_not_connected off
	54	input [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH - 1:0] omni_data;
	55	// Omni write data
	56	// synopsys translate_on
	57	// vlint flag_input_port_not_connected on
	58	input clk; // Clock signal
	59	input rst_l; // Reset signal
	60	input w_ld; // SW load
	61	// vlint flag_input_port_not_connected off
	62	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
	63	// vlint flag_input_port_not_connected on
	64	output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH-1:0] interrupt_retry_timer_csrbus_read_data;
65	// SW read data
66
67	//====================================================================
68	// Type declarations
69	//====================================================================
70	// synopsys translate_off
71	wire omni_ld; // Omni load
72	// vlint flag_dangling_net_within_module off
73	// vlint flag_net_has_no_load off
74	wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH - 1:0] omni_data;
75	// Omni write data
76	// synopsys translate_on
77	// vlint flag_dangling_net_within_module on
78	// vlint flag_net_has_no_load on
79	wire clk; // Clock signal
80	wire rst_l; // Reset signal
81	wire w_ld; // SW load
82	// vlint flag_dangling_net_within_module off
83	// vlint flag_net_has_no_load off
84	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
85	// vlint flag_dangling_net_within_module on
86	// vlint flag_net_has_no_load on
87	wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH-1:0] interrupt_retry_timer_csrbus_read_data;
88	// SW read data
89
90	//====================================================================
91	// Logic
92	//====================================================================
93
94	//----- Reset values
95	// verilint 531 off
96	wire [24:0] reset_limit = 25'h0;
97	// verilint 531 on
98
99	//----- Active high reset wires
100	wire rst_l_active_high = ~rst_l;
101
102	//====================================================
103	// Instantiation of flops
104	//====================================================
105
106	// bit 0
107	csr_sw csr_sw_0
108	(
109	// synopsys translate_off
110	.omni_ld (omni_ld),
111	.omni_data (omni_data[0]),
112	.omni_rw_alias (1'b1),
113	.omni_rw1c_alias (1'b0),
114	.omni_rw1s_alias (1'b0),
115	// synopsys translate_on
116	.rst (rst_l_active_high),
117	.rst_val (reset_limit[0]),
118	.csr_ld (w_ld),
119	.csr_data (csrbus_wr_data[0]),
120	.rw_alias (1'b1),
121	.rw1c_alias (1'b0),
122	.rw1s_alias (1'b0),
123	.hw_ld (1'b0),
124	.hw_data (1'b0),
125	.cp (clk),
126	.q (interrupt_retry_timer_csrbus_read_data[0])
127	);
128
129	// bit 1
130	csr_sw csr_sw_1
131	(
132	// synopsys translate_off
133	.omni_ld (omni_ld),
134	.omni_data (omni_data[1]),
135	.omni_rw_alias (1'b1),
136	.omni_rw1c_alias (1'b0),
137	.omni_rw1s_alias (1'b0),
138	// synopsys translate_on
139	.rst (rst_l_active_high),
140	.rst_val (reset_limit[1]),
141	.csr_ld (w_ld),
142	.csr_data (csrbus_wr_data[1]),
143	.rw_alias (1'b1),
144	.rw1c_alias (1'b0),
145	.rw1s_alias (1'b0),
146	.hw_ld (1'b0),
147	.hw_data (1'b0),
148	.cp (clk),
149	.q (interrupt_retry_timer_csrbus_read_data[1])
150	);
151
152	// bit 2
153	csr_sw csr_sw_2
154	(
155	// synopsys translate_off
156	.omni_ld (omni_ld),
157	.omni_data (omni_data[2]),
158	.omni_rw_alias (1'b1),
159	.omni_rw1c_alias (1'b0),
160	.omni_rw1s_alias (1'b0),
161	// synopsys translate_on
162	.rst (rst_l_active_high),
163	.rst_val (reset_limit[2]),
164	.csr_ld (w_ld),
165	.csr_data (csrbus_wr_data[2]),
166	.rw_alias (1'b1),
167	.rw1c_alias (1'b0),
168	.rw1s_alias (1'b0),
169	.hw_ld (1'b0),
170	.hw_data (1'b0),
171	.cp (clk),
172	.q (interrupt_retry_timer_csrbus_read_data[2])
173	);
174
175	// bit 3
176	csr_sw csr_sw_3
177	(
178	// synopsys translate_off
179	.omni_ld (omni_ld),
180	.omni_data (omni_data[3]),
181	.omni_rw_alias (1'b1),
182	.omni_rw1c_alias (1'b0),
183	.omni_rw1s_alias (1'b0),
184	// synopsys translate_on
185	.rst (rst_l_active_high),
186	.rst_val (reset_limit[3]),
187	.csr_ld (w_ld),
188	.csr_data (csrbus_wr_data[3]),
189	.rw_alias (1'b1),
190	.rw1c_alias (1'b0),
191	.rw1s_alias (1'b0),
192	.hw_ld (1'b0),
193	.hw_data (1'b0),
194	.cp (clk),
195	.q (interrupt_retry_timer_csrbus_read_data[3])
196	);
197
198	// bit 4
199	csr_sw csr_sw_4
200	(
201	// synopsys translate_off
202	.omni_ld (omni_ld),
203	.omni_data (omni_data[4]),
204	.omni_rw_alias (1'b1),
205	.omni_rw1c_alias (1'b0),
206	.omni_rw1s_alias (1'b0),
207	// synopsys translate_on
208	.rst (rst_l_active_high),
209	.rst_val (reset_limit[4]),
210	.csr_ld (w_ld),
211	.csr_data (csrbus_wr_data[4]),
212	.rw_alias (1'b1),
213	.rw1c_alias (1'b0),
214	.rw1s_alias (1'b0),
215	.hw_ld (1'b0),
216	.hw_data (1'b0),
217	.cp (clk),
218	.q (interrupt_retry_timer_csrbus_read_data[4])
219	);
220
221	// bit 5
222	csr_sw csr_sw_5
223	(
224	// synopsys translate_off
225	.omni_ld (omni_ld),
226	.omni_data (omni_data[5]),
227	.omni_rw_alias (1'b1),
228	.omni_rw1c_alias (1'b0),
229	.omni_rw1s_alias (1'b0),
230	// synopsys translate_on
231	.rst (rst_l_active_high),
232	.rst_val (reset_limit[5]),
233	.csr_ld (w_ld),
234	.csr_data (csrbus_wr_data[5]),
235	.rw_alias (1'b1),
236	.rw1c_alias (1'b0),
237	.rw1s_alias (1'b0),
238	.hw_ld (1'b0),
239	.hw_data (1'b0),
240	.cp (clk),
241	.q (interrupt_retry_timer_csrbus_read_data[5])
242	);
243
244	// bit 6
245	csr_sw csr_sw_6
246	(
247	// synopsys translate_off
248	.omni_ld (omni_ld),
249	.omni_data (omni_data[6]),
250	.omni_rw_alias (1'b1),
251	.omni_rw1c_alias (1'b0),
252	.omni_rw1s_alias (1'b0),
253	// synopsys translate_on
254	.rst (rst_l_active_high),
255	.rst_val (reset_limit[6]),
256	.csr_ld (w_ld),
257	.csr_data (csrbus_wr_data[6]),
258	.rw_alias (1'b1),
259	.rw1c_alias (1'b0),
260	.rw1s_alias (1'b0),
261	.hw_ld (1'b0),
262	.hw_data (1'b0),
263	.cp (clk),
264	.q (interrupt_retry_timer_csrbus_read_data[6])
265	);
266
267	// bit 7
268	csr_sw csr_sw_7
269	(
270	// synopsys translate_off
271	.omni_ld (omni_ld),
272	.omni_data (omni_data[7]),
273	.omni_rw_alias (1'b1),
274	.omni_rw1c_alias (1'b0),
275	.omni_rw1s_alias (1'b0),
276	// synopsys translate_on
277	.rst (rst_l_active_high),
278	.rst_val (reset_limit[7]),
279	.csr_ld (w_ld),
280	.csr_data (csrbus_wr_data[7]),
281	.rw_alias (1'b1),
282	.rw1c_alias (1'b0),
283	.rw1s_alias (1'b0),
284	.hw_ld (1'b0),
285	.hw_data (1'b0),
286	.cp (clk),
287	.q (interrupt_retry_timer_csrbus_read_data[7])
288	);
289
290	// bit 8
291	csr_sw csr_sw_8
292	(
293	// synopsys translate_off
294	.omni_ld (omni_ld),
295	.omni_data (omni_data[8]),
296	.omni_rw_alias (1'b1),
297	.omni_rw1c_alias (1'b0),
298	.omni_rw1s_alias (1'b0),
299	// synopsys translate_on
300	.rst (rst_l_active_high),
301	.rst_val (reset_limit[8]),
302	.csr_ld (w_ld),
303	.csr_data (csrbus_wr_data[8]),
304	.rw_alias (1'b1),
305	.rw1c_alias (1'b0),
306	.rw1s_alias (1'b0),
307	.hw_ld (1'b0),
308	.hw_data (1'b0),
309	.cp (clk),
310	.q (interrupt_retry_timer_csrbus_read_data[8])
311	);
312
313	// bit 9
314	csr_sw csr_sw_9
315	(
316	// synopsys translate_off
317	.omni_ld (omni_ld),
318	.omni_data (omni_data[9]),
319	.omni_rw_alias (1'b1),
320	.omni_rw1c_alias (1'b0),
321	.omni_rw1s_alias (1'b0),
322	// synopsys translate_on
323	.rst (rst_l_active_high),
324	.rst_val (reset_limit[9]),
325	.csr_ld (w_ld),
326	.csr_data (csrbus_wr_data[9]),
327	.rw_alias (1'b1),
328	.rw1c_alias (1'b0),
329	.rw1s_alias (1'b0),
330	.hw_ld (1'b0),
331	.hw_data (1'b0),
332	.cp (clk),
333	.q (interrupt_retry_timer_csrbus_read_data[9])
334	);
335
336	// bit 10
337	csr_sw csr_sw_10
338	(
339	// synopsys translate_off
340	.omni_ld (omni_ld),
341	.omni_data (omni_data[10]),
342	.omni_rw_alias (1'b1),
343	.omni_rw1c_alias (1'b0),
344	.omni_rw1s_alias (1'b0),
345	// synopsys translate_on
346	.rst (rst_l_active_high),
347	.rst_val (reset_limit[10]),
348	.csr_ld (w_ld),
349	.csr_data (csrbus_wr_data[10]),
350	.rw_alias (1'b1),
351	.rw1c_alias (1'b0),
352	.rw1s_alias (1'b0),
353	.hw_ld (1'b0),
354	.hw_data (1'b0),
355	.cp (clk),
356	.q (interrupt_retry_timer_csrbus_read_data[10])
357	);
358
359	// bit 11
360	csr_sw csr_sw_11
361	(
362	// synopsys translate_off
363	.omni_ld (omni_ld),
364	.omni_data (omni_data[11]),
365	.omni_rw_alias (1'b1),
366	.omni_rw1c_alias (1'b0),
367	.omni_rw1s_alias (1'b0),
368	// synopsys translate_on
369	.rst (rst_l_active_high),
370	.rst_val (reset_limit[11]),
371	.csr_ld (w_ld),
372	.csr_data (csrbus_wr_data[11]),
373	.rw_alias (1'b1),
374	.rw1c_alias (1'b0),
375	.rw1s_alias (1'b0),
376	.hw_ld (1'b0),
377	.hw_data (1'b0),
378	.cp (clk),
379	.q (interrupt_retry_timer_csrbus_read_data[11])
380	);
381
382	// bit 12
383	csr_sw csr_sw_12
384	(
385	// synopsys translate_off
386	.omni_ld (omni_ld),
387	.omni_data (omni_data[12]),
388	.omni_rw_alias (1'b1),
389	.omni_rw1c_alias (1'b0),
390	.omni_rw1s_alias (1'b0),
391	// synopsys translate_on
392	.rst (rst_l_active_high),
393	.rst_val (reset_limit[12]),
394	.csr_ld (w_ld),
395	.csr_data (csrbus_wr_data[12]),
396	.rw_alias (1'b1),
397	.rw1c_alias (1'b0),
398	.rw1s_alias (1'b0),
399	.hw_ld (1'b0),
400	.hw_data (1'b0),
401	.cp (clk),
402	.q (interrupt_retry_timer_csrbus_read_data[12])
403	);
404
405	// bit 13
406	csr_sw csr_sw_13
407	(
408	// synopsys translate_off
409	.omni_ld (omni_ld),
410	.omni_data (omni_data[13]),
411	.omni_rw_alias (1'b1),
412	.omni_rw1c_alias (1'b0),
413	.omni_rw1s_alias (1'b0),
414	// synopsys translate_on
415	.rst (rst_l_active_high),
416	.rst_val (reset_limit[13]),
417	.csr_ld (w_ld),
418	.csr_data (csrbus_wr_data[13]),
419	.rw_alias (1'b1),
420	.rw1c_alias (1'b0),
421	.rw1s_alias (1'b0),
422	.hw_ld (1'b0),
423	.hw_data (1'b0),
424	.cp (clk),
425	.q (interrupt_retry_timer_csrbus_read_data[13])
426	);
427
428	// bit 14
429	csr_sw csr_sw_14
430	(
431	// synopsys translate_off
432	.omni_ld (omni_ld),
433	.omni_data (omni_data[14]),
434	.omni_rw_alias (1'b1),
435	.omni_rw1c_alias (1'b0),
436	.omni_rw1s_alias (1'b0),
437	// synopsys translate_on
438	.rst (rst_l_active_high),
439	.rst_val (reset_limit[14]),
440	.csr_ld (w_ld),
441	.csr_data (csrbus_wr_data[14]),
442	.rw_alias (1'b1),
443	.rw1c_alias (1'b0),
444	.rw1s_alias (1'b0),
445	.hw_ld (1'b0),
446	.hw_data (1'b0),
447	.cp (clk),
448	.q (interrupt_retry_timer_csrbus_read_data[14])
449	);
450
451	// bit 15
452	csr_sw csr_sw_15
453	(
454	// synopsys translate_off
455	.omni_ld (omni_ld),
456	.omni_data (omni_data[15]),
457	.omni_rw_alias (1'b1),
458	.omni_rw1c_alias (1'b0),
459	.omni_rw1s_alias (1'b0),
460	// synopsys translate_on
461	.rst (rst_l_active_high),
462	.rst_val (reset_limit[15]),
463	.csr_ld (w_ld),
464	.csr_data (csrbus_wr_data[15]),
465	.rw_alias (1'b1),
466	.rw1c_alias (1'b0),
467	.rw1s_alias (1'b0),
468	.hw_ld (1'b0),
469	.hw_data (1'b0),
470	.cp (clk),
471	.q (interrupt_retry_timer_csrbus_read_data[15])
472	);
473
474	// bit 16
475	csr_sw csr_sw_16
476	(
477	// synopsys translate_off
478	.omni_ld (omni_ld),
479	.omni_data (omni_data[16]),
480	.omni_rw_alias (1'b1),
481	.omni_rw1c_alias (1'b0),
482	.omni_rw1s_alias (1'b0),
483	// synopsys translate_on
484	.rst (rst_l_active_high),
485	.rst_val (reset_limit[16]),
486	.csr_ld (w_ld),
487	.csr_data (csrbus_wr_data[16]),
488	.rw_alias (1'b1),
489	.rw1c_alias (1'b0),
490	.rw1s_alias (1'b0),
491	.hw_ld (1'b0),
492	.hw_data (1'b0),
493	.cp (clk),
494	.q (interrupt_retry_timer_csrbus_read_data[16])
495	);
496
497	// bit 17
498	csr_sw csr_sw_17
499	(
500	// synopsys translate_off
501	.omni_ld (omni_ld),
502	.omni_data (omni_data[17]),
503	.omni_rw_alias (1'b1),
504	.omni_rw1c_alias (1'b0),
505	.omni_rw1s_alias (1'b0),
506	// synopsys translate_on
507	.rst (rst_l_active_high),
508	.rst_val (reset_limit[17]),
509	.csr_ld (w_ld),
510	.csr_data (csrbus_wr_data[17]),
511	.rw_alias (1'b1),
512	.rw1c_alias (1'b0),
513	.rw1s_alias (1'b0),
514	.hw_ld (1'b0),
515	.hw_data (1'b0),
516	.cp (clk),
517	.q (interrupt_retry_timer_csrbus_read_data[17])
518	);
519
520	// bit 18
521	csr_sw csr_sw_18
522	(
523	// synopsys translate_off
524	.omni_ld (omni_ld),
525	.omni_data (omni_data[18]),
526	.omni_rw_alias (1'b1),
527	.omni_rw1c_alias (1'b0),
528	.omni_rw1s_alias (1'b0),
529	// synopsys translate_on
530	.rst (rst_l_active_high),
531	.rst_val (reset_limit[18]),
532	.csr_ld (w_ld),
533	.csr_data (csrbus_wr_data[18]),
534	.rw_alias (1'b1),
535	.rw1c_alias (1'b0),
536	.rw1s_alias (1'b0),
537	.hw_ld (1'b0),
538	.hw_data (1'b0),
539	.cp (clk),
540	.q (interrupt_retry_timer_csrbus_read_data[18])
541	);
542
543	// bit 19
544	csr_sw csr_sw_19
545	(
546	// synopsys translate_off
547	.omni_ld (omni_ld),
548	.omni_data (omni_data[19]),
549	.omni_rw_alias (1'b1),
550	.omni_rw1c_alias (1'b0),
551	.omni_rw1s_alias (1'b0),
552	// synopsys translate_on
553	.rst (rst_l_active_high),
554	.rst_val (reset_limit[19]),
555	.csr_ld (w_ld),
556	.csr_data (csrbus_wr_data[19]),
557	.rw_alias (1'b1),
558	.rw1c_alias (1'b0),
559	.rw1s_alias (1'b0),
560	.hw_ld (1'b0),
561	.hw_data (1'b0),
562	.cp (clk),
563	.q (interrupt_retry_timer_csrbus_read_data[19])
564	);
565
566	// bit 20
567	csr_sw csr_sw_20
568	(
569	// synopsys translate_off
570	.omni_ld (omni_ld),
571	.omni_data (omni_data[20]),
572	.omni_rw_alias (1'b1),
573	.omni_rw1c_alias (1'b0),
574	.omni_rw1s_alias (1'b0),
575	// synopsys translate_on
576	.rst (rst_l_active_high),
577	.rst_val (reset_limit[20]),
578	.csr_ld (w_ld),
579	.csr_data (csrbus_wr_data[20]),
580	.rw_alias (1'b1),
581	.rw1c_alias (1'b0),
582	.rw1s_alias (1'b0),
583	.hw_ld (1'b0),
584	.hw_data (1'b0),
585	.cp (clk),
586	.q (interrupt_retry_timer_csrbus_read_data[20])
587	);
588
589	// bit 21
590	csr_sw csr_sw_21
591	(
592	// synopsys translate_off
593	.omni_ld (omni_ld),
594	.omni_data (omni_data[21]),
595	.omni_rw_alias (1'b1),
596	.omni_rw1c_alias (1'b0),
597	.omni_rw1s_alias (1'b0),
598	// synopsys translate_on
599	.rst (rst_l_active_high),
600	.rst_val (reset_limit[21]),
601	.csr_ld (w_ld),
602	.csr_data (csrbus_wr_data[21]),
603	.rw_alias (1'b1),
604	.rw1c_alias (1'b0),
605	.rw1s_alias (1'b0),
606	.hw_ld (1'b0),
607	.hw_data (1'b0),
608	.cp (clk),
609	.q (interrupt_retry_timer_csrbus_read_data[21])
610	);
611
612	// bit 22
613	csr_sw csr_sw_22
614	(
615	// synopsys translate_off
616	.omni_ld (omni_ld),
617	.omni_data (omni_data[22]),
618	.omni_rw_alias (1'b1),
619	.omni_rw1c_alias (1'b0),
620	.omni_rw1s_alias (1'b0),
621	// synopsys translate_on
622	.rst (rst_l_active_high),
623	.rst_val (reset_limit[22]),
624	.csr_ld (w_ld),
625	.csr_data (csrbus_wr_data[22]),
626	.rw_alias (1'b1),
627	.rw1c_alias (1'b0),
628	.rw1s_alias (1'b0),
629	.hw_ld (1'b0),
630	.hw_data (1'b0),
631	.cp (clk),
632	.q (interrupt_retry_timer_csrbus_read_data[22])
633	);
634
635	// bit 23
636	csr_sw csr_sw_23
637	(
638	// synopsys translate_off
639	.omni_ld (omni_ld),
640	.omni_data (omni_data[23]),
641	.omni_rw_alias (1'b1),
642	.omni_rw1c_alias (1'b0),
643	.omni_rw1s_alias (1'b0),
644	// synopsys translate_on
645	.rst (rst_l_active_high),
646	.rst_val (reset_limit[23]),
647	.csr_ld (w_ld),
648	.csr_data (csrbus_wr_data[23]),
649	.rw_alias (1'b1),
650	.rw1c_alias (1'b0),
651	.rw1s_alias (1'b0),
652	.hw_ld (1'b0),
653	.hw_data (1'b0),
654	.cp (clk),
655	.q (interrupt_retry_timer_csrbus_read_data[23])
656	);
657
658	// bit 24
659	csr_sw csr_sw_24
660	(
661	// synopsys translate_off
662	.omni_ld (omni_ld),
663	.omni_data (omni_data[24]),
664	.omni_rw_alias (1'b1),
665	.omni_rw1c_alias (1'b0),
666	.omni_rw1s_alias (1'b0),
667	// synopsys translate_on
668	.rst (rst_l_active_high),
669	.rst_val (reset_limit[24]),
670	.csr_ld (w_ld),
671	.csr_data (csrbus_wr_data[24]),
672	.rw_alias (1'b1),
673	.rw1c_alias (1'b0),
674	.rw1s_alias (1'b0),
675	.hw_ld (1'b0),
676	.hw_data (1'b0),
677	.cp (clk),
678	.q (interrupt_retry_timer_csrbus_read_data[24])
679	);
680
681	assign interrupt_retry_timer_csrbus_read_data[25] = 1'b0; // bit 25
682	assign interrupt_retry_timer_csrbus_read_data[26] = 1'b0; // bit 26
683	assign interrupt_retry_timer_csrbus_read_data[27] = 1'b0; // bit 27
684	assign interrupt_retry_timer_csrbus_read_data[28] = 1'b0; // bit 28
685	assign interrupt_retry_timer_csrbus_read_data[29] = 1'b0; // bit 29
686	assign interrupt_retry_timer_csrbus_read_data[30] = 1'b0; // bit 30
687	assign interrupt_retry_timer_csrbus_read_data[31] = 1'b0; // bit 31
688	assign interrupt_retry_timer_csrbus_read_data[32] = 1'b0; // bit 32
689	assign interrupt_retry_timer_csrbus_read_data[33] = 1'b0; // bit 33
690	assign interrupt_retry_timer_csrbus_read_data[34] = 1'b0; // bit 34
691	assign interrupt_retry_timer_csrbus_read_data[35] = 1'b0; // bit 35
692	assign interrupt_retry_timer_csrbus_read_data[36] = 1'b0; // bit 36
693	assign interrupt_retry_timer_csrbus_read_data[37] = 1'b0; // bit 37
694	assign interrupt_retry_timer_csrbus_read_data[38] = 1'b0; // bit 38
695	assign interrupt_retry_timer_csrbus_read_data[39] = 1'b0; // bit 39
696	assign interrupt_retry_timer_csrbus_read_data[40] = 1'b0; // bit 40
697	assign interrupt_retry_timer_csrbus_read_data[41] = 1'b0; // bit 41
698	assign interrupt_retry_timer_csrbus_read_data[42] = 1'b0; // bit 42
699	assign interrupt_retry_timer_csrbus_read_data[43] = 1'b0; // bit 43
700	assign interrupt_retry_timer_csrbus_read_data[44] = 1'b0; // bit 44
701	assign interrupt_retry_timer_csrbus_read_data[45] = 1'b0; // bit 45
702	assign interrupt_retry_timer_csrbus_read_data[46] = 1'b0; // bit 46
703	assign interrupt_retry_timer_csrbus_read_data[47] = 1'b0; // bit 47
704	assign interrupt_retry_timer_csrbus_read_data[48] = 1'b0; // bit 48
705	assign interrupt_retry_timer_csrbus_read_data[49] = 1'b0; // bit 49
706	assign interrupt_retry_timer_csrbus_read_data[50] = 1'b0; // bit 50
707	assign interrupt_retry_timer_csrbus_read_data[51] = 1'b0; // bit 51
708	assign interrupt_retry_timer_csrbus_read_data[52] = 1'b0; // bit 52
709	assign interrupt_retry_timer_csrbus_read_data[53] = 1'b0; // bit 53
710	assign interrupt_retry_timer_csrbus_read_data[54] = 1'b0; // bit 54
711	assign interrupt_retry_timer_csrbus_read_data[55] = 1'b0; // bit 55
712	assign interrupt_retry_timer_csrbus_read_data[56] = 1'b0; // bit 56
713	assign interrupt_retry_timer_csrbus_read_data[57] = 1'b0; // bit 57
714	assign interrupt_retry_timer_csrbus_read_data[58] = 1'b0; // bit 58
715	assign interrupt_retry_timer_csrbus_read_data[59] = 1'b0; // bit 59
716	assign interrupt_retry_timer_csrbus_read_data[60] = 1'b0; // bit 60
717	assign interrupt_retry_timer_csrbus_read_data[61] = 1'b0; // bit 61
718	assign interrupt_retry_timer_csrbus_read_data[62] = 1'b0; // bit 62
719	assign interrupt_retry_timer_csrbus_read_data[63] = 1'b0; // bit 63
720
721	endmodule // dmu_imu_iss_csr_interrupt_retry_timer_entry