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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_ors.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_ors ( | |
36 | ||
37 | // Clock and Reset | |
38 | ||
39 | clk, | |
40 | rst_l, | |
41 | ||
42 | // Inputs from SCS sub-block | |
43 | ||
44 | scs2ors_rcd, | |
45 | scs2ors_rcd_sel, | |
46 | ||
47 | // Inputs from EQS sub-block | |
48 | ||
49 | eqs2ors_eq_addr, | |
50 | eqs2ors_sel, | |
51 | ||
52 | // Outputs to LRM Block | |
53 | ||
54 | im2rm_rcd, | |
55 | im2rm_rcd_enq, | |
56 | ||
57 | // Debug Ports | |
58 | ||
59 | dbg2ors_dbg_sel_a, | |
60 | dbg2ors_dbg_sel_b, | |
61 | ors2dbg_dbg_a, | |
62 | ors2dbg_dbg_b, | |
63 | ||
64 | //Perf Counters | |
65 | ||
66 | ors2ics_perf_eq_mondos, | |
67 | ors2ics_perf_mondos, | |
68 | ors2ics_perf_msi, | |
69 | ors2ics_perf_eq_wr, | |
70 | ||
71 | ors2dbg_idle, | |
72 | csr_sun4v_en | |
73 | ||
74 | ); | |
75 | ||
76 | ||
77 | //############################################################################ | |
78 | // PORT DECLARATIONS | |
79 | //############################################################################ | |
80 | ||
81 | //------------------------------------------------------------------------ | |
82 | // Clock and Reset Signals | |
83 | //------------------------------------------------------------------------ | |
84 | input clk; | |
85 | input rst_l; | |
86 | ||
87 | ||
88 | //------------------------------------------------------------------------ | |
89 | // Inputs to Out Record Sub-block | |
90 | //------------------------------------------------------------------------ | |
91 | ||
92 | input [`FIRE_DLC_IOT_REC_WDTH-1:0] scs2ors_rcd; | |
93 | input scs2ors_rcd_sel; | |
94 | ||
95 | ||
96 | input [`FIRE_DLC_IOT_ADDR_WDTH-1:0] eqs2ors_eq_addr; | |
97 | input eqs2ors_sel; | |
98 | ||
99 | //------------------------------------------------------------------------ | |
100 | // Outputs to LRM | |
101 | //------------------------------------------------------------------------ | |
102 | ||
103 | output [`FIRE_DLC_IOT_REC_WDTH-1:0] im2rm_rcd; | |
104 | output im2rm_rcd_enq; | |
105 | ||
106 | ||
107 | //------------------------------------------------------------------------ | |
108 | // Debug Ports | |
109 | //------------------------------------------------------------------------ | |
110 | ||
111 | input [2:0] dbg2ors_dbg_sel_a; | |
112 | input [2:0] dbg2ors_dbg_sel_b; | |
113 | output [`FIRE_DEBUG_WDTH-1:0] ors2dbg_dbg_a; | |
114 | output [`FIRE_DEBUG_WDTH-1:0] ors2dbg_dbg_b; | |
115 | ||
116 | //------------------------------------------------------------------------ | |
117 | // Perf Counters | |
118 | //------------------------------------------------------------------------ | |
119 | output ors2ics_perf_eq_mondos; | |
120 | output ors2ics_perf_mondos; | |
121 | output ors2ics_perf_msi; | |
122 | output ors2ics_perf_eq_wr; | |
123 | ||
124 | //------------------------------------------------------------------------ | |
125 | // Idle Checkers | |
126 | //------------------------------------------------------------------------ | |
127 | output ors2dbg_idle; | |
128 | ||
129 | //------------------------------------------------------------------------ | |
130 | // for sun4v eq address | |
131 | //------------------------------------------------------------------------ | |
132 | input csr_sun4v_en; | |
133 | ||
134 | ||
135 | //############################################################################ | |
136 | // PARAMETERS | |
137 | //############################################################################ | |
138 | ||
139 | //############################################################################ | |
140 | // SIGNAL DECLARATIONS | |
141 | //############################################################################ | |
142 | ||
143 | ||
144 | //************************************************** | |
145 | // Wire | |
146 | //************************************************** | |
147 | ||
148 | //-------------------------- | |
149 | // Live Record Fields | |
150 | //-------------------------- | |
151 | wire [`FIRE_DLC_IOT_TYPE_WDTH-1:0] in_type; | |
152 | wire [`FIRE_DLC_IOT_ADDR_WDTH-1:0] in_address; | |
153 | ||
154 | //------------------------------------- | |
155 | // Signal to look at EQ lookup results | |
156 | //------------------------------------- | |
157 | wire scs_addr_insert; | |
158 | wire eqs_addr_insert; | |
159 | wire addr_insert; | |
160 | wire [`FIRE_DLC_IOT_ADDR_WDTH-1:0] out_address; | |
161 | wire [`FIRE_DLC_IOT_TYPE_WDTH-1:0] out_type; | |
162 | wire out_addr_mode; | |
163 | ||
164 | wire pkt_is_msi; | |
165 | wire pkt_is_mes; | |
166 | wire is_mondo_eq; | |
167 | ||
168 | //************************************************** | |
169 | // Registers that Are Not Flops | |
170 | //************************************************** | |
171 | ||
172 | //************************************************** | |
173 | // Registers that Are Flops | |
174 | //************************************************** | |
175 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_a; | |
176 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_b; | |
177 | //------------------------------------- | |
178 | // Out Record Fields | |
179 | //------------------------------------- | |
180 | reg [`FIRE_DLC_IOT_REC_WDTH-1:0] im2rm_rcd; | |
181 | reg im2rm_rcd_enq; | |
182 | ||
183 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_a; | |
184 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_b; | |
185 | ||
186 | //############################################################################ | |
187 | // ZERO IN CHECKERS | |
188 | //############################################################################ | |
189 | ||
190 | // Need to make sure that EQS and SCS think record is an MSI or Message | |
191 | //and assert together | |
192 | ||
193 | //0in assert_together -leader scs_addr_insert -follower eqs_addr_insert -active (scs_addr_insert & scs2ors_rcd_sel) | |
194 | ||
195 | //Check Address format comming from EQS | |
196 | ||
197 | //---------------------------------------- | |
198 | // 63:19 - Base address - 61:17 | |
199 | // 18:13 - EQ - 16:11 | |
200 | // 12:6 - Tail pointer for EQ - 10:4 | |
201 | // 5:2 - All zero's - 3:0 | |
202 | //---------------------------------------- | |
203 | ||
204 | //0in maximum -var eqs2ors_eq_addr[16:11] -val 35 | |
205 | ||
206 | ||
207 | ||
208 | //############################################################################ | |
209 | // COMBINATIONAL LOGIC | |
210 | //############################################################################ | |
211 | ||
212 | //-------------------------------- | |
213 | // Grab the Incomming Packet Type | |
214 | //-------------------------------- | |
215 | ||
216 | assign in_type = scs2ors_rcd[`FIRE_DLC_IOT_TYPE_MSB:`FIRE_DLC_IOT_TYPE_LSB]; | |
217 | ||
218 | ||
219 | //---------------------------------- | |
220 | //Grab the Incomming Packet Address | |
221 | //---------------------------------- | |
222 | ||
223 | assign in_address = scs2ors_rcd[`FIRE_DLC_IOT_ADDR_MSB:`FIRE_DLC_IOT_ADDR_LSB]; | |
224 | ||
225 | ||
226 | //************************************************** | |
227 | // The address portion | |
228 | //************************************************** | |
229 | //-------------------------------- | |
230 | // Check to See if the packet is | |
231 | // - MSI | |
232 | // - Message | |
233 | //-------------------------------- | |
234 | ||
235 | assign pkt_is_msi = in_type[`FIRE_DLC_IMU_OTYPE_DECODE_2] & | |
236 | !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_1] & | |
237 | !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_0]; | |
238 | ||
239 | assign pkt_is_mes = !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_2]; | |
240 | ||
241 | assign scs_addr_insert= pkt_is_msi | pkt_is_mes; | |
242 | ||
243 | //-------------------------------- | |
244 | // Check to See if the EQS thinks | |
245 | // an address should be inserted | |
246 | //-------------------------------- | |
247 | assign eqs_addr_insert = eqs2ors_sel; | |
248 | ||
249 | //-------------------------------- | |
250 | // Check to See if they both agree | |
251 | // an address should be inserted | |
252 | //-------------------------------- | |
253 | assign addr_insert = eqs_addr_insert & scs_addr_insert; | |
254 | ||
255 | //-------------------------------- | |
256 | // If the packet is | |
257 | // - MSI | |
258 | // - Message | |
259 | // | |
260 | // Check to see if address is needed | |
261 | // - if yes insert new addr | |
262 | // - if no use old address | |
263 | //-------------------------------- | |
264 | ||
265 | //BP n2 12-12-05 | |
266 | // if sun4v mode & eqs_ors_addr[61]=1 & addr_insert force addr[61] to 1 or if | |
267 | // in sun4v mode and eqs_ors_addr[61] =0, the use the in_address[61] instead of the eqs2ors_eq_addr[61] | |
268 | // thus use the pipeline value going to devtsb of bit 61 because this bit and the bus number | |
269 | // are used in the devtsb lookup | |
270 | //assign out_address = addr_insert ? eqs2ors_eq_addr : in_address; | |
271 | assign out_address[61] = ( | |
272 | (csr_sun4v_en & addr_insert & pkt_is_mes) ? {1'b1} : | |
273 | ( | |
274 | (csr_sun4v_en & addr_insert & pkt_is_msi & (eqs2ors_eq_addr[61]==1'b1)) ? | |
275 | 1'b1 : | |
276 | ( (csr_sun4v_en & addr_insert & pkt_is_msi & (eqs2ors_eq_addr[61]==1'b0)) ? | |
277 | in_address[61] : | |
278 | (addr_insert ? eqs2ors_eq_addr[61] : in_address[61]) ) | |
279 | ) ); | |
280 | ||
281 | ||
282 | assign out_address[60:0] = (csr_sun4v_en & addr_insert & pkt_is_mes) ? {24'hfff800,eqs2ors_eq_addr[36:0]} : | |
283 | ( | |
284 | addr_insert ? eqs2ors_eq_addr[60:0] : in_address[60:0] | |
285 | ); | |
286 | ||
287 | ||
288 | //************************************************** | |
289 | // The type portion | |
290 | //************************************************* | |
291 | ||
292 | //-------------------------------- | |
293 | // If the packet is | |
294 | // - MSI | |
295 | // - Message | |
296 | // | |
297 | // Use the upper bit of the EQ address | |
298 | // to check if it is bypass mode or | |
299 | // not. If set it is in by pass mode | |
300 | // and need to be set to a 1. | |
301 | // | |
302 | // This chose 64 bit over 32 bit mode | |
303 | // | |
304 | //-------------------------------- | |
305 | assign out_addr_mode = eqs2ors_eq_addr[`FIRE_DLC_IOT_ADDR_WDTH-1]; | |
306 | ||
307 | assign out_type = addr_insert ? {in_type[6],out_addr_mode,in_type[4:0]} : in_type; | |
308 | ||
309 | //----------------------------------------------------- | |
310 | // Debug Ports | |
311 | //----------------------------------------------------- | |
312 | ||
313 | always @ (dbg2ors_dbg_sel_a or im2rm_rcd_enq or im2rm_rcd or scs2ors_rcd_sel or in_type or | |
314 | pkt_is_msi or pkt_is_mes or scs_addr_insert or eqs_addr_insert or addr_insert) | |
315 | begin | |
316 | case (dbg2ors_dbg_sel_a) // synopsys infer_mux | |
317 | 3'b000: n_dbg_a = {im2rm_rcd_enq, im2rm_rcd[`FIRE_DLC_IOT_TYPE_MSB:`FIRE_DLC_IOT_TYPE_LSB]}; | |
318 | 3'b001: n_dbg_a = {scs2ors_rcd_sel, in_type[6:0]}; | |
319 | 3'b010: n_dbg_a = {3'h0, pkt_is_msi, pkt_is_mes, scs_addr_insert, eqs_addr_insert, addr_insert}; | |
320 | 3'b011: n_dbg_a = 8'h00; | |
321 | 3'b100: n_dbg_a = 8'h00; | |
322 | 3'b101: n_dbg_a = 8'h00; | |
323 | 3'b110: n_dbg_a = 8'h00; | |
324 | 3'b111: n_dbg_a = 8'h00; | |
325 | endcase | |
326 | end | |
327 | ||
328 | always @ (dbg2ors_dbg_sel_b or im2rm_rcd_enq or im2rm_rcd or scs2ors_rcd_sel or in_type or | |
329 | pkt_is_msi or pkt_is_mes or scs_addr_insert or eqs_addr_insert or addr_insert) | |
330 | begin | |
331 | case (dbg2ors_dbg_sel_b) // synopsys infer_mux | |
332 | 3'b000: n_dbg_b = {im2rm_rcd_enq, im2rm_rcd[`FIRE_DLC_IOT_TYPE_MSB:`FIRE_DLC_IOT_TYPE_LSB]}; | |
333 | 3'b001: n_dbg_b = {scs2ors_rcd_sel, in_type[6:0]}; | |
334 | 3'b010: n_dbg_b = {3'h0, pkt_is_msi, pkt_is_mes, scs_addr_insert, eqs_addr_insert, addr_insert}; | |
335 | 3'b011: n_dbg_b = 8'h00; | |
336 | 3'b100: n_dbg_b = 8'h00; | |
337 | 3'b101: n_dbg_b = 8'h00; | |
338 | 3'b110: n_dbg_b = 8'h00; | |
339 | 3'b111: n_dbg_b = 8'h00; | |
340 | endcase | |
341 | end | |
342 | ||
343 | ||
344 | always @ (posedge clk) | |
345 | begin | |
346 | if (!rst_l) begin | |
347 | dbg_a <= 8'b0; | |
348 | dbg_b <= 8'b0; | |
349 | end | |
350 | else begin | |
351 | dbg_a <= n_dbg_a; | |
352 | dbg_b <= n_dbg_b; | |
353 | end | |
354 | end | |
355 | ||
356 | ||
357 | assign ors2dbg_dbg_a = dbg_a; | |
358 | assign ors2dbg_dbg_b = dbg_b; | |
359 | ||
360 | //----------------------------------------------------- | |
361 | // Performace Counters | |
362 | //----------------------------------------------------- | |
363 | ||
364 | assign is_mondo_eq = (scs2ors_rcd[`FIRE_DLC_IOT_REQID_MSB-3:`FIRE_DLC_IOT_REQID_LSB+7] < 6'd60) & | |
365 | (scs2ors_rcd[`FIRE_DLC_IOT_REQID_MSB-3:`FIRE_DLC_IOT_REQID_LSB+7] > 6'd23); | |
366 | ||
367 | assign ors2ics_perf_eq_mondos = is_mondo_eq & out_type[`FIRE_DLC_IMU_OTYPE_DECODE_0] & scs2ors_rcd_sel; | |
368 | ||
369 | assign ors2ics_perf_mondos = out_type[`FIRE_DLC_IMU_OTYPE_DECODE_0] & scs2ors_rcd_sel; | |
370 | ||
371 | assign ors2ics_perf_msi = pkt_is_msi & scs2ors_rcd_sel; | |
372 | ||
373 | assign ors2ics_perf_eq_wr = (pkt_is_msi | pkt_is_mes) & scs2ors_rcd_sel; | |
374 | ||
375 | //------------------------------------------------------------------------ | |
376 | // Idle Checkers | |
377 | //------------------------------------------------------------------------ | |
378 | assign ors2dbg_idle = ~scs2ors_rcd_sel & ~im2rm_rcd_enq; | |
379 | ||
380 | ||
381 | //############################################################################ | |
382 | // SEQUENTIAL LOGIC | |
383 | //############################################################################ | |
384 | ||
385 | //----------------------------------------------------------------------------- | |
386 | // Delay all of the In Record infomrtaion to keep in step with the pipeline. | |
387 | // | |
388 | //----------------------------------------------------------------------------- | |
389 | always @ (posedge clk) | |
390 | if (!rst_l) | |
391 | begin // At reset reset all of them to zero. | |
392 | im2rm_rcd <= {`FIRE_DLC_IOT_REC_WDTH{1'h0}}; | |
393 | im2rm_rcd_enq <= 1'h0; | |
394 | end | |
395 | else | |
396 | begin | |
397 | im2rm_rcd <= {out_type,scs2ors_rcd[`FIRE_DLC_IOT_TC_MSB:`FIRE_DLC_IOT_DATA_LSB], out_address, scs2ors_rcd[`FIRE_DLC_IOT_DPTR_MSB:0]}; | |
398 | im2rm_rcd_enq <= scs2ors_rcd_sel; | |
399 | end | |
400 | ||
401 | ||
402 | endmodule |