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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_intx.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_intx ( | |
36 | clk, | |
37 | rst_l, | |
38 | ||
39 | pipe_select_in, | |
40 | message_code, | |
41 | ||
42 | pipe_select_out, | |
43 | rds2iss_intx_int_l, | |
44 | ||
45 | ||
46 | csrbus_valid, | |
47 | csrbus_done, | |
48 | csrbus_mapped, | |
49 | csrbus_wr_data, | |
50 | csrbus_wr, | |
51 | csrbus_read_data, | |
52 | csrbus_addr, | |
53 | csrbus_src_bus, | |
54 | csrbus_acc_vio, | |
55 | ||
56 | // Static ID Sel | |
57 | ||
58 | j2d_instance_id | |
59 | ||
60 | ||
61 | ); | |
62 | ||
63 | ||
64 | //############################################################################ | |
65 | // PORT DECLARATIONS | |
66 | //############################################################################ | |
67 | ||
68 | //------------------------------------------------------------------------ | |
69 | // Clock and Reset Signals | |
70 | //------------------------------------------------------------------------ | |
71 | input clk; | |
72 | input rst_l; | |
73 | ||
74 | ||
75 | //------------------------------------------------------------------------ | |
76 | // Input Select Signals | |
77 | //------------------------------------------------------------------------ | |
78 | input pipe_select_in; | |
79 | input [7:0] message_code; | |
80 | ||
81 | //------------------------------------------------------------------------ | |
82 | // Output Signals | |
83 | //------------------------------------------------------------------------ | |
84 | output pipe_select_out; | |
85 | output [3:0] rds2iss_intx_int_l; | |
86 | ||
87 | ||
88 | ||
89 | //------------------------------------------------------------------------ | |
90 | // PIO INTERFACE | |
91 | //------------------------------------------------------------------------ | |
92 | input csrbus_valid; | |
93 | output csrbus_done; | |
94 | output csrbus_mapped; | |
95 | ||
96 | input [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_wr_data; | |
97 | input csrbus_wr; | |
98 | ||
99 | output [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_read_data; | |
100 | ||
101 | input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] csrbus_addr; | |
102 | ||
103 | input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] csrbus_src_bus; | |
104 | output csrbus_acc_vio; | |
105 | ||
106 | ||
107 | ||
108 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; | |
109 | ||
110 | ||
111 | ||
112 | ||
113 | //############################################################################ | |
114 | // PARAMETERS | |
115 | //############################################################################ | |
116 | parameter ASSERT_A = 8'b0010_0000; | |
117 | parameter ASSERT_B = 8'b0010_0001; | |
118 | parameter ASSERT_C = 8'b0010_0010; | |
119 | parameter ASSERT_D = 8'b0010_0011; | |
120 | parameter DEASSERT_A = 8'b0010_0100; | |
121 | parameter DEASSERT_B = 8'b0010_0101; | |
122 | parameter DEASSERT_C = 8'b0010_0110; | |
123 | parameter DEASSERT_D = 8'b0010_0111; | |
124 | ||
125 | ||
126 | //############################################################################ | |
127 | // SIGNAL DECLARATIONS | |
128 | //############################################################################ | |
129 | ||
130 | ||
131 | //************************************************** | |
132 | // Wire | |
133 | //************************************************** | |
134 | //-------------------------- | |
135 | // Interrupt Read Registers | |
136 | //-------------------------- | |
137 | wire int_a_reg; | |
138 | wire int_b_reg; | |
139 | wire int_c_reg; | |
140 | wire int_d_reg; | |
141 | ||
142 | ||
143 | //-------------------------- | |
144 | // Supported Message Selects | |
145 | //-------------------------- | |
146 | ||
147 | wire assert_a_sel; | |
148 | wire deassert_a_sel; | |
149 | wire assert_b_sel; | |
150 | wire deassert_b_sel; | |
151 | wire assert_c_sel; | |
152 | wire deassert_c_sel; | |
153 | wire assert_d_sel; | |
154 | wire deassert_d_sel; | |
155 | ||
156 | //-------------------------- | |
157 | // Signals to Update Flops | |
158 | //-------------------------- | |
159 | ||
160 | wire load_int_a; | |
161 | wire load_int_b; | |
162 | wire load_int_c; | |
163 | wire load_int_d; | |
164 | ||
165 | wire load_data_int_a; | |
166 | wire load_data_int_b; | |
167 | wire load_data_int_c; | |
168 | wire load_data_int_d; | |
169 | ||
170 | ||
171 | //************************************************** | |
172 | // Registers that Are Not Flops | |
173 | //************************************************** | |
174 | ||
175 | ||
176 | //************************************************** | |
177 | // Registers that Are Flops | |
178 | //************************************************** | |
179 | reg pipe_select_out; | |
180 | ||
181 | ||
182 | ||
183 | //############################################################################ | |
184 | // ZERO IN CHECKERS | |
185 | //############################################################################ | |
186 | ||
187 | ||
188 | ||
189 | //############################################################################ | |
190 | // COMBINATIONAL LOGIC | |
191 | //############################################################################ | |
192 | ||
193 | //-------------------------------------------------------------------------- | |
194 | // Decode the Supported Message Types | |
195 | //-------------------------------------------------------------------------- | |
196 | assign assert_a_sel = (message_code == ASSERT_A); | |
197 | assign deassert_a_sel = (message_code == DEASSERT_A); | |
198 | assign assert_b_sel = (message_code == ASSERT_B); | |
199 | assign deassert_b_sel = (message_code == DEASSERT_B); | |
200 | assign assert_c_sel = (message_code == ASSERT_C); | |
201 | assign deassert_c_sel = (message_code == DEASSERT_C); | |
202 | assign assert_d_sel = (message_code == ASSERT_D); | |
203 | assign deassert_d_sel = (message_code == DEASSERT_D); | |
204 | ||
205 | ||
206 | //-------------------------------------------------------------------------- | |
207 | // Assign the Interrupt Signal for the INTX | |
208 | // | |
209 | // - Each bit is one of the ints a,b,c,d | |
210 | // - If it is a "1" inetrrupts is needed | |
211 | // - Inverted to make active low | |
212 | //-------------------------------------------------------------------------- | |
213 | ||
214 | assign rds2iss_intx_int_l = ~{int_d_reg,int_c_reg,int_b_reg,int_a_reg}; | |
215 | ||
216 | ||
217 | //-------------------------------------------------------------------------- | |
218 | // Logic to Update Value of the int_x_reg | |
219 | // | |
220 | // - Get an assert set to 1 | |
221 | // - Get a deassert set to 0 | |
222 | // | |
223 | //-------------------------------------------------------------------------- | |
224 | ||
225 | assign load_int_a = pipe_select_in & (assert_a_sel | deassert_a_sel); | |
226 | assign load_int_b = pipe_select_in & (assert_b_sel | deassert_b_sel); | |
227 | assign load_int_c = pipe_select_in & (assert_c_sel | deassert_c_sel); | |
228 | assign load_int_d = pipe_select_in & (assert_d_sel | deassert_d_sel); | |
229 | ||
230 | assign load_data_int_a = assert_a_sel; | |
231 | assign load_data_int_b = assert_b_sel; | |
232 | assign load_data_int_c = assert_c_sel; | |
233 | assign load_data_int_d = assert_d_sel; | |
234 | ||
235 | ||
236 | ||
237 | //############################################################################ | |
238 | // SEQUENTIAL LOGIC | |
239 | //############################################################################ | |
240 | ||
241 | ||
242 | //-------------------------------------------------------------------------- | |
243 | // FLOP THE OUTPUTS | |
244 | // | |
245 | //-------------------------------------------------------------------------- | |
246 | ||
247 | always @ (posedge clk) | |
248 | if (!rst_l) | |
249 | begin // At reset reset all of them to zero. | |
250 | pipe_select_out <= 1'b0; | |
251 | end | |
252 | else | |
253 | begin | |
254 | pipe_select_out <= pipe_select_in; // delay by one pipe stage | |
255 | end | |
256 | ||
257 | ||
258 | ||
259 | //############################################################################ | |
260 | // MODULE INSTANTIATIONS | |
261 | //############################################################################ | |
262 | ||
263 | ||
264 | dmu_imu_rds_intx_csr csr ( | |
265 | .clk (clk), | |
266 | .csrbus_valid (csrbus_valid), | |
267 | .csrbus_done (csrbus_done), | |
268 | .csrbus_mapped (csrbus_mapped), | |
269 | .csrbus_wr_data (csrbus_wr_data), | |
270 | .csrbus_wr (csrbus_wr), | |
271 | .csrbus_read_data (csrbus_read_data), | |
272 | .csrbus_addr (csrbus_addr), | |
273 | .rst_l (rst_l), | |
274 | ||
275 | .csrbus_src_bus (csrbus_src_bus), | |
276 | .csrbus_acc_vio (csrbus_acc_vio), | |
277 | .instance_id (j2d_instance_id), | |
278 | ||
279 | .intx_status_reg_int_a_ext_read_data (int_a_reg), | |
280 | .intx_status_reg_int_b_ext_read_data (int_b_reg), | |
281 | .intx_status_reg_int_c_ext_read_data (int_c_reg), | |
282 | .intx_status_reg_int_d_ext_read_data (int_d_reg), | |
283 | ||
284 | .int_a_int_clr_reg_clr_hw_ld (load_int_a), | |
285 | .int_a_int_clr_reg_clr_hw_write (load_data_int_a), | |
286 | .int_a_int_clr_reg_clr_hw_read (int_a_reg), | |
287 | ||
288 | .int_b_int_clr_reg_clr_hw_ld (load_int_b), | |
289 | .int_b_int_clr_reg_clr_hw_write (load_data_int_b), | |
290 | .int_b_int_clr_reg_clr_hw_read (int_b_reg), | |
291 | ||
292 | .int_c_int_clr_reg_clr_hw_ld (load_int_c), | |
293 | .int_c_int_clr_reg_clr_hw_write (load_data_int_c), | |
294 | .int_c_int_clr_reg_clr_hw_read (int_c_reg), | |
295 | ||
296 | .int_d_int_clr_reg_clr_hw_ld (load_int_d), | |
297 | .int_d_int_clr_reg_clr_hw_write (load_data_int_d), | |
298 | .int_d_int_clr_reg_clr_hw_read (int_d_reg) | |
299 | ||
300 | ||
301 | ); | |
302 | ||
303 | ||
304 | endmodule |