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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_intx_addr_decode.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_intx_addr_decode | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | daemon_csrbus_valid, | |
40 | daemon_csrbus_addr, | |
41 | csrbus_src_bus, | |
42 | daemon_csrbus_wr, | |
43 | daemon_csrbus_wr_out, | |
44 | daemon_csrbus_wr_data, | |
45 | daemon_csrbus_wr_data_out, | |
46 | daemon_csrbus_mapped, | |
47 | csrbus_acc_vio, | |
48 | daemon_transaction_in_progress, | |
49 | instance_id, | |
50 | daemon_csrbus_done, | |
51 | intx_status_reg_select, | |
52 | int_a_int_clr_reg_select_pulse, | |
53 | int_b_int_clr_reg_select_pulse, | |
54 | int_c_int_clr_reg_select_pulse, | |
55 | int_d_int_clr_reg_select_pulse | |
56 | ); | |
57 | ||
58 | //==================================================================== | |
59 | // Polarity declarations | |
60 | //==================================================================== | |
61 | input clk; // Clock signal | |
62 | input rst_l; // Reset | |
63 | input daemon_csrbus_valid; // Daemon_Valid | |
64 | input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
65 | input [1:0] csrbus_src_bus; // Source bus | |
66 | input daemon_csrbus_wr; // Read/Write signal | |
67 | output daemon_csrbus_wr_out; // Read/Write signal | |
68 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
69 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
70 | output daemon_csrbus_mapped; // mapped | |
71 | output csrbus_acc_vio; // acc_vio | |
72 | input daemon_transaction_in_progress; // daemon_transaction_in_progress | |
73 | input instance_id; // Instance ID | |
74 | output daemon_csrbus_done; // Operation is done | |
75 | output intx_status_reg_select; // select signal | |
76 | output int_a_int_clr_reg_select_pulse; // select signal | |
77 | output int_b_int_clr_reg_select_pulse; // select signal | |
78 | output int_c_int_clr_reg_select_pulse; // select signal | |
79 | output int_d_int_clr_reg_select_pulse; // select signal | |
80 | ||
81 | //==================================================================== | |
82 | // Type declarations | |
83 | //==================================================================== | |
84 | wire clk; // Clock signal | |
85 | wire rst_l; // Reset | |
86 | wire daemon_csrbus_valid; // Daemon_Valid | |
87 | wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
88 | wire [1:0] csrbus_src_bus; // Source bus | |
89 | wire daemon_csrbus_wr; // Read/Write signal | |
90 | reg daemon_csrbus_wr_out; // Read/Write signal | |
91 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
92 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
93 | wire daemon_csrbus_mapped; // mapped | |
94 | wire csrbus_acc_vio; // acc_vio | |
95 | wire daemon_transaction_in_progress; // daemon_transaction_in_progress | |
96 | wire instance_id; // Instance ID | |
97 | wire daemon_csrbus_done; // Operation is done | |
98 | reg intx_status_reg_select; // select signal | |
99 | reg int_a_int_clr_reg_select_pulse; // select signal | |
100 | reg int_b_int_clr_reg_select_pulse; // select signal | |
101 | reg int_c_int_clr_reg_select_pulse; // select signal | |
102 | reg int_d_int_clr_reg_select_pulse; // select signal | |
103 | ||
104 | ||
105 | //==================================================================== | |
106 | // Clocked valid | |
107 | //==================================================================== | |
108 | reg clocked_valid; | |
109 | reg clocked_valid_pulse; | |
110 | always @(posedge clk) | |
111 | begin | |
112 | if(~rst_l) | |
113 | begin | |
114 | clocked_valid <= 1'b0; | |
115 | clocked_valid_pulse <= 1'b0; | |
116 | end | |
117 | else | |
118 | begin | |
119 | clocked_valid <= daemon_csrbus_valid; | |
120 | clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid; | |
121 | end | |
122 | end | |
123 | ||
124 | //==================================================================== | |
125 | // Address Decode | |
126 | //==================================================================== | |
127 | reg intx_status_reg_addr_decoded; | |
128 | reg int_a_int_clr_reg_addr_decoded; | |
129 | reg int_b_int_clr_reg_addr_decoded; | |
130 | reg int_c_int_clr_reg_addr_decoded; | |
131 | reg int_d_int_clr_reg_addr_decoded; | |
132 | ||
133 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) | |
134 | begin | |
135 | if (~daemon_csrbus_valid) | |
136 | begin | |
137 | intx_status_reg_addr_decoded = 1'b0; | |
138 | int_a_int_clr_reg_addr_decoded = 1'b0; | |
139 | int_b_int_clr_reg_addr_decoded = 1'b0; | |
140 | int_c_int_clr_reg_addr_decoded = 1'b0; | |
141 | int_d_int_clr_reg_addr_decoded = 1'b0; | |
142 | end | |
143 | else | |
144 | case (instance_id) | |
145 | ||
146 | `FIRE_DLC_IMU_RDS_INTX_INSTANCE_ID_VALUE_A: | |
147 | begin | |
148 | intx_status_reg_addr_decoded = | |
149 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_HW_ADDR; | |
150 | int_a_int_clr_reg_addr_decoded = | |
151 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_HW_ADDR; | |
152 | int_b_int_clr_reg_addr_decoded = | |
153 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_HW_ADDR; | |
154 | int_c_int_clr_reg_addr_decoded = | |
155 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_HW_ADDR; | |
156 | int_d_int_clr_reg_addr_decoded = | |
157 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_HW_ADDR; | |
158 | end | |
159 | ||
160 | `FIRE_DLC_IMU_RDS_INTX_INSTANCE_ID_VALUE_B: | |
161 | begin | |
162 | intx_status_reg_addr_decoded = | |
163 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_B_INTX_STATUS_REG_HW_ADDR; | |
164 | int_a_int_clr_reg_addr_decoded = | |
165 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_A_INT_CLR_REG_HW_ADDR; | |
166 | int_b_int_clr_reg_addr_decoded = | |
167 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_B_INT_CLR_REG_HW_ADDR; | |
168 | int_c_int_clr_reg_addr_decoded = | |
169 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_C_INT_CLR_REG_HW_ADDR; | |
170 | int_d_int_clr_reg_addr_decoded = | |
171 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_D_INT_CLR_REG_HW_ADDR; | |
172 | end | |
173 | ||
174 | default: | |
175 | begin | |
176 | intx_status_reg_addr_decoded = 1'b0; | |
177 | int_a_int_clr_reg_addr_decoded = 1'b0; | |
178 | int_b_int_clr_reg_addr_decoded = 1'b0; | |
179 | int_c_int_clr_reg_addr_decoded = 1'b0; | |
180 | int_d_int_clr_reg_addr_decoded = 1'b0; | |
181 | // vlint flag_system_call off | |
182 | // synopsys translate_off | |
183 | if(daemon_csrbus_valid) | |
184 | begin // axis tbcall_region | |
185 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_intx_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_imu_rds_intx_csr is bad"); `endif | |
186 | end // end of tbcall_region | |
187 | // synopsys translate_on | |
188 | // vlint flag_system_call on | |
189 | end | |
190 | endcase | |
191 | end | |
192 | ||
193 | //==================================================================== | |
194 | // Register violations | |
195 | //==================================================================== | |
196 | //----- reg_acc_vio: intx_status_reg | |
197 | reg intx_status_reg_acc_vio; | |
198 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
199 | intx_status_reg_addr_decoded or | |
200 | daemon_transaction_in_progress) | |
201 | begin | |
202 | if (daemon_transaction_in_progress | ~intx_status_reg_addr_decoded) | |
203 | intx_status_reg_acc_vio = 1'b0; | |
204 | else | |
205 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
206 | // reads | |
207 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
208 | intx_status_reg_acc_vio = 1'b0; | |
209 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
210 | intx_status_reg_acc_vio = 1'b0; | |
211 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
212 | intx_status_reg_acc_vio = 1'b0; | |
213 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
214 | intx_status_reg_acc_vio = 1'b0; | |
215 | // writes | |
216 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
217 | intx_status_reg_acc_vio = 1'b0; | |
218 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
219 | intx_status_reg_acc_vio = 1'b0; | |
220 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
221 | intx_status_reg_acc_vio = 1'b0; | |
222 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
223 | intx_status_reg_acc_vio = 1'b0; | |
224 | ||
225 | default: | |
226 | begin | |
227 | intx_status_reg_acc_vio = 1'b0; | |
228 | begin // axis tbcall_region | |
229 | // vlint flag_system_call off | |
230 | // synopsys translate_off | |
231 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_intx_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_intx_csr_a_intx_status_reg"); `endif | |
232 | // synopsys translate_on | |
233 | // vlint flag_system_call on | |
234 | end // end of tbcall_region | |
235 | end | |
236 | endcase | |
237 | end | |
238 | //----- reg_acc_vio: int_a_int_clr_reg | |
239 | reg int_a_int_clr_reg_acc_vio; | |
240 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
241 | int_a_int_clr_reg_addr_decoded or | |
242 | daemon_transaction_in_progress) | |
243 | begin | |
244 | if (daemon_transaction_in_progress | ~int_a_int_clr_reg_addr_decoded) | |
245 | int_a_int_clr_reg_acc_vio = 1'b0; | |
246 | else | |
247 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
248 | // reads | |
249 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
250 | int_a_int_clr_reg_acc_vio = 1'b0; | |
251 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
252 | int_a_int_clr_reg_acc_vio = 1'b0; | |
253 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
254 | int_a_int_clr_reg_acc_vio = 1'b0; | |
255 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
256 | int_a_int_clr_reg_acc_vio = 1'b0; | |
257 | // writes | |
258 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
259 | int_a_int_clr_reg_acc_vio = 1'b0; | |
260 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
261 | int_a_int_clr_reg_acc_vio = 1'b0; | |
262 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
263 | int_a_int_clr_reg_acc_vio = 1'b0; | |
264 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
265 | int_a_int_clr_reg_acc_vio = 1'b0; | |
266 | ||
267 | default: | |
268 | begin | |
269 | int_a_int_clr_reg_acc_vio = 1'b0; | |
270 | begin // axis tbcall_region | |
271 | // vlint flag_system_call off | |
272 | // synopsys translate_off | |
273 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_intx_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_intx_csr_a_int_a_int_clr_reg"); `endif | |
274 | // synopsys translate_on | |
275 | // vlint flag_system_call on | |
276 | end // end of tbcall_region | |
277 | end | |
278 | endcase | |
279 | end | |
280 | //----- reg_acc_vio: int_b_int_clr_reg | |
281 | reg int_b_int_clr_reg_acc_vio; | |
282 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
283 | int_b_int_clr_reg_addr_decoded or | |
284 | daemon_transaction_in_progress) | |
285 | begin | |
286 | if (daemon_transaction_in_progress | ~int_b_int_clr_reg_addr_decoded) | |
287 | int_b_int_clr_reg_acc_vio = 1'b0; | |
288 | else | |
289 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
290 | // reads | |
291 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
292 | int_b_int_clr_reg_acc_vio = 1'b0; | |
293 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
294 | int_b_int_clr_reg_acc_vio = 1'b0; | |
295 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
296 | int_b_int_clr_reg_acc_vio = 1'b0; | |
297 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
298 | int_b_int_clr_reg_acc_vio = 1'b0; | |
299 | // writes | |
300 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
301 | int_b_int_clr_reg_acc_vio = 1'b0; | |
302 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
303 | int_b_int_clr_reg_acc_vio = 1'b0; | |
304 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
305 | int_b_int_clr_reg_acc_vio = 1'b0; | |
306 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
307 | int_b_int_clr_reg_acc_vio = 1'b0; | |
308 | ||
309 | default: | |
310 | begin | |
311 | int_b_int_clr_reg_acc_vio = 1'b0; | |
312 | begin // axis tbcall_region | |
313 | // vlint flag_system_call off | |
314 | // synopsys translate_off | |
315 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_intx_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_intx_csr_a_int_b_int_clr_reg"); `endif | |
316 | // synopsys translate_on | |
317 | // vlint flag_system_call on | |
318 | end // end of tbcall_region | |
319 | end | |
320 | endcase | |
321 | end | |
322 | //----- reg_acc_vio: int_c_int_clr_reg | |
323 | reg int_c_int_clr_reg_acc_vio; | |
324 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
325 | int_c_int_clr_reg_addr_decoded or | |
326 | daemon_transaction_in_progress) | |
327 | begin | |
328 | if (daemon_transaction_in_progress | ~int_c_int_clr_reg_addr_decoded) | |
329 | int_c_int_clr_reg_acc_vio = 1'b0; | |
330 | else | |
331 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
332 | // reads | |
333 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
334 | int_c_int_clr_reg_acc_vio = 1'b0; | |
335 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
336 | int_c_int_clr_reg_acc_vio = 1'b0; | |
337 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
338 | int_c_int_clr_reg_acc_vio = 1'b0; | |
339 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
340 | int_c_int_clr_reg_acc_vio = 1'b0; | |
341 | // writes | |
342 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
343 | int_c_int_clr_reg_acc_vio = 1'b0; | |
344 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
345 | int_c_int_clr_reg_acc_vio = 1'b0; | |
346 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
347 | int_c_int_clr_reg_acc_vio = 1'b0; | |
348 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
349 | int_c_int_clr_reg_acc_vio = 1'b0; | |
350 | ||
351 | default: | |
352 | begin | |
353 | int_c_int_clr_reg_acc_vio = 1'b0; | |
354 | begin // axis tbcall_region | |
355 | // vlint flag_system_call off | |
356 | // synopsys translate_off | |
357 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_intx_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_intx_csr_a_int_c_int_clr_reg"); `endif | |
358 | // synopsys translate_on | |
359 | // vlint flag_system_call on | |
360 | end // end of tbcall_region | |
361 | end | |
362 | endcase | |
363 | end | |
364 | //----- reg_acc_vio: int_d_int_clr_reg | |
365 | reg int_d_int_clr_reg_acc_vio; | |
366 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
367 | int_d_int_clr_reg_addr_decoded or | |
368 | daemon_transaction_in_progress) | |
369 | begin | |
370 | if (daemon_transaction_in_progress | ~int_d_int_clr_reg_addr_decoded) | |
371 | int_d_int_clr_reg_acc_vio = 1'b0; | |
372 | else | |
373 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
374 | // reads | |
375 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
376 | int_d_int_clr_reg_acc_vio = 1'b0; | |
377 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
378 | int_d_int_clr_reg_acc_vio = 1'b0; | |
379 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
380 | int_d_int_clr_reg_acc_vio = 1'b0; | |
381 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
382 | int_d_int_clr_reg_acc_vio = 1'b0; | |
383 | // writes | |
384 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
385 | int_d_int_clr_reg_acc_vio = 1'b0; | |
386 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
387 | int_d_int_clr_reg_acc_vio = 1'b0; | |
388 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
389 | int_d_int_clr_reg_acc_vio = 1'b0; | |
390 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
391 | int_d_int_clr_reg_acc_vio = 1'b0; | |
392 | ||
393 | default: | |
394 | begin | |
395 | int_d_int_clr_reg_acc_vio = 1'b0; | |
396 | begin // axis tbcall_region | |
397 | // vlint flag_system_call off | |
398 | // synopsys translate_off | |
399 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_intx_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_intx_csr_a_int_d_int_clr_reg"); `endif | |
400 | // synopsys translate_on | |
401 | // vlint flag_system_call on | |
402 | end // end of tbcall_region | |
403 | end | |
404 | endcase | |
405 | end | |
406 | ||
407 | //==================================================================== | |
408 | // Status: daemon_csrbus_mapped / csrbus_acc_vio | |
409 | //==================================================================== | |
410 | //----- OUTPUT: daemon_csrbus_mapped | |
411 | assign daemon_csrbus_mapped = clocked_valid_pulse & | |
412 | ( | |
413 | intx_status_reg_addr_decoded | | |
414 | int_a_int_clr_reg_addr_decoded | | |
415 | int_b_int_clr_reg_addr_decoded | | |
416 | int_c_int_clr_reg_addr_decoded | | |
417 | int_d_int_clr_reg_addr_decoded | |
418 | ); | |
419 | ||
420 | ||
421 | // daemon_csrbus_mapped gets asserted after fixed number of cycles | |
422 | // after daemon_csrbus_valid become high | |
423 | /* 0in assert_together -name mapped_after_valid | |
424 | -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1)) | |
425 | -follower $0in_rising_edge(daemon_csrbus_mapped) | |
426 | -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid") | |
427 | -module dmu_imu_rds_intx_addr_decode | |
428 | -clock clk | |
429 | -active $0in_rising_edge(daemon_csrbus_mapped) | |
430 | */ | |
431 | ||
432 | // daemon_csrbus_mapped is a pulse | |
433 | /* 0in assert_timer -name daemon_csrbus_mapped_pulse | |
434 | -var daemon_csrbus_mapped -max 1 | |
435 | -message "daemon_csrbus_mapped pulse length is not 1" | |
436 | -module dmu_imu_rds_intx_addr_decode | |
437 | -clock clk | |
438 | */ | |
439 | //----- OUTPUT: csrbus_acc_vio | |
440 | assign csrbus_acc_vio = clocked_valid_pulse & | |
441 | intx_status_reg_acc_vio | | |
442 | int_a_int_clr_reg_acc_vio | | |
443 | int_b_int_clr_reg_acc_vio | | |
444 | int_c_int_clr_reg_acc_vio | | |
445 | int_d_int_clr_reg_acc_vio; | |
446 | ||
447 | //==================================================================== | |
448 | // Select | |
449 | //==================================================================== | |
450 | always @(posedge clk) | |
451 | begin | |
452 | if(~rst_l) | |
453 | begin | |
454 | intx_status_reg_select <= 1'b0; | |
455 | int_a_int_clr_reg_select_pulse <= 1'b0; | |
456 | int_b_int_clr_reg_select_pulse <= 1'b0; | |
457 | int_c_int_clr_reg_select_pulse <= 1'b0; | |
458 | int_d_int_clr_reg_select_pulse <= 1'b0; | |
459 | end | |
460 | else | |
461 | begin | |
462 | intx_status_reg_select <= | |
463 | ~intx_status_reg_acc_vio & | |
464 | intx_status_reg_addr_decoded; | |
465 | ||
466 | int_a_int_clr_reg_select_pulse <= | |
467 | ~int_a_int_clr_reg_acc_vio & | |
468 | clocked_valid_pulse & | |
469 | int_a_int_clr_reg_addr_decoded; | |
470 | ||
471 | int_b_int_clr_reg_select_pulse <= | |
472 | ~int_b_int_clr_reg_acc_vio & | |
473 | clocked_valid_pulse & | |
474 | int_b_int_clr_reg_addr_decoded; | |
475 | ||
476 | int_c_int_clr_reg_select_pulse <= | |
477 | ~int_c_int_clr_reg_acc_vio & | |
478 | clocked_valid_pulse & | |
479 | int_c_int_clr_reg_addr_decoded; | |
480 | ||
481 | int_d_int_clr_reg_select_pulse <= | |
482 | ~int_d_int_clr_reg_acc_vio & | |
483 | clocked_valid_pulse & | |
484 | int_d_int_clr_reg_addr_decoded; | |
485 | ||
486 | end | |
487 | end | |
488 | ||
489 | //==================================================================== | |
490 | // daemon_csrbus_wr / daemon_csrbus_wr_data | |
491 | //==================================================================== | |
492 | always @(posedge clk) | |
493 | begin | |
494 | if(~rst_l) | |
495 | begin | |
496 | daemon_csrbus_wr_out <= 1'b0; | |
497 | daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0; | |
498 | end | |
499 | else | |
500 | begin | |
501 | daemon_csrbus_wr_out <= daemon_csrbus_wr; | |
502 | daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data; | |
503 | end | |
504 | end | |
505 | ||
506 | //==================================================================== | |
507 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming | |
508 | //==================================================================== | |
509 | ||
510 | //==================================================================== | |
511 | // OUTPUT: daemon_csrbus_done (pipelining) | |
512 | //==================================================================== | |
513 | //----- DONE for internal/extern registers | |
514 | reg stage_1_daemon_csrbus_done_internal_0; | |
515 | reg stage_2_daemon_csrbus_done_internal_0; | |
516 | ||
517 | always @(posedge clk) | |
518 | begin | |
519 | if(~rst_l) | |
520 | begin | |
521 | stage_1_daemon_csrbus_done_internal_0 <= 1'b0; | |
522 | end | |
523 | else | |
524 | begin | |
525 | stage_1_daemon_csrbus_done_internal_0 <= | |
526 | int_a_int_clr_reg_select_pulse | | |
527 | int_b_int_clr_reg_select_pulse | | |
528 | int_c_int_clr_reg_select_pulse | | |
529 | int_d_int_clr_reg_select_pulse | | |
530 | intx_status_reg_select & clocked_valid_pulse; | |
531 | end | |
532 | if(~rst_l) | |
533 | begin | |
534 | stage_2_daemon_csrbus_done_internal_0 <= 1'b0; | |
535 | end | |
536 | else | |
537 | begin | |
538 | stage_2_daemon_csrbus_done_internal_0 <= | |
539 | stage_1_daemon_csrbus_done_internal_0; | |
540 | end | |
541 | end | |
542 | ||
543 | //----- OUTPUT: daemon_csrbus_done | |
544 | assign daemon_csrbus_done = daemon_csrbus_valid & | |
545 | ( | |
546 | stage_2_daemon_csrbus_done_internal_0 | |
547 | ); | |
548 | ||
549 | // daemon_csrbus_done gets asserted only when csrbus_valid is high | |
550 | /* 0in assert -name daemon_csrbus_done_high | |
551 | -var daemon_csrbus_valid -active daemon_csrbus_done | |
552 | -message "csrbus_done got asserted while csrbus_valid is low" | |
553 | -module dmu_imu_rds_intx_addr_decode | |
554 | -clock clk | |
555 | */ | |
556 | ||
557 | // daemon_csrbus_done is a pulse | |
558 | /* 0in assert_timer -name daemon_csrbus_done_pulse | |
559 | -var daemon_csrbus_done -max 1 | |
560 | -message "csrbus_done pulse length is not 1" | |
561 | -module dmu_imu_rds_intx_addr_decode | |
562 | -clock clk | |
563 | */ | |
564 | ||
565 | endmodule // dmu_imu_rds_intx_addr_decode |