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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_intx_csr_int_c_int_clr_reg_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_intx_csr_int_c_int_clr_reg_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | int_c_int_clr_reg_csrbus_read_data, | |
46 | int_c_int_clr_reg_clr_hw_ld, | |
47 | int_c_int_clr_reg_clr_hw_write | |
48 | ); | |
49 | ||
50 | //==================================================================== | |
51 | // Polarity declarations | |
52 | //==================================================================== | |
53 | // synopsys translate_off | |
54 | input omni_ld; // Omni load | |
55 | // vlint flag_input_port_not_connected off | |
56 | input [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH - 1:0] omni_data; | |
57 | // Omni write data | |
58 | // synopsys translate_on | |
59 | // vlint flag_input_port_not_connected on | |
60 | input clk; // Clock signal | |
61 | input rst_l; // Reset signal | |
62 | input w_ld; // SW load | |
63 | // vlint flag_input_port_not_connected off | |
64 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
65 | // vlint flag_input_port_not_connected on | |
66 | output [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] int_c_int_clr_reg_csrbus_read_data; | |
67 | // SW read data | |
68 | input int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for | |
69 | // int_c_int_clr_reg_clr. When set, <hw | |
70 | // write signal> will be loaded into | |
71 | // int_c_int_clr_reg. | |
72 | input int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of | |
73 | // int_c_int_clr_reg_clr. | |
74 | ||
75 | //==================================================================== | |
76 | // Type declarations | |
77 | //==================================================================== | |
78 | // synopsys translate_off | |
79 | wire omni_ld; // Omni load | |
80 | // vlint flag_dangling_net_within_module off | |
81 | // vlint flag_net_has_no_load off | |
82 | wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH - 1:0] omni_data; | |
83 | // Omni write data | |
84 | // synopsys translate_on | |
85 | // vlint flag_dangling_net_within_module on | |
86 | // vlint flag_net_has_no_load on | |
87 | wire clk; // Clock signal | |
88 | wire rst_l; // Reset signal | |
89 | wire w_ld; // SW load | |
90 | // vlint flag_dangling_net_within_module off | |
91 | // vlint flag_net_has_no_load off | |
92 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
93 | // vlint flag_dangling_net_within_module on | |
94 | // vlint flag_net_has_no_load on | |
95 | wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] int_c_int_clr_reg_csrbus_read_data; | |
96 | // SW read data | |
97 | wire int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for | |
98 | // int_c_int_clr_reg_clr. When set, <hw write | |
99 | // signal> will be loaded into | |
100 | // int_c_int_clr_reg. | |
101 | wire int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of | |
102 | // int_c_int_clr_reg_clr. | |
103 | ||
104 | //==================================================================== | |
105 | // Logic | |
106 | //==================================================================== | |
107 | ||
108 | //----- Reset values | |
109 | // verilint 531 off | |
110 | wire [0:0] reset_clr = 1'h0; | |
111 | // verilint 531 on | |
112 | ||
113 | //----- Active high reset wires | |
114 | wire rst_l_active_high = ~rst_l; | |
115 | ||
116 | //==================================================== | |
117 | // Instantiation of flops | |
118 | //==================================================== | |
119 | ||
120 | // bit 0 | |
121 | csr_sw csr_sw_0 | |
122 | ( | |
123 | // synopsys translate_off | |
124 | .omni_ld (omni_ld), | |
125 | .omni_data (omni_data[0]), | |
126 | .omni_rw_alias (1'b0), | |
127 | .omni_rw1c_alias (1'b1), | |
128 | .omni_rw1s_alias (1'b0), | |
129 | // synopsys translate_on | |
130 | .rst (rst_l_active_high), | |
131 | .rst_val (reset_clr[0]), | |
132 | .csr_ld (w_ld), | |
133 | .csr_data (csrbus_wr_data[0]), | |
134 | .rw_alias (1'b0), | |
135 | .rw1c_alias (1'b1), | |
136 | .rw1s_alias (1'b0), | |
137 | .hw_ld (int_c_int_clr_reg_clr_hw_ld), | |
138 | .hw_data (int_c_int_clr_reg_clr_hw_write), | |
139 | .cp (clk), | |
140 | .q (int_c_int_clr_reg_csrbus_read_data[0]) | |
141 | ); | |
142 | ||
143 | assign int_c_int_clr_reg_csrbus_read_data[1] = 1'b0; // bit 1 | |
144 | assign int_c_int_clr_reg_csrbus_read_data[2] = 1'b0; // bit 2 | |
145 | assign int_c_int_clr_reg_csrbus_read_data[3] = 1'b0; // bit 3 | |
146 | assign int_c_int_clr_reg_csrbus_read_data[4] = 1'b0; // bit 4 | |
147 | assign int_c_int_clr_reg_csrbus_read_data[5] = 1'b0; // bit 5 | |
148 | assign int_c_int_clr_reg_csrbus_read_data[6] = 1'b0; // bit 6 | |
149 | assign int_c_int_clr_reg_csrbus_read_data[7] = 1'b0; // bit 7 | |
150 | assign int_c_int_clr_reg_csrbus_read_data[8] = 1'b0; // bit 8 | |
151 | assign int_c_int_clr_reg_csrbus_read_data[9] = 1'b0; // bit 9 | |
152 | assign int_c_int_clr_reg_csrbus_read_data[10] = 1'b0; // bit 10 | |
153 | assign int_c_int_clr_reg_csrbus_read_data[11] = 1'b0; // bit 11 | |
154 | assign int_c_int_clr_reg_csrbus_read_data[12] = 1'b0; // bit 12 | |
155 | assign int_c_int_clr_reg_csrbus_read_data[13] = 1'b0; // bit 13 | |
156 | assign int_c_int_clr_reg_csrbus_read_data[14] = 1'b0; // bit 14 | |
157 | assign int_c_int_clr_reg_csrbus_read_data[15] = 1'b0; // bit 15 | |
158 | assign int_c_int_clr_reg_csrbus_read_data[16] = 1'b0; // bit 16 | |
159 | assign int_c_int_clr_reg_csrbus_read_data[17] = 1'b0; // bit 17 | |
160 | assign int_c_int_clr_reg_csrbus_read_data[18] = 1'b0; // bit 18 | |
161 | assign int_c_int_clr_reg_csrbus_read_data[19] = 1'b0; // bit 19 | |
162 | assign int_c_int_clr_reg_csrbus_read_data[20] = 1'b0; // bit 20 | |
163 | assign int_c_int_clr_reg_csrbus_read_data[21] = 1'b0; // bit 21 | |
164 | assign int_c_int_clr_reg_csrbus_read_data[22] = 1'b0; // bit 22 | |
165 | assign int_c_int_clr_reg_csrbus_read_data[23] = 1'b0; // bit 23 | |
166 | assign int_c_int_clr_reg_csrbus_read_data[24] = 1'b0; // bit 24 | |
167 | assign int_c_int_clr_reg_csrbus_read_data[25] = 1'b0; // bit 25 | |
168 | assign int_c_int_clr_reg_csrbus_read_data[26] = 1'b0; // bit 26 | |
169 | assign int_c_int_clr_reg_csrbus_read_data[27] = 1'b0; // bit 27 | |
170 | assign int_c_int_clr_reg_csrbus_read_data[28] = 1'b0; // bit 28 | |
171 | assign int_c_int_clr_reg_csrbus_read_data[29] = 1'b0; // bit 29 | |
172 | assign int_c_int_clr_reg_csrbus_read_data[30] = 1'b0; // bit 30 | |
173 | assign int_c_int_clr_reg_csrbus_read_data[31] = 1'b0; // bit 31 | |
174 | assign int_c_int_clr_reg_csrbus_read_data[32] = 1'b0; // bit 32 | |
175 | assign int_c_int_clr_reg_csrbus_read_data[33] = 1'b0; // bit 33 | |
176 | assign int_c_int_clr_reg_csrbus_read_data[34] = 1'b0; // bit 34 | |
177 | assign int_c_int_clr_reg_csrbus_read_data[35] = 1'b0; // bit 35 | |
178 | assign int_c_int_clr_reg_csrbus_read_data[36] = 1'b0; // bit 36 | |
179 | assign int_c_int_clr_reg_csrbus_read_data[37] = 1'b0; // bit 37 | |
180 | assign int_c_int_clr_reg_csrbus_read_data[38] = 1'b0; // bit 38 | |
181 | assign int_c_int_clr_reg_csrbus_read_data[39] = 1'b0; // bit 39 | |
182 | assign int_c_int_clr_reg_csrbus_read_data[40] = 1'b0; // bit 40 | |
183 | assign int_c_int_clr_reg_csrbus_read_data[41] = 1'b0; // bit 41 | |
184 | assign int_c_int_clr_reg_csrbus_read_data[42] = 1'b0; // bit 42 | |
185 | assign int_c_int_clr_reg_csrbus_read_data[43] = 1'b0; // bit 43 | |
186 | assign int_c_int_clr_reg_csrbus_read_data[44] = 1'b0; // bit 44 | |
187 | assign int_c_int_clr_reg_csrbus_read_data[45] = 1'b0; // bit 45 | |
188 | assign int_c_int_clr_reg_csrbus_read_data[46] = 1'b0; // bit 46 | |
189 | assign int_c_int_clr_reg_csrbus_read_data[47] = 1'b0; // bit 47 | |
190 | assign int_c_int_clr_reg_csrbus_read_data[48] = 1'b0; // bit 48 | |
191 | assign int_c_int_clr_reg_csrbus_read_data[49] = 1'b0; // bit 49 | |
192 | assign int_c_int_clr_reg_csrbus_read_data[50] = 1'b0; // bit 50 | |
193 | assign int_c_int_clr_reg_csrbus_read_data[51] = 1'b0; // bit 51 | |
194 | assign int_c_int_clr_reg_csrbus_read_data[52] = 1'b0; // bit 52 | |
195 | assign int_c_int_clr_reg_csrbus_read_data[53] = 1'b0; // bit 53 | |
196 | assign int_c_int_clr_reg_csrbus_read_data[54] = 1'b0; // bit 54 | |
197 | assign int_c_int_clr_reg_csrbus_read_data[55] = 1'b0; // bit 55 | |
198 | assign int_c_int_clr_reg_csrbus_read_data[56] = 1'b0; // bit 56 | |
199 | assign int_c_int_clr_reg_csrbus_read_data[57] = 1'b0; // bit 57 | |
200 | assign int_c_int_clr_reg_csrbus_read_data[58] = 1'b0; // bit 58 | |
201 | assign int_c_int_clr_reg_csrbus_read_data[59] = 1'b0; // bit 59 | |
202 | assign int_c_int_clr_reg_csrbus_read_data[60] = 1'b0; // bit 60 | |
203 | assign int_c_int_clr_reg_csrbus_read_data[61] = 1'b0; // bit 61 | |
204 | assign int_c_int_clr_reg_csrbus_read_data[62] = 1'b0; // bit 62 | |
205 | assign int_c_int_clr_reg_csrbus_read_data[63] = 1'b0; // bit 63 | |
206 | ||
207 | endmodule // dmu_imu_rds_intx_csr_int_c_int_clr_reg_entry |