[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_rds_intx_default_grp.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_rds_intx_default_grp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_imu_rds_intx_default_grp 
	(
	clk,
	intx_status_reg_select,
	intx_status_reg_ext_read_data,
	int_a_int_clr_reg_clr_hw_ld,
	int_a_int_clr_reg_clr_hw_write,
	int_a_int_clr_reg_clr_hw_read,
	int_a_int_clr_reg_select_pulse,
	int_b_int_clr_reg_clr_hw_ld,
	int_b_int_clr_reg_clr_hw_write,
	int_b_int_clr_reg_clr_hw_read,
	int_b_int_clr_reg_select_pulse,
	int_c_int_clr_reg_clr_hw_ld,
	int_c_int_clr_reg_clr_hw_write,
	int_c_int_clr_reg_clr_hw_read,
	int_c_int_clr_reg_select_pulse,
	int_d_int_clr_reg_clr_hw_ld,
	int_d_int_clr_reg_clr_hw_write,
	int_d_int_clr_reg_clr_hw_read,
	int_d_int_clr_reg_select_pulse,
	rst_l,
	daemon_csrbus_wr_in,
	daemon_csrbus_wr_data_in,
	read_data_0_out
	);

//====================================================
//     Polarity declarations
//====================================================
input  clk;  // Clock signal
input  intx_status_reg_select;  // select
input  [`FIRE_CSRBUS_DATA_WIDTH - 1:0] intx_status_reg_ext_read_data;
    // Read Data
input  int_a_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                     // int_a_int_clr_reg_clr. When set, <hw
                                     // write signal>  will be loaded into
                                     // int_a_int_clr_reg.
input  int_a_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                        // int_a_int_clr_reg_clr.
output int_a_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                       // of int_a_int_clr_reg_clr.
input  int_a_int_clr_reg_select_pulse;  // select
input  int_b_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                     // int_b_int_clr_reg_clr. When set, <hw
                                     // write signal>  will be loaded into
                                     // int_b_int_clr_reg.
input  int_b_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                        // int_b_int_clr_reg_clr.
output int_b_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                       // of int_b_int_clr_reg_clr.
input  int_b_int_clr_reg_select_pulse;  // select
input  int_c_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                     // int_c_int_clr_reg_clr. When set, <hw
                                     // write signal>  will be loaded into
                                     // int_c_int_clr_reg.
input  int_c_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                        // int_c_int_clr_reg_clr.
output int_c_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                       // of int_c_int_clr_reg_clr.
input  int_c_int_clr_reg_select_pulse;  // select
input  int_d_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                     // int_d_int_clr_reg_clr. When set, <hw
                                     // write signal>  will be loaded into
                                     // int_d_int_clr_reg.
input  int_d_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                        // int_d_int_clr_reg_clr.
output int_d_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                       // of int_d_int_clr_reg_clr.
input  int_d_int_clr_reg_select_pulse;  // select
input  rst_l;  // HW reset
input  daemon_csrbus_wr_in;  // csrbus_wr
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in;  // SW write data
output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out;  // Read Data

//====================================================
//     Type declarations
//====================================================
wire clk;  // Clock signal
wire intx_status_reg_select;  // select
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] intx_status_reg_ext_read_data;
    // Read Data
wire int_a_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                   // int_a_int_clr_reg_clr. When set, <hw write
                                   // signal>  will be loaded into
                                   // int_a_int_clr_reg.
wire int_a_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                      // int_a_int_clr_reg_clr.
wire int_a_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                     // of int_a_int_clr_reg_clr.
wire int_a_int_clr_reg_select_pulse;  // select
wire int_b_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                   // int_b_int_clr_reg_clr. When set, <hw write
                                   // signal>  will be loaded into
                                   // int_b_int_clr_reg.
wire int_b_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                      // int_b_int_clr_reg_clr.
wire int_b_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                     // of int_b_int_clr_reg_clr.
wire int_b_int_clr_reg_select_pulse;  // select
wire int_c_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                   // int_c_int_clr_reg_clr. When set, <hw write
                                   // signal>  will be loaded into
                                   // int_c_int_clr_reg.
wire int_c_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                      // int_c_int_clr_reg_clr.
wire int_c_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                     // of int_c_int_clr_reg_clr.
wire int_c_int_clr_reg_select_pulse;  // select
wire int_d_int_clr_reg_clr_hw_ld;  // Hardware load enable for
                                   // int_d_int_clr_reg_clr. When set, <hw write
                                   // signal>  will be loaded into
                                   // int_d_int_clr_reg.
wire int_d_int_clr_reg_clr_hw_write;  // data bus for hw loading of
                                      // int_d_int_clr_reg_clr.
wire int_d_int_clr_reg_clr_hw_read;  // This signal provides the current value
                                     // of int_d_int_clr_reg_clr.
wire int_d_int_clr_reg_select_pulse;  // select
wire rst_l;  // HW reset
wire daemon_csrbus_wr_in;  // csrbus_wr
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in;  // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out;  // Read Data


//====================================================
//   Local signals
//====================================================
//----- For CSR register: int_a_int_clr_reg
wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH-1:0] int_a_int_clr_reg_csrbus_read_data;
    // Entry Based Read Data

//----- For CSR register: int_b_int_clr_reg
wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WIDTH-1:0] int_b_int_clr_reg_csrbus_read_data;
    // Entry Based Read Data

//----- For CSR register: int_c_int_clr_reg
wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] int_c_int_clr_reg_csrbus_read_data;
    // Entry Based Read Data

//----- For CSR register: int_d_int_clr_reg
wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WIDTH-1:0] int_d_int_clr_reg_csrbus_read_data;
    // Entry Based Read Data

//====================================================
//     Assignments only (first stage)
//====================================================
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in;
wire daemon_csrbus_wr      = daemon_csrbus_wr_in;

//====================================================
//      Automatic hw_ld / hw_write
//====================================================

//====================================================
//      Extern select
//====================================================

//=====================================================
//      OUTPUT: read_data_out
//=====================================================
dmu_imu_rds_intx_csrpipe_5 dmu_imu_rds_intx_csrpipe_5_inst_1
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.reg_in	(1'b1),
	.reg_out	(1'b1),
	.data0	(intx_status_reg_ext_read_data),
	.sel0	(intx_status_reg_select),
	.data1	(int_a_int_clr_reg_csrbus_read_data),
	.sel1	(int_a_int_clr_reg_select_pulse),
	.data2	(int_b_int_clr_reg_csrbus_read_data),
	.sel2	(int_b_int_clr_reg_select_pulse),
	.data3	(int_c_int_clr_reg_csrbus_read_data),
	.sel3	(int_c_int_clr_reg_select_pulse),
	.data4	(int_d_int_clr_reg_csrbus_read_data),
	.sel4	(int_d_int_clr_reg_select_pulse),
	.out	(read_data_0_out)
	);


//====================================================
//     Instantiation of registers
//====================================================

wire int_a_int_clr_reg_w_ld =int_a_int_clr_reg_select_pulse & daemon_csrbus_wr;

dmu_imu_rds_intx_csr_int_a_int_clr_reg int_a_int_clr_reg
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.int_a_int_clr_reg_w_ld	(int_a_int_clr_reg_w_ld),
	.csrbus_wr_data	(daemon_csrbus_wr_data),
	.int_a_int_clr_reg_csrbus_read_data	(int_a_int_clr_reg_csrbus_read_data),
	.int_a_int_clr_reg_clr_hw_ld	(int_a_int_clr_reg_clr_hw_ld),
	.int_a_int_clr_reg_clr_hw_write	(int_a_int_clr_reg_clr_hw_write),
	.int_a_int_clr_reg_clr_hw_read	(int_a_int_clr_reg_clr_hw_read)
	);

wire int_b_int_clr_reg_w_ld =int_b_int_clr_reg_select_pulse & daemon_csrbus_wr;

dmu_imu_rds_intx_csr_int_b_int_clr_reg int_b_int_clr_reg
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.int_b_int_clr_reg_w_ld	(int_b_int_clr_reg_w_ld),
	.csrbus_wr_data	(daemon_csrbus_wr_data),
	.int_b_int_clr_reg_csrbus_read_data	(int_b_int_clr_reg_csrbus_read_data),
	.int_b_int_clr_reg_clr_hw_ld	(int_b_int_clr_reg_clr_hw_ld),
	.int_b_int_clr_reg_clr_hw_write	(int_b_int_clr_reg_clr_hw_write),
	.int_b_int_clr_reg_clr_hw_read	(int_b_int_clr_reg_clr_hw_read)
	);

wire int_c_int_clr_reg_w_ld =int_c_int_clr_reg_select_pulse & daemon_csrbus_wr;

dmu_imu_rds_intx_csr_int_c_int_clr_reg int_c_int_clr_reg
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.int_c_int_clr_reg_w_ld	(int_c_int_clr_reg_w_ld),
	.csrbus_wr_data	(daemon_csrbus_wr_data),
	.int_c_int_clr_reg_csrbus_read_data	(int_c_int_clr_reg_csrbus_read_data),
	.int_c_int_clr_reg_clr_hw_ld	(int_c_int_clr_reg_clr_hw_ld),
	.int_c_int_clr_reg_clr_hw_write	(int_c_int_clr_reg_clr_hw_write),
	.int_c_int_clr_reg_clr_hw_read	(int_c_int_clr_reg_clr_hw_read)
	);

wire int_d_int_clr_reg_w_ld =int_d_int_clr_reg_select_pulse & daemon_csrbus_wr;

dmu_imu_rds_intx_csr_int_d_int_clr_reg int_d_int_clr_reg
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.int_d_int_clr_reg_w_ld	(int_d_int_clr_reg_w_ld),
	.csrbus_wr_data	(daemon_csrbus_wr_data),
	.int_d_int_clr_reg_csrbus_read_data	(int_d_int_clr_reg_csrbus_read_data),
	.int_d_int_clr_reg_clr_hw_ld	(int_d_int_clr_reg_clr_hw_ld),
	.int_d_int_clr_reg_clr_hw_write	(int_d_int_clr_reg_clr_hw_write),
	.int_d_int_clr_reg_clr_hw_read	(int_d_int_clr_reg_clr_hw_read)
	);

endmodule // dmu_imu_rds_intx_default_grp
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_imu_rds_intx_default_grp.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_imu_rds_intx_default_grp
	36	(
	37	clk,
	38	intx_status_reg_select,
	39	intx_status_reg_ext_read_data,
	40	int_a_int_clr_reg_clr_hw_ld,
	41	int_a_int_clr_reg_clr_hw_write,
	42	int_a_int_clr_reg_clr_hw_read,
	43	int_a_int_clr_reg_select_pulse,
	44	int_b_int_clr_reg_clr_hw_ld,
	45	int_b_int_clr_reg_clr_hw_write,
	46	int_b_int_clr_reg_clr_hw_read,
	47	int_b_int_clr_reg_select_pulse,
	48	int_c_int_clr_reg_clr_hw_ld,
	49	int_c_int_clr_reg_clr_hw_write,
	50	int_c_int_clr_reg_clr_hw_read,
	51	int_c_int_clr_reg_select_pulse,
	52	int_d_int_clr_reg_clr_hw_ld,
	53	int_d_int_clr_reg_clr_hw_write,
	54	int_d_int_clr_reg_clr_hw_read,
	55	int_d_int_clr_reg_select_pulse,
	56	rst_l,
	57	daemon_csrbus_wr_in,
	58	daemon_csrbus_wr_data_in,
	59	read_data_0_out
	60	);
	61
	62	//====================================================
	63	// Polarity declarations
	64	//====================================================
65	input clk; // Clock signal
66	input intx_status_reg_select; // select
67	input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] intx_status_reg_ext_read_data;
68	// Read Data
69	input int_a_int_clr_reg_clr_hw_ld; // Hardware load enable for
70	// int_a_int_clr_reg_clr. When set, <hw
71	// write signal> will be loaded into
72	// int_a_int_clr_reg.
73	input int_a_int_clr_reg_clr_hw_write; // data bus for hw loading of
74	// int_a_int_clr_reg_clr.
75	output int_a_int_clr_reg_clr_hw_read; // This signal provides the current value
76	// of int_a_int_clr_reg_clr.
77	input int_a_int_clr_reg_select_pulse; // select
78	input int_b_int_clr_reg_clr_hw_ld; // Hardware load enable for
79	// int_b_int_clr_reg_clr. When set, <hw
80	// write signal> will be loaded into
81	// int_b_int_clr_reg.
82	input int_b_int_clr_reg_clr_hw_write; // data bus for hw loading of
83	// int_b_int_clr_reg_clr.
84	output int_b_int_clr_reg_clr_hw_read; // This signal provides the current value
85	// of int_b_int_clr_reg_clr.
86	input int_b_int_clr_reg_select_pulse; // select
87	input int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for
88	// int_c_int_clr_reg_clr. When set, <hw
89	// write signal> will be loaded into
90	// int_c_int_clr_reg.
91	input int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of
92	// int_c_int_clr_reg_clr.
93	output int_c_int_clr_reg_clr_hw_read; // This signal provides the current value
94	// of int_c_int_clr_reg_clr.
95	input int_c_int_clr_reg_select_pulse; // select
96	input int_d_int_clr_reg_clr_hw_ld; // Hardware load enable for
97	// int_d_int_clr_reg_clr. When set, <hw
98	// write signal> will be loaded into
99	// int_d_int_clr_reg.
100	input int_d_int_clr_reg_clr_hw_write; // data bus for hw loading of
101	// int_d_int_clr_reg_clr.
102	output int_d_int_clr_reg_clr_hw_read; // This signal provides the current value
103	// of int_d_int_clr_reg_clr.
104	input int_d_int_clr_reg_select_pulse; // select
105	input rst_l; // HW reset
106	input daemon_csrbus_wr_in; // csrbus_wr
107	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
108	output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
109
110	//====================================================
111	// Type declarations
112	//====================================================
113	wire clk; // Clock signal
114	wire intx_status_reg_select; // select
115	wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] intx_status_reg_ext_read_data;
116	// Read Data
117	wire int_a_int_clr_reg_clr_hw_ld; // Hardware load enable for
118	// int_a_int_clr_reg_clr. When set, <hw write
119	// signal> will be loaded into
120	// int_a_int_clr_reg.
121	wire int_a_int_clr_reg_clr_hw_write; // data bus for hw loading of
122	// int_a_int_clr_reg_clr.
123	wire int_a_int_clr_reg_clr_hw_read; // This signal provides the current value
124	// of int_a_int_clr_reg_clr.
125	wire int_a_int_clr_reg_select_pulse; // select
126	wire int_b_int_clr_reg_clr_hw_ld; // Hardware load enable for
127	// int_b_int_clr_reg_clr. When set, <hw write
128	// signal> will be loaded into
129	// int_b_int_clr_reg.
130	wire int_b_int_clr_reg_clr_hw_write; // data bus for hw loading of
131	// int_b_int_clr_reg_clr.
132	wire int_b_int_clr_reg_clr_hw_read; // This signal provides the current value
133	// of int_b_int_clr_reg_clr.
134	wire int_b_int_clr_reg_select_pulse; // select
135	wire int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for
136	// int_c_int_clr_reg_clr. When set, <hw write
137	// signal> will be loaded into
138	// int_c_int_clr_reg.
139	wire int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of
140	// int_c_int_clr_reg_clr.
141	wire int_c_int_clr_reg_clr_hw_read; // This signal provides the current value
142	// of int_c_int_clr_reg_clr.
143	wire int_c_int_clr_reg_select_pulse; // select
144	wire int_d_int_clr_reg_clr_hw_ld; // Hardware load enable for
145	// int_d_int_clr_reg_clr. When set, <hw write
146	// signal> will be loaded into
147	// int_d_int_clr_reg.
148	wire int_d_int_clr_reg_clr_hw_write; // data bus for hw loading of
149	// int_d_int_clr_reg_clr.
150	wire int_d_int_clr_reg_clr_hw_read; // This signal provides the current value
151	// of int_d_int_clr_reg_clr.
152	wire int_d_int_clr_reg_select_pulse; // select
153	wire rst_l; // HW reset
154	wire daemon_csrbus_wr_in; // csrbus_wr
155	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
156	wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
157
158
159	//====================================================
160	// Local signals
161	//====================================================
162	//----- For CSR register: int_a_int_clr_reg
163	wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH-1:0] int_a_int_clr_reg_csrbus_read_data;
164	// Entry Based Read Data
165
166	//----- For CSR register: int_b_int_clr_reg
167	wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WIDTH-1:0] int_b_int_clr_reg_csrbus_read_data;
168	// Entry Based Read Data
169
170	//----- For CSR register: int_c_int_clr_reg
171	wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] int_c_int_clr_reg_csrbus_read_data;
172	// Entry Based Read Data
173
174	//----- For CSR register: int_d_int_clr_reg
175	wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WIDTH-1:0] int_d_int_clr_reg_csrbus_read_data;
176	// Entry Based Read Data
177
178	//====================================================
179	// Assignments only (first stage)
180	//====================================================
181	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in;
182	wire daemon_csrbus_wr = daemon_csrbus_wr_in;
183
184	//====================================================
185	// Automatic hw_ld / hw_write
186	//====================================================
187
188	//====================================================
189	// Extern select
190	//====================================================
191
192	//=====================================================
193	// OUTPUT: read_data_out
194	//=====================================================
195	dmu_imu_rds_intx_csrpipe_5 dmu_imu_rds_intx_csrpipe_5_inst_1
196	(
197	.clk (clk),
198	.rst_l (rst_l),
199	.reg_in (1'b1),
200	.reg_out (1'b1),
201	.data0 (intx_status_reg_ext_read_data),
202	.sel0 (intx_status_reg_select),
203	.data1 (int_a_int_clr_reg_csrbus_read_data),
204	.sel1 (int_a_int_clr_reg_select_pulse),
205	.data2 (int_b_int_clr_reg_csrbus_read_data),
206	.sel2 (int_b_int_clr_reg_select_pulse),
207	.data3 (int_c_int_clr_reg_csrbus_read_data),
208	.sel3 (int_c_int_clr_reg_select_pulse),
209	.data4 (int_d_int_clr_reg_csrbus_read_data),
210	.sel4 (int_d_int_clr_reg_select_pulse),
211	.out (read_data_0_out)
212	);
213
214
215	//====================================================
216	// Instantiation of registers
217	//====================================================
218
219	wire int_a_int_clr_reg_w_ld =int_a_int_clr_reg_select_pulse & daemon_csrbus_wr;
220
221	dmu_imu_rds_intx_csr_int_a_int_clr_reg int_a_int_clr_reg
222	(
223	.clk (clk),
224	.rst_l (rst_l),
225	.int_a_int_clr_reg_w_ld (int_a_int_clr_reg_w_ld),
226	.csrbus_wr_data (daemon_csrbus_wr_data),
227	.int_a_int_clr_reg_csrbus_read_data (int_a_int_clr_reg_csrbus_read_data),
228	.int_a_int_clr_reg_clr_hw_ld (int_a_int_clr_reg_clr_hw_ld),
229	.int_a_int_clr_reg_clr_hw_write (int_a_int_clr_reg_clr_hw_write),
230	.int_a_int_clr_reg_clr_hw_read (int_a_int_clr_reg_clr_hw_read)
231	);
232
233	wire int_b_int_clr_reg_w_ld =int_b_int_clr_reg_select_pulse & daemon_csrbus_wr;
234
235	dmu_imu_rds_intx_csr_int_b_int_clr_reg int_b_int_clr_reg
236	(
237	.clk (clk),
238	.rst_l (rst_l),
239	.int_b_int_clr_reg_w_ld (int_b_int_clr_reg_w_ld),
240	.csrbus_wr_data (daemon_csrbus_wr_data),
241	.int_b_int_clr_reg_csrbus_read_data (int_b_int_clr_reg_csrbus_read_data),
242	.int_b_int_clr_reg_clr_hw_ld (int_b_int_clr_reg_clr_hw_ld),
243	.int_b_int_clr_reg_clr_hw_write (int_b_int_clr_reg_clr_hw_write),
244	.int_b_int_clr_reg_clr_hw_read (int_b_int_clr_reg_clr_hw_read)
245	);
246
247	wire int_c_int_clr_reg_w_ld =int_c_int_clr_reg_select_pulse & daemon_csrbus_wr;
248
249	dmu_imu_rds_intx_csr_int_c_int_clr_reg int_c_int_clr_reg
250	(
251	.clk (clk),
252	.rst_l (rst_l),
253	.int_c_int_clr_reg_w_ld (int_c_int_clr_reg_w_ld),
254	.csrbus_wr_data (daemon_csrbus_wr_data),
255	.int_c_int_clr_reg_csrbus_read_data (int_c_int_clr_reg_csrbus_read_data),
256	.int_c_int_clr_reg_clr_hw_ld (int_c_int_clr_reg_clr_hw_ld),
257	.int_c_int_clr_reg_clr_hw_write (int_c_int_clr_reg_clr_hw_write),
258	.int_c_int_clr_reg_clr_hw_read (int_c_int_clr_reg_clr_hw_read)
259	);
260
261	wire int_d_int_clr_reg_w_ld =int_d_int_clr_reg_select_pulse & daemon_csrbus_wr;
262
263	dmu_imu_rds_intx_csr_int_d_int_clr_reg int_d_int_clr_reg
264	(
265	.clk (clk),
266	.rst_l (rst_l),
267	.int_d_int_clr_reg_w_ld (int_d_int_clr_reg_w_ld),
268	.csrbus_wr_data (daemon_csrbus_wr_data),
269	.int_d_int_clr_reg_csrbus_read_data (int_d_int_clr_reg_csrbus_read_data),
270	.int_d_int_clr_reg_clr_hw_ld (int_d_int_clr_reg_clr_hw_ld),
271	.int_d_int_clr_reg_clr_hw_write (int_d_int_clr_reg_clr_hw_write),
272	.int_d_int_clr_reg_clr_hw_read (int_d_int_clr_reg_clr_hw_read)
273	);
274
275	endmodule // dmu_imu_rds_intx_default_grp