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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_mess.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_mess ( | |
36 | clk, | |
37 | rst_l, | |
38 | ||
39 | pipe_select_in, | |
40 | message_code, | |
41 | ||
42 | pipe_select_out, | |
43 | header_good, | |
44 | message_eq_num, | |
45 | ||
46 | rds2ics_pmeack_mes_not_en_error, | |
47 | rds2ics_pmpme_mes_not_en_error, | |
48 | rds2ics_fatal_mes_not_en_error, | |
49 | rds2ics_nonfatal_mes_not_en_error, | |
50 | rds2ics_cor_mes_not_en_error, | |
51 | ||
52 | csrbus_valid, | |
53 | csrbus_done, | |
54 | csrbus_mapped, | |
55 | csrbus_wr_data, | |
56 | csrbus_wr, | |
57 | csrbus_read_data, | |
58 | csrbus_addr, | |
59 | csrbus_src_bus, | |
60 | csrbus_acc_vio, | |
61 | ||
62 | // Static ID Sel | |
63 | ||
64 | j2d_instance_id | |
65 | ||
66 | ||
67 | ); | |
68 | ||
69 | ||
70 | //############################################################################ | |
71 | // PORT DECLARATIONS | |
72 | //############################################################################ | |
73 | ||
74 | //------------------------------------------------------------------------ | |
75 | // Clock and Reset Signals | |
76 | //------------------------------------------------------------------------ | |
77 | input clk; | |
78 | input rst_l; | |
79 | ||
80 | ||
81 | //------------------------------------------------------------------------ | |
82 | // Input Select Signals | |
83 | //------------------------------------------------------------------------ | |
84 | input pipe_select_in; | |
85 | input [7:0] message_code; | |
86 | ||
87 | //------------------------------------------------------------------------ | |
88 | // Output Signals | |
89 | //------------------------------------------------------------------------ | |
90 | output pipe_select_out; | |
91 | output header_good; | |
92 | output [5:0] message_eq_num; | |
93 | ||
94 | ||
95 | output rds2ics_pmeack_mes_not_en_error; | |
96 | output rds2ics_pmpme_mes_not_en_error; | |
97 | output rds2ics_fatal_mes_not_en_error; | |
98 | output rds2ics_nonfatal_mes_not_en_error; | |
99 | output rds2ics_cor_mes_not_en_error; | |
100 | ||
101 | //------------------------------------------------------------------------ | |
102 | // PIO INTERFACE | |
103 | //------------------------------------------------------------------------ | |
104 | input csrbus_valid; | |
105 | output csrbus_done; | |
106 | output csrbus_mapped; | |
107 | ||
108 | ||
109 | input [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_wr_data; | |
110 | input csrbus_wr; | |
111 | ||
112 | output [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_read_data; | |
113 | ||
114 | input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] csrbus_addr; | |
115 | ||
116 | input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] csrbus_src_bus; | |
117 | output csrbus_acc_vio; | |
118 | ||
119 | ||
120 | ||
121 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; | |
122 | ||
123 | ||
124 | ||
125 | //############################################################################ | |
126 | // PARAMETERS | |
127 | //############################################################################ | |
128 | parameter ERR_COR_CODE = 8'b0011_0000; | |
129 | parameter ERR_NONFATAL_CODE = 8'b0011_0001; | |
130 | parameter ERR_FATAL_CODE = 8'b0011_0011; | |
131 | parameter PM_PME_CODE = 8'b0001_1000; | |
132 | parameter PME_TO_ACK_CODE = 8'b0001_1011; | |
133 | ||
134 | ||
135 | ||
136 | //############################################################################ | |
137 | // SIGNAL DECLARATIONS | |
138 | //############################################################################ | |
139 | ||
140 | ||
141 | //************************************************** | |
142 | // Wire | |
143 | //************************************************** | |
144 | ||
145 | ||
146 | //-------------------------- | |
147 | // Unsupported Message Signals | |
148 | //-------------------------- | |
149 | wire unsupported_valid; | |
150 | wire [5:0] unsupported_eq; | |
151 | ||
152 | //-------------------------- | |
153 | // Message Signals | |
154 | //-------------------------- | |
155 | wire [7:0] message_valid; | |
156 | wire [7:0] message_eq_bit_5; | |
157 | wire [7:0] message_eq_bit_4; | |
158 | wire [7:0] message_eq_bit_3; | |
159 | wire [7:0] message_eq_bit_2; | |
160 | wire [7:0] message_eq_bit_1; | |
161 | wire [7:0] message_eq_bit_0; | |
162 | ||
163 | //-------------------------- | |
164 | // Supported Message Selects | |
165 | //-------------------------- | |
166 | ||
167 | wire err_corr_sel; | |
168 | wire err_nonfatal_sel; | |
169 | wire err_fatal_sel; | |
170 | wire pm_pme_sel; | |
171 | wire pme_to_ack_sel; | |
172 | ||
173 | wire [4:0] supported_sel; | |
174 | ||
175 | //-------------------------- | |
176 | // Supported Message Valid | |
177 | //-------------------------- | |
178 | ||
179 | wire err_corr_valid; | |
180 | wire err_nonfatal_valid; | |
181 | wire err_fatal_valid; | |
182 | wire pm_pme_valid; | |
183 | wire pme_to_ack_valid; | |
184 | ||
185 | //-------------------------- | |
186 | // Supported Message EQ Num | |
187 | //-------------------------- | |
188 | ||
189 | wire [5:0] err_corr_eq; | |
190 | wire [5:0] err_nonfatal_eq; | |
191 | wire [5:0] err_fatal_eq; | |
192 | wire [5:0] pm_pme_eq; | |
193 | wire [5:0] pme_to_ack_eq; | |
194 | ||
195 | //-------------------------- | |
196 | // HW Address Signal | |
197 | //-------------------------- | |
198 | //wire header_error; | |
199 | wire n_header_good; | |
200 | wire [5:0] n_message_eq_num; | |
201 | wire n_rds2ics_pmeack_mes_not_en_error; | |
202 | wire n_rds2ics_pmpme_mes_not_en_error; | |
203 | wire n_rds2ics_fatal_mes_not_en_error; | |
204 | wire n_rds2ics_nonfatal_mes_not_en_error; | |
205 | wire n_rds2ics_cor_mes_not_en_error; | |
206 | ||
207 | //************************************************** | |
208 | // Registers that Are Not Flops | |
209 | //************************************************** | |
210 | ||
211 | reg [2:0] message_sel; | |
212 | ||
213 | //************************************************** | |
214 | // Registers that Are Flops | |
215 | //************************************************** | |
216 | reg pipe_select_out; | |
217 | reg header_good; | |
218 | reg [5:0] message_eq_num; | |
219 | reg rds2ics_pmeack_mes_not_en_error; | |
220 | reg rds2ics_pmpme_mes_not_en_error; | |
221 | reg rds2ics_fatal_mes_not_en_error; | |
222 | reg rds2ics_nonfatal_mes_not_en_error; | |
223 | reg rds2ics_cor_mes_not_en_error; | |
224 | ||
225 | //############################################################################ | |
226 | // ZERO IN CHECKERS | |
227 | //############################################################################ | |
228 | ||
229 | //--------------------------------------------------- | |
230 | // One Hot Message Decodes | |
231 | //--------------------------------------------------- | |
232 | ||
233 | //0in bits_on -var supported_sel -max 1 | |
234 | ||
235 | //############################################################################ | |
236 | // COMBINATIONAL LOGIC | |
237 | //############################################################################ | |
238 | ||
239 | //-------------------------------------------------------------------------- | |
240 | // Decode the Supported Message Types | |
241 | //-------------------------------------------------------------------------- | |
242 | assign err_corr_sel = pipe_select_in & (message_code == ERR_COR_CODE); | |
243 | assign err_nonfatal_sel = pipe_select_in & (message_code == ERR_NONFATAL_CODE); | |
244 | assign err_fatal_sel = pipe_select_in & (message_code == ERR_FATAL_CODE); | |
245 | assign pm_pme_sel = pipe_select_in & (message_code == PM_PME_CODE); | |
246 | assign pme_to_ack_sel = pipe_select_in & (message_code == PME_TO_ACK_CODE); | |
247 | ||
248 | assign supported_sel = {err_corr_sel, err_nonfatal_sel, err_fatal_sel, pm_pme_sel, pme_to_ack_sel}; | |
249 | ||
250 | //-------------------------------------------------------------------------- | |
251 | // Unsupported Valid and EQ | |
252 | // | |
253 | // Since all unsuported messages are dropped silently | |
254 | // the following two signal are used as the defaults when | |
255 | // a non valid message is received | |
256 | // | |
257 | // - the unsupported_valid signal is used to make the header NOT good | |
258 | // - the unsupported_eq sets the EQ to a default value of zero | |
259 | //-------------------------------------------------------------------------- | |
260 | assign unsupported_valid = 1'b0; | |
261 | assign unsupported_eq = 6'h0; | |
262 | ||
263 | //-------------------------------------------------------------------------- | |
264 | // Encode Supported Messages and Unsupported Messages | |
265 | // | |
266 | // Turn the supported messages and unsupported message into a encoded number | |
267 | // - atten_but_press_sel = 0 | |
268 | // - pme_to_ack_sel = 1 | |
269 | // - pm_pme_sel = 2 | |
270 | // - err_fatal_sel = 3 | |
271 | // - err_nonfatal_sel = 4 | |
272 | // - err_corr_sel = 5 | |
273 | // | |
274 | // - all unsupported = 6 | |
275 | //-------------------------------------------------------------------------- | |
276 | ||
277 | always @(supported_sel) | |
278 | begin | |
279 | case (supported_sel) | |
280 | 5'b00001: message_sel = 3'h0; // pme_to_ack_sel | |
281 | 5'b00010: message_sel = 3'h1; // pm_pme_sel | |
282 | 5'b00100: message_sel = 3'h2; // err_fatal_sel | |
283 | 5'b01000: message_sel = 3'h3; // err_nonfatal_sel | |
284 | 5'b10000: message_sel = 3'h4; // err_corr_sel | |
285 | default: message_sel = 3'h5; // unsuported | |
286 | endcase | |
287 | end | |
288 | ||
289 | ||
290 | //-------------------------------------------------------------------------- | |
291 | // Concatenate the valid and eq number data | |
292 | // | |
293 | // - Since we support 36 EQ's this takes 6 bits when encoded | |
294 | // - Each Message can be rounted to any of those EQ's depending | |
295 | // on the SW programmed value | |
296 | // | |
297 | // - Since we support 6 messages + unsupported we have 7 EQ's to | |
298 | // choose from | |
299 | // | |
300 | // - Below is code to set up each of the 6 EQ bits with 1 of 7 possible | |
301 | // selections | |
302 | // | |
303 | // - This code will be used as a mux later on based on the selected | |
304 | // message | |
305 | // | |
306 | // - The same is done for the valid signals | |
307 | //-------------------------------------------------------------------------- | |
308 | assign message_valid = {2'h0,unsupported_valid, err_corr_valid, err_nonfatal_valid, err_fatal_valid, | |
309 | pm_pme_valid, pme_to_ack_valid}; | |
310 | ||
311 | assign message_eq_bit_5 = {2'h0,unsupported_eq[5], err_corr_eq[5], err_nonfatal_eq[5], err_fatal_eq[5], | |
312 | pm_pme_eq[5], pme_to_ack_eq[5]}; | |
313 | ||
314 | assign message_eq_bit_4 = {2'h0,unsupported_eq[4], err_corr_eq[4], err_nonfatal_eq[4], err_fatal_eq[4], | |
315 | pm_pme_eq[4], pme_to_ack_eq[4]}; | |
316 | ||
317 | assign message_eq_bit_3 = {2'h0,unsupported_eq[3], err_corr_eq[3], err_nonfatal_eq[3], err_fatal_eq[3], | |
318 | pm_pme_eq[3], pme_to_ack_eq[3]}; | |
319 | ||
320 | assign message_eq_bit_2 = {2'h0,unsupported_eq[2], err_corr_eq[2], err_nonfatal_eq[2], err_fatal_eq[2], | |
321 | pm_pme_eq[2], pme_to_ack_eq[2]}; | |
322 | ||
323 | assign message_eq_bit_1 = {2'h0,unsupported_eq[1], err_corr_eq[1], err_nonfatal_eq[1], err_fatal_eq[1], | |
324 | pm_pme_eq[1], pme_to_ack_eq[1]}; | |
325 | ||
326 | assign message_eq_bit_0 = {2'h0,unsupported_eq[0], err_corr_eq[0], err_nonfatal_eq[0], err_fatal_eq[0], | |
327 | pm_pme_eq[0], pme_to_ack_eq[0]}; | |
328 | ||
329 | ||
330 | //-------------------------------------------------------------------------- | |
331 | // Get the outputs Ready to be flopped. | |
332 | // | |
333 | // - Determine if the Header is Good | |
334 | // - The header is good if: | |
335 | // - pipe stage was selected | |
336 | // - message is valid (as set by SW) for message now in pipe | |
337 | // - Done by the mux set up above | |
338 | // - Using message_sel as select line | |
339 | // - Unsupported are always invalid | |
340 | // | |
341 | // - Determin if the Value of the EQ | |
342 | // - Done by the mux set up above | |
343 | // - Using message_sel as select line | |
344 | // - Unsupported are always EQ 0 | |
345 | // | |
346 | //-------------------------------------------------------------------------- | |
347 | ||
348 | assign n_header_good = pipe_select_in & message_valid[message_sel]; | |
349 | ||
350 | assign n_message_eq_num = {message_eq_bit_5[message_sel],message_eq_bit_4[message_sel],message_eq_bit_3[message_sel], | |
351 | message_eq_bit_2[message_sel],message_eq_bit_1[message_sel],message_eq_bit_0[message_sel]}; | |
352 | ||
353 | ||
354 | assign n_rds2ics_pmeack_mes_not_en_error = pipe_select_in & ~message_valid[0] & (message_sel == 3'h0); | |
355 | assign n_rds2ics_pmpme_mes_not_en_error = pipe_select_in & ~message_valid[1] & (message_sel == 3'h1); | |
356 | assign n_rds2ics_fatal_mes_not_en_error = pipe_select_in & ~message_valid[2] & (message_sel == 3'h2); | |
357 | assign n_rds2ics_nonfatal_mes_not_en_error = pipe_select_in & ~message_valid[3] & (message_sel == 3'h3); | |
358 | assign n_rds2ics_cor_mes_not_en_error = pipe_select_in & ~message_valid[4] & (message_sel == 3'h4); | |
359 | ||
360 | ||
361 | ||
362 | //############################################################################ | |
363 | // SEQUENTIAL LOGIC | |
364 | //############################################################################ | |
365 | ||
366 | ||
367 | //-------------------------------------------------------------------------- | |
368 | // FLOP THE OUTPUTS | |
369 | // | |
370 | //-------------------------------------------------------------------------- | |
371 | ||
372 | always @ (posedge clk) | |
373 | if (!rst_l) | |
374 | begin // At reset reset all of them to zero. | |
375 | pipe_select_out <= 1'b0; | |
376 | header_good <= 1'b0; | |
377 | message_eq_num <= 6'h0; | |
378 | rds2ics_pmeack_mes_not_en_error <= 1'b0; | |
379 | rds2ics_pmpme_mes_not_en_error <= 1'b0; | |
380 | rds2ics_fatal_mes_not_en_error <= 1'b0; | |
381 | rds2ics_nonfatal_mes_not_en_error <= 1'b0; | |
382 | rds2ics_cor_mes_not_en_error <= 1'b0; | |
383 | end | |
384 | else | |
385 | begin | |
386 | pipe_select_out <= pipe_select_in; | |
387 | header_good <= n_header_good; | |
388 | message_eq_num <= n_message_eq_num; | |
389 | rds2ics_pmeack_mes_not_en_error <= n_rds2ics_pmeack_mes_not_en_error; | |
390 | rds2ics_pmpme_mes_not_en_error <= n_rds2ics_pmpme_mes_not_en_error; | |
391 | rds2ics_fatal_mes_not_en_error <= n_rds2ics_fatal_mes_not_en_error; | |
392 | rds2ics_nonfatal_mes_not_en_error <= n_rds2ics_nonfatal_mes_not_en_error; | |
393 | rds2ics_cor_mes_not_en_error <= n_rds2ics_cor_mes_not_en_error; | |
394 | end | |
395 | ||
396 | ||
397 | ||
398 | //############################################################################ | |
399 | // MODULE INSTANTIATIONS | |
400 | //############################################################################ | |
401 | ||
402 | ||
403 | dmu_imu_rds_mess_csr csr ( | |
404 | ||
405 | .clk (clk), | |
406 | .csrbus_valid (csrbus_valid), | |
407 | .csrbus_done (csrbus_done), | |
408 | .csrbus_mapped (csrbus_mapped), | |
409 | .csrbus_wr_data (csrbus_wr_data), | |
410 | .csrbus_wr (csrbus_wr), | |
411 | .csrbus_read_data (csrbus_read_data), | |
412 | .csrbus_addr (csrbus_addr), | |
413 | .rst_l (rst_l), | |
414 | ||
415 | .csrbus_src_bus (csrbus_src_bus), | |
416 | .csrbus_acc_vio (csrbus_acc_vio), | |
417 | .instance_id (j2d_instance_id), | |
418 | ||
419 | .err_cor_mapping_v_hw_read (err_corr_valid), | |
420 | .err_cor_mapping_eqnum_hw_read (err_corr_eq), | |
421 | .err_nonfatal_mapping_v_hw_read (err_nonfatal_valid), | |
422 | .err_nonfatal_mapping_eqnum_hw_read (err_nonfatal_eq), | |
423 | .err_fatal_mapping_v_hw_read (err_fatal_valid), | |
424 | .err_fatal_mapping_eqnum_hw_read (err_fatal_eq), | |
425 | .pm_pme_mapping_v_hw_read (pm_pme_valid), | |
426 | .pm_pme_mapping_eqnum_hw_read (pm_pme_eq), | |
427 | .pme_to_ack_mapping_v_hw_read (pme_to_ack_valid), | |
428 | .pme_to_ack_mapping_eqnum_hw_read (pme_to_ack_eq) | |
429 | ); | |
430 | ||
431 | ||
432 | endmodule |