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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_msi_addr_decode.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_msi_addr_decode | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | daemon_csrbus_valid, | |
40 | daemon_csrbus_addr, | |
41 | csrbus_src_bus, | |
42 | daemon_csrbus_wr, | |
43 | daemon_csrbus_wr_out, | |
44 | daemon_csrbus_wr_data, | |
45 | daemon_csrbus_wr_data_out, | |
46 | daemon_csrbus_mapped, | |
47 | csrbus_acc_vio, | |
48 | daemon_transaction_in_progress, | |
49 | instance_id, | |
50 | daemon_csrbus_done, | |
51 | msi_mapping_select, | |
52 | msi_clear_reg_select, | |
53 | int_mondo_data_0_reg_select_pulse, | |
54 | int_mondo_data_1_reg_select_pulse | |
55 | ); | |
56 | ||
57 | //==================================================================== | |
58 | // Polarity declarations | |
59 | //==================================================================== | |
60 | input clk; // Clock signal | |
61 | input rst_l; // Reset | |
62 | input daemon_csrbus_valid; // Daemon_Valid | |
63 | input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
64 | input [1:0] csrbus_src_bus; // Source bus | |
65 | input daemon_csrbus_wr; // Read/Write signal | |
66 | output daemon_csrbus_wr_out; // Read/Write signal | |
67 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
68 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
69 | output daemon_csrbus_mapped; // mapped | |
70 | output csrbus_acc_vio; // acc_vio | |
71 | input daemon_transaction_in_progress; // daemon_transaction_in_progress | |
72 | input instance_id; // Instance ID | |
73 | output daemon_csrbus_done; // Operation is done | |
74 | output msi_mapping_select; // select signal | |
75 | output msi_clear_reg_select; // select signal | |
76 | output int_mondo_data_0_reg_select_pulse; // select signal | |
77 | output int_mondo_data_1_reg_select_pulse; // select signal | |
78 | ||
79 | //==================================================================== | |
80 | // Type declarations | |
81 | //==================================================================== | |
82 | wire clk; // Clock signal | |
83 | wire rst_l; // Reset | |
84 | wire daemon_csrbus_valid; // Daemon_Valid | |
85 | wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr | |
86 | wire [1:0] csrbus_src_bus; // Source bus | |
87 | wire daemon_csrbus_wr; // Read/Write signal | |
88 | reg daemon_csrbus_wr_out; // Read/Write signal | |
89 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data | |
90 | reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data | |
91 | wire daemon_csrbus_mapped; // mapped | |
92 | wire csrbus_acc_vio; // acc_vio | |
93 | wire daemon_transaction_in_progress; // daemon_transaction_in_progress | |
94 | wire instance_id; // Instance ID | |
95 | wire daemon_csrbus_done; // Operation is done | |
96 | reg msi_mapping_select; // select signal | |
97 | reg msi_clear_reg_select; // select signal | |
98 | reg int_mondo_data_0_reg_select_pulse; // select signal | |
99 | reg int_mondo_data_1_reg_select_pulse; // select signal | |
100 | ||
101 | ||
102 | //==================================================================== | |
103 | // Clocked valid | |
104 | //==================================================================== | |
105 | reg clocked_valid; | |
106 | reg clocked_valid_pulse; | |
107 | always @(posedge clk) | |
108 | begin | |
109 | if(~rst_l) | |
110 | begin | |
111 | clocked_valid <= 1'b0; | |
112 | clocked_valid_pulse <= 1'b0; | |
113 | end | |
114 | else | |
115 | begin | |
116 | clocked_valid <= daemon_csrbus_valid; | |
117 | clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid; | |
118 | end | |
119 | end | |
120 | ||
121 | //==================================================================== | |
122 | // Address Decode | |
123 | //==================================================================== | |
124 | reg msi_mapping_addr_decoded; | |
125 | reg msi_clear_reg_addr_decoded; | |
126 | reg int_mondo_data_0_reg_addr_decoded; | |
127 | reg int_mondo_data_1_reg_addr_decoded; | |
128 | ||
129 | always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id) | |
130 | begin | |
131 | if (~daemon_csrbus_valid) | |
132 | begin | |
133 | msi_mapping_addr_decoded = 1'b0; | |
134 | msi_clear_reg_addr_decoded = 1'b0; | |
135 | int_mondo_data_0_reg_addr_decoded = 1'b0; | |
136 | int_mondo_data_1_reg_addr_decoded = 1'b0; | |
137 | end | |
138 | else | |
139 | case (instance_id) | |
140 | ||
141 | `FIRE_DLC_IMU_RDS_MSI_INSTANCE_ID_VALUE_A: | |
142 | begin | |
143 | msi_mapping_addr_decoded = | |
144 | {8'b0,daemon_csrbus_addr[26:8]} == | |
145 | `FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_HW_ADDR >> | |
146 | `FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_LOW_ADDR_WIDTH; | |
147 | msi_clear_reg_addr_decoded = | |
148 | {8'b0,daemon_csrbus_addr[26:8]} == | |
149 | `FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_HW_ADDR >> | |
150 | `FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_LOW_ADDR_WIDTH | | |
151 | {8'b0,daemon_csrbus_addr[26:8]} == | |
152 | `FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_HW_ADDR >> | |
153 | `FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_LOW_ADDR_WIDTH; | |
154 | int_mondo_data_0_reg_addr_decoded = | |
155 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_HW_ADDR; | |
156 | int_mondo_data_1_reg_addr_decoded = | |
157 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_HW_ADDR; | |
158 | end | |
159 | ||
160 | `FIRE_DLC_IMU_RDS_MSI_INSTANCE_ID_VALUE_B: | |
161 | begin | |
162 | msi_mapping_addr_decoded = | |
163 | {8'b0,daemon_csrbus_addr[26:8]} == | |
164 | `FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_MAPPING_HW_ADDR >> | |
165 | `FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_LOW_ADDR_WIDTH; | |
166 | msi_clear_reg_addr_decoded = | |
167 | {8'b0,daemon_csrbus_addr[26:8]} == | |
168 | `FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1C_ALIAS_HW_ADDR >> | |
169 | `FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_LOW_ADDR_WIDTH | | |
170 | {8'b0,daemon_csrbus_addr[26:8]} == | |
171 | `FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1S_ALIAS_HW_ADDR >> | |
172 | `FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_LOW_ADDR_WIDTH; | |
173 | int_mondo_data_0_reg_addr_decoded = | |
174 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_0_REG_HW_ADDR; | |
175 | int_mondo_data_1_reg_addr_decoded = | |
176 | daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_1_REG_HW_ADDR; | |
177 | end | |
178 | ||
179 | default: | |
180 | begin | |
181 | msi_mapping_addr_decoded = 1'b0; | |
182 | msi_clear_reg_addr_decoded = 1'b0; | |
183 | int_mondo_data_0_reg_addr_decoded = 1'b0; | |
184 | int_mondo_data_1_reg_addr_decoded = 1'b0; | |
185 | // vlint flag_system_call off | |
186 | // synopsys translate_off | |
187 | if(daemon_csrbus_valid) | |
188 | begin // axis tbcall_region | |
189 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_msi_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_imu_rds_msi_csr is bad"); `endif | |
190 | end // end of tbcall_region | |
191 | // synopsys translate_on | |
192 | // vlint flag_system_call on | |
193 | end | |
194 | endcase | |
195 | end | |
196 | ||
197 | //==================================================================== | |
198 | // Register violations | |
199 | //==================================================================== | |
200 | //----- reg_acc_vio: msi_mapping | |
201 | reg msi_mapping_acc_vio; | |
202 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
203 | msi_mapping_addr_decoded or | |
204 | daemon_transaction_in_progress) | |
205 | begin | |
206 | if (daemon_transaction_in_progress | ~msi_mapping_addr_decoded) | |
207 | msi_mapping_acc_vio = 1'b0; | |
208 | else | |
209 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
210 | // reads | |
211 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
212 | msi_mapping_acc_vio = 1'b0; | |
213 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
214 | msi_mapping_acc_vio = 1'b0; | |
215 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
216 | msi_mapping_acc_vio = 1'b0; | |
217 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
218 | msi_mapping_acc_vio = 1'b0; | |
219 | // writes | |
220 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
221 | msi_mapping_acc_vio = 1'b0; | |
222 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
223 | msi_mapping_acc_vio = 1'b0; | |
224 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
225 | msi_mapping_acc_vio = 1'b0; | |
226 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
227 | msi_mapping_acc_vio = 1'b0; | |
228 | ||
229 | default: | |
230 | begin | |
231 | msi_mapping_acc_vio = 1'b0; | |
232 | begin // axis tbcall_region | |
233 | // vlint flag_system_call off | |
234 | // synopsys translate_off | |
235 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_msi_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_msi_csr_a_msi_mapping"); `endif | |
236 | // synopsys translate_on | |
237 | // vlint flag_system_call on | |
238 | end // end of tbcall_region | |
239 | end | |
240 | endcase | |
241 | end | |
242 | //----- reg_acc_vio: msi_clear_reg | |
243 | reg msi_clear_reg_acc_vio; | |
244 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
245 | msi_clear_reg_addr_decoded or | |
246 | daemon_transaction_in_progress) | |
247 | begin | |
248 | if (daemon_transaction_in_progress | ~msi_clear_reg_addr_decoded) | |
249 | msi_clear_reg_acc_vio = 1'b0; | |
250 | else | |
251 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
252 | // reads | |
253 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
254 | msi_clear_reg_acc_vio = 1'b0; | |
255 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
256 | msi_clear_reg_acc_vio = 1'b0; | |
257 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
258 | msi_clear_reg_acc_vio = 1'b0; | |
259 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
260 | msi_clear_reg_acc_vio = 1'b0; | |
261 | // writes | |
262 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
263 | msi_clear_reg_acc_vio = 1'b0; | |
264 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
265 | msi_clear_reg_acc_vio = 1'b0; | |
266 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
267 | msi_clear_reg_acc_vio = 1'b0; | |
268 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
269 | msi_clear_reg_acc_vio = 1'b0; | |
270 | ||
271 | default: | |
272 | begin | |
273 | msi_clear_reg_acc_vio = 1'b0; | |
274 | begin // axis tbcall_region | |
275 | // vlint flag_system_call off | |
276 | // synopsys translate_off | |
277 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_msi_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_msi_csr_a_msi_clear_reg_rw1c_alias"); `endif | |
278 | // synopsys translate_on | |
279 | // vlint flag_system_call on | |
280 | end // end of tbcall_region | |
281 | end | |
282 | endcase | |
283 | end | |
284 | //----- reg_acc_vio: int_mondo_data_0_reg | |
285 | reg int_mondo_data_0_reg_acc_vio; | |
286 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
287 | int_mondo_data_0_reg_addr_decoded or | |
288 | daemon_transaction_in_progress) | |
289 | begin | |
290 | if (daemon_transaction_in_progress | ~int_mondo_data_0_reg_addr_decoded) | |
291 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
292 | else | |
293 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
294 | // reads | |
295 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
296 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
297 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
298 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
299 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
300 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
301 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
302 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
303 | // writes | |
304 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
305 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
306 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
307 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
308 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
309 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
310 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
311 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
312 | ||
313 | default: | |
314 | begin | |
315 | int_mondo_data_0_reg_acc_vio = 1'b0; | |
316 | begin // axis tbcall_region | |
317 | // vlint flag_system_call off | |
318 | // synopsys translate_off | |
319 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_msi_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_msi_csr_a_int_mondo_data_0_reg"); `endif | |
320 | // synopsys translate_on | |
321 | // vlint flag_system_call on | |
322 | end // end of tbcall_region | |
323 | end | |
324 | endcase | |
325 | end | |
326 | //----- reg_acc_vio: int_mondo_data_1_reg | |
327 | reg int_mondo_data_1_reg_acc_vio; | |
328 | always @(csrbus_src_bus or daemon_csrbus_wr or | |
329 | int_mondo_data_1_reg_addr_decoded or | |
330 | daemon_transaction_in_progress) | |
331 | begin | |
332 | if (daemon_transaction_in_progress | ~int_mondo_data_1_reg_addr_decoded) | |
333 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
334 | else | |
335 | case ({csrbus_src_bus, daemon_csrbus_wr}) | |
336 | // reads | |
337 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}: | |
338 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
339 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}: | |
340 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
341 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}: | |
342 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
343 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}: | |
344 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
345 | // writes | |
346 | {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}: | |
347 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
348 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}: | |
349 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
350 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}: | |
351 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
352 | {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}: | |
353 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
354 | ||
355 | default: | |
356 | begin | |
357 | int_mondo_data_1_reg_acc_vio = 1'b0; | |
358 | begin // axis tbcall_region | |
359 | // vlint flag_system_call off | |
360 | // synopsys translate_off | |
361 | `ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_msi_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_msi_csr_a_int_mondo_data_1_reg"); `endif | |
362 | // synopsys translate_on | |
363 | // vlint flag_system_call on | |
364 | end // end of tbcall_region | |
365 | end | |
366 | endcase | |
367 | end | |
368 | ||
369 | //==================================================================== | |
370 | // Status: daemon_csrbus_mapped / csrbus_acc_vio | |
371 | //==================================================================== | |
372 | //----- OUTPUT: daemon_csrbus_mapped | |
373 | assign daemon_csrbus_mapped = clocked_valid_pulse & | |
374 | ( | |
375 | msi_mapping_addr_decoded | | |
376 | msi_clear_reg_addr_decoded | | |
377 | int_mondo_data_0_reg_addr_decoded | | |
378 | int_mondo_data_1_reg_addr_decoded | |
379 | ); | |
380 | ||
381 | ||
382 | // daemon_csrbus_mapped gets asserted after fixed number of cycles | |
383 | // after daemon_csrbus_valid become high | |
384 | /* 0in assert_together -name mapped_after_valid | |
385 | -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1)) | |
386 | -follower $0in_rising_edge(daemon_csrbus_mapped) | |
387 | -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid") | |
388 | -module dmu_imu_rds_msi_addr_decode | |
389 | -clock clk | |
390 | -active $0in_rising_edge(daemon_csrbus_mapped) | |
391 | */ | |
392 | ||
393 | // daemon_csrbus_mapped is a pulse | |
394 | /* 0in assert_timer -name daemon_csrbus_mapped_pulse | |
395 | -var daemon_csrbus_mapped -max 1 | |
396 | -message "daemon_csrbus_mapped pulse length is not 1" | |
397 | -module dmu_imu_rds_msi_addr_decode | |
398 | -clock clk | |
399 | */ | |
400 | //----- OUTPUT: csrbus_acc_vio | |
401 | assign csrbus_acc_vio = clocked_valid_pulse & | |
402 | msi_mapping_acc_vio | | |
403 | msi_clear_reg_acc_vio | | |
404 | int_mondo_data_0_reg_acc_vio | | |
405 | int_mondo_data_1_reg_acc_vio; | |
406 | ||
407 | //==================================================================== | |
408 | // Select | |
409 | //==================================================================== | |
410 | always @(posedge clk) | |
411 | begin | |
412 | if(~rst_l) | |
413 | begin | |
414 | msi_mapping_select <= 1'b0; | |
415 | msi_clear_reg_select <= 1'b0; | |
416 | int_mondo_data_0_reg_select_pulse <= 1'b0; | |
417 | int_mondo_data_1_reg_select_pulse <= 1'b0; | |
418 | end | |
419 | else | |
420 | begin | |
421 | msi_mapping_select <= | |
422 | ~ msi_mapping_acc_vio & | |
423 | msi_mapping_addr_decoded; | |
424 | ||
425 | msi_clear_reg_select <= | |
426 | ~ msi_clear_reg_acc_vio & | |
427 | msi_clear_reg_addr_decoded; | |
428 | ||
429 | int_mondo_data_0_reg_select_pulse <= | |
430 | ~int_mondo_data_0_reg_acc_vio & | |
431 | clocked_valid_pulse & | |
432 | int_mondo_data_0_reg_addr_decoded; | |
433 | ||
434 | int_mondo_data_1_reg_select_pulse <= | |
435 | ~int_mondo_data_1_reg_acc_vio & | |
436 | clocked_valid_pulse & | |
437 | int_mondo_data_1_reg_addr_decoded; | |
438 | ||
439 | end | |
440 | end | |
441 | ||
442 | //==================================================================== | |
443 | // daemon_csrbus_wr / daemon_csrbus_wr_data | |
444 | //==================================================================== | |
445 | always @(posedge clk) | |
446 | begin | |
447 | if(~rst_l) | |
448 | begin | |
449 | daemon_csrbus_wr_out <= 1'b0; | |
450 | daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0; | |
451 | end | |
452 | else | |
453 | begin | |
454 | daemon_csrbus_wr_out <= daemon_csrbus_wr; | |
455 | daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data; | |
456 | end | |
457 | end | |
458 | ||
459 | //==================================================================== | |
460 | // Cycle Counter: Used for ExtReadTiming / ExtWriteTiming | |
461 | //==================================================================== | |
462 | ||
463 | //==================================================================== | |
464 | // OUTPUT: daemon_csrbus_done (pipelining) | |
465 | //==================================================================== | |
466 | //----- DONE for internal/extern registers | |
467 | reg stage_1_daemon_csrbus_done_internal_0; | |
468 | reg stage_1_daemon_csrbus_done_internal_1; | |
469 | reg stage_2_daemon_csrbus_done_internal_0; | |
470 | reg stage_3_daemon_csrbus_done_internal_0; | |
471 | reg stage_4_daemon_csrbus_done_internal_0; | |
472 | ||
473 | always @(posedge clk) | |
474 | begin | |
475 | if(~rst_l) | |
476 | begin | |
477 | stage_1_daemon_csrbus_done_internal_0 <= 1'b0; | |
478 | stage_1_daemon_csrbus_done_internal_1 <= 1'b0; | |
479 | end | |
480 | else | |
481 | begin | |
482 | stage_1_daemon_csrbus_done_internal_0 <= | |
483 | int_mondo_data_0_reg_select_pulse | | |
484 | int_mondo_data_1_reg_select_pulse | | |
485 | msi_mapping_select & clocked_valid_pulse; | |
486 | stage_1_daemon_csrbus_done_internal_1 <= | |
487 | msi_clear_reg_select & clocked_valid_pulse; | |
488 | end | |
489 | if(~rst_l) | |
490 | begin | |
491 | stage_2_daemon_csrbus_done_internal_0 <= 1'b0; | |
492 | end | |
493 | else | |
494 | begin | |
495 | stage_2_daemon_csrbus_done_internal_0 <= | |
496 | stage_1_daemon_csrbus_done_internal_0 | | |
497 | stage_1_daemon_csrbus_done_internal_1; | |
498 | end | |
499 | if(~rst_l) | |
500 | begin | |
501 | stage_3_daemon_csrbus_done_internal_0 <= 1'b0; | |
502 | end | |
503 | else | |
504 | begin | |
505 | stage_3_daemon_csrbus_done_internal_0 <= | |
506 | stage_2_daemon_csrbus_done_internal_0; | |
507 | end | |
508 | if(~rst_l) | |
509 | begin | |
510 | stage_4_daemon_csrbus_done_internal_0 <= 1'b0; | |
511 | end | |
512 | else | |
513 | begin | |
514 | stage_4_daemon_csrbus_done_internal_0 <= | |
515 | stage_3_daemon_csrbus_done_internal_0; | |
516 | end | |
517 | end | |
518 | ||
519 | //----- OUTPUT: daemon_csrbus_done | |
520 | assign daemon_csrbus_done = daemon_csrbus_valid & | |
521 | ( | |
522 | stage_4_daemon_csrbus_done_internal_0 | |
523 | ); | |
524 | ||
525 | // daemon_csrbus_done gets asserted only when csrbus_valid is high | |
526 | /* 0in assert -name daemon_csrbus_done_high | |
527 | -var daemon_csrbus_valid -active daemon_csrbus_done | |
528 | -message "csrbus_done got asserted while csrbus_valid is low" | |
529 | -module dmu_imu_rds_msi_addr_decode | |
530 | -clock clk | |
531 | */ | |
532 | ||
533 | // daemon_csrbus_done is a pulse | |
534 | /* 0in assert_timer -name daemon_csrbus_done_pulse | |
535 | -var daemon_csrbus_done -max 1 | |
536 | -message "csrbus_done pulse length is not 1" | |
537 | -module dmu_imu_rds_msi_addr_decode | |
538 | -clock clk | |
539 | */ | |
540 | ||
541 | endmodule // dmu_imu_rds_msi_addr_decode |