[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_rds_msi_csr.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_rds_msi_csr.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_imu_rds_msi_csr 
	(
	clk,
	csrbus_addr,
	csrbus_wr_data,
	csrbus_wr,
	csrbus_valid,
	csrbus_mapped,
	csrbus_done,
	csrbus_read_data,
	rst_l,
	csrbus_src_bus,
	csrbus_acc_vio,
	instance_id,
	ext_addr,
	ext_wr,
	msi_mapping_v_ext_wr_data,
	msi_mapping_eqnum_ext_wr_data,
	msi_mapping_ext_select,
	msi_mapping_ext_read_data,
	msi_clear_reg_eqwr_n_ext_wr_data,
	msi_clear_reg_ext_select,
	msi_clear_reg_ext_read_data,
	int_mondo_data_0_reg_data_hw_read,
	int_mondo_data_1_reg_hw_read
	);

//====================================================
//     Polarity declarations
//====================================================
input  clk;  // Clock signal
input  [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr;  // Address bus
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
input  csrbus_wr;  // Read/Write signal
input  csrbus_valid;  // Valid address
output csrbus_mapped;  // Address is mapped
output csrbus_done;  // Operation is done
output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data;  // SW read data bus
input  rst_l;  // Reset signal
input  [1:0] csrbus_src_bus;  // Source bus
output csrbus_acc_vio;  // Violation signal
input  instance_id;  // Instance ID
output [7:0] ext_addr;  // External address bus for dcm msi
output ext_wr;  // When one, csr operation is a write. When zero, operation is a
                // read.
output msi_mapping_v_ext_wr_data;  // Provides SW write data for external
                                   // register "msi_mapping", field "v"
output [5:0] msi_mapping_eqnum_ext_wr_data;  // Provides SW write data for
                                             // external register "msi_mapping",
                                             // field "eqnum"
output msi_mapping_ext_select;  // When set, register msi_mapping is selected.
                                // This signal is a pulse.
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_mapping_ext_read_data;  // Read data
                                                                 // from the
                                                                 // external
                                                                 // bypass
                                                                 // register
output msi_clear_reg_eqwr_n_ext_wr_data;  // Provides SW write data for external
                                          // register "msi_clear_reg", field
                                          // "eqwr_n"
output msi_clear_reg_ext_select;  // When set, register msi_clear_reg is
                                  // selected. This signal is a pulse.
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_clear_reg_ext_read_data;
    // Read data from the external bypass register
output [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_INT_SLC] int_mondo_data_0_reg_data_hw_read;
    // This signal provides the current value of int_mondo_data_0_reg_data.
output [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WIDTH-1:0] int_mondo_data_1_reg_hw_read;
    // This signal provides the current value of int_mondo_data_1_reg.

//====================================================
//     Type declarations
//====================================================
wire clk;  // Clock signal
wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr;  // Address bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
wire csrbus_wr;  // Read/Write signal
wire csrbus_valid;  // Valid address
wire csrbus_mapped;  // Address is mapped
wire csrbus_done;  // Operation is done
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data;  // SW read data bus
wire rst_l;  // Reset signal
wire [1:0] csrbus_src_bus;  // Source bus
wire csrbus_acc_vio;  // Violation signal
wire instance_id;  // Instance ID
wire [7:0] ext_addr;  // External address bus for dcm msi
wire ext_wr;  // When one, csr operation is a write. When zero, operation is a
              // read.
wire msi_mapping_v_ext_wr_data;  // Provides SW write data for external register
                                 // "msi_mapping", field "v"
wire [5:0] msi_mapping_eqnum_ext_wr_data;  // Provides SW write data for
                                           // external register "msi_mapping",
                                           // field "eqnum"
wire msi_mapping_ext_select;  // When set, register msi_mapping is selected.
                              // This signal is a pulse.
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_mapping_ext_read_data;  // Read data from
                                                               // the external
                                                               // bypass
                                                               // register
wire msi_clear_reg_eqwr_n_ext_wr_data;  // Provides SW write data for external
                                        // register "msi_clear_reg", field
                                        // "eqwr_n"
wire msi_clear_reg_ext_select;  // When set, register msi_clear_reg is selected.
                                // This signal is a pulse.
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_clear_reg_ext_read_data;  // Read data
                                                                 // from the
                                                                 // external
                                                                 // bypass
                                                                 // register
wire [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_INT_SLC] int_mondo_data_0_reg_data_hw_read;
    // This signal provides the current value of int_mondo_data_0_reg_data.
wire [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WIDTH-1:0] int_mondo_data_1_reg_hw_read;
    // This signal provides the current value of int_mondo_data_1_reg.

//====================================================
//     Logic
//====================================================
wire daemon_transaction_in_progress;
wire daemon_csrbus_mapped;
wire daemon_csrbus_valid;
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp;
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data;
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire daemon_csrbus_done;
wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr;
wire daemon_csrbus_wr_tmp;
wire daemon_csrbus_wr;

//summit modcovoff -bepgnv
pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon (
    .daemon_csrbus_valid (daemon_csrbus_valid),
    .daemon_csrbus_mapped (daemon_csrbus_mapped),
    .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
    .daemon_csrbus_done (daemon_csrbus_done),
    .daemon_csrbus_addr (daemon_csrbus_addr),
    .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
    .daemon_transaction_in_progress (daemon_transaction_in_progress),
// synopsys translate_off
      .clk(clk),
      .rst_l(rst_l),
      .csrbus_read_data (csrbus_read_data),
// synopsys translate_on
    .csrbus_valid (csrbus_valid),
    .csrbus_mapped (csrbus_mapped),
    .csrbus_wr_data (csrbus_wr_data),
    .csrbus_done (csrbus_done),
    .csrbus_addr (csrbus_addr),
    .csrbus_wr (csrbus_wr)
  );
//summit modcovon -bepgnv

//====================================================================
//   Address decode
//====================================================================
wire msi_mapping_select;
wire msi_clear_reg_select;
wire int_mondo_data_0_reg_select_pulse;
wire int_mondo_data_1_reg_select_pulse;

dmu_imu_rds_msi_addr_decode dmu_imu_rds_msi_addr_decode
	(
	.clk	(clk),
	.rst_l	(rst_l),
	.daemon_csrbus_valid	(daemon_csrbus_valid),
	.daemon_csrbus_addr	(daemon_csrbus_addr),
	.csrbus_src_bus	(csrbus_src_bus),
	.daemon_csrbus_wr	(daemon_csrbus_wr_tmp),
	.daemon_csrbus_wr_out	(daemon_csrbus_wr),
	.daemon_csrbus_wr_data	(daemon_csrbus_wr_data_tmp),
	.daemon_csrbus_wr_data_out	(daemon_csrbus_wr_data),
	.daemon_csrbus_mapped	(daemon_csrbus_mapped),
	.csrbus_acc_vio	(csrbus_acc_vio),
	.daemon_transaction_in_progress	(daemon_transaction_in_progress),
	.instance_id	(instance_id),
	.daemon_csrbus_done	(daemon_csrbus_done),
	.msi_mapping_select	(msi_mapping_select),
	.msi_clear_reg_select	(msi_clear_reg_select),
	.int_mondo_data_0_reg_select_pulse	(int_mondo_data_0_reg_select_pulse),
	.int_mondo_data_1_reg_select_pulse	(int_mondo_data_1_reg_select_pulse)
	);

//====================================================================
//    OUTPUT: csrbus_read_data (pipelining)
//====================================================================
//----- connecting wires
wire stage_2_default_grp_rst_l;
wire stage_mux_only_rst_l;
wire [7:0] stage_2_default_grp_ext_addr;
wire stage_2_default_grp_daemon_csrbus_wr;
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_2_default_grp_daemon_csrbus_wr_data;
wire [7:0] stage_mux_only_ext_addr;
wire stage_mux_only_daemon_csrbus_wr;
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data;

//----- Stage: 1 / Grp: default_grp (4 inputs / 2 outputs)
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out;
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_1_out;
wire default_grp_msi_mapping_select;
wire default_grp_msi_clear_reg_select;
wire default_grp_int_mondo_data_0_reg_select_pulse;
wire default_grp_int_mondo_data_1_reg_select_pulse;

dmu_imu_rds_msi_default_grp dmu_imu_rds_msi_default_grp
	(
	.clk	(clk),
	.msi_mapping_ext_select	(msi_mapping_ext_select),
	.msi_mapping_select	(default_grp_msi_mapping_select),
	.msi_mapping_ext_read_data	(msi_mapping_ext_read_data),
	.msi_mapping_v_ext_wr_data	(msi_mapping_v_ext_wr_data),
	.msi_mapping_eqnum_ext_wr_data	(msi_mapping_eqnum_ext_wr_data),
	.msi_clear_reg_ext_select	(msi_clear_reg_ext_select),
	.msi_clear_reg_select	(default_grp_msi_clear_reg_select),
	.msi_clear_reg_ext_read_data	(msi_clear_reg_ext_read_data),
	.msi_clear_reg_eqwr_n_ext_wr_data	(msi_clear_reg_eqwr_n_ext_wr_data),
	.int_mondo_data_0_reg_data_hw_read	(int_mondo_data_0_reg_data_hw_read),
	.int_mondo_data_0_reg_select_pulse	(default_grp_int_mondo_data_0_reg_select_pulse),
	.int_mondo_data_1_reg_hw_read	(int_mondo_data_1_reg_hw_read),
	.int_mondo_data_1_reg_select_pulse	(default_grp_int_mondo_data_1_reg_select_pulse),
	.rst_l	(stage_2_default_grp_rst_l),
	.daemon_csrbus_wr_in	(stage_2_default_grp_daemon_csrbus_wr),
	.daemon_csrbus_wr_out	(ext_wr),
	.daemon_csrbus_wr_data_in	(stage_2_default_grp_daemon_csrbus_wr_data),
	.ext_addr_in	(stage_2_default_grp_ext_addr[7:0]),
	.ext_addr_out	(ext_addr),
	.read_data_0_out	(default_grp_read_data_0_out),
	.read_data_1_out	(default_grp_read_data_1_out)
	);

//----- Stage: 2 / Grp: stage_2_default_grp (2 inputs / 1 outputs)
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_2_default_grp_read_data_0_out;
wire stage_2_default_grp_msi_mapping_select;
wire stage_2_default_grp_msi_clear_reg_select;
wire stage_2_default_grp_int_mondo_data_0_reg_select_pulse;
wire stage_2_default_grp_int_mondo_data_1_reg_select_pulse;

dmu_imu_rds_msi_stage_2_default_grp dmu_imu_rds_msi_stage_2_default_grp
	(
	.clk	(clk),
	.read_data_0	(default_grp_read_data_0_out),
	.read_data_1	(default_grp_read_data_1_out),
	.msi_mapping_select	(stage_2_default_grp_msi_mapping_select),
	.msi_mapping_select_out	(default_grp_msi_mapping_select),
	.msi_clear_reg_select	(stage_2_default_grp_msi_clear_reg_select),
	.msi_clear_reg_select_out	(default_grp_msi_clear_reg_select),
	.int_mondo_data_0_reg_select_pulse	(stage_2_default_grp_int_mondo_data_0_reg_select_pulse),
	.int_mondo_data_0_reg_select_pulse_out	(default_grp_int_mondo_data_0_reg_select_pulse),
	.int_mondo_data_1_reg_select_pulse	(stage_2_default_grp_int_mondo_data_1_reg_select_pulse),
	.int_mondo_data_1_reg_select_pulse_out	(default_grp_int_mondo_data_1_reg_select_pulse),
	.rst_l	(stage_mux_only_rst_l),
	.rst_l_out	(stage_2_default_grp_rst_l),
	.daemon_csrbus_wr_in	(stage_mux_only_daemon_csrbus_wr),
	.daemon_csrbus_wr_out	(stage_2_default_grp_daemon_csrbus_wr),
	.daemon_csrbus_wr_data_in	(stage_mux_only_daemon_csrbus_wr_data),
	.daemon_csrbus_wr_data_out	(stage_2_default_grp_daemon_csrbus_wr_data),
	.ext_addr_in	(stage_mux_only_ext_addr[7:0]),
	.ext_addr_out	(stage_2_default_grp_ext_addr),
	.read_data_0_out	(stage_2_default_grp_read_data_0_out)
	);

//----- Stage: 3 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only)
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out;

dmu_imu_rds_msi_stage_mux_only dmu_imu_rds_msi_stage_mux_only
	(
	.clk	(clk),
	.read_data_0	(stage_2_default_grp_read_data_0_out),
	.msi_mapping_select	(msi_mapping_select),
	.msi_mapping_select_out	(stage_2_default_grp_msi_mapping_select),
	.msi_clear_reg_select	(msi_clear_reg_select),
	.msi_clear_reg_select_out	(stage_2_default_grp_msi_clear_reg_select),
	.int_mondo_data_0_reg_select_pulse	(int_mondo_data_0_reg_select_pulse),
	.int_mondo_data_0_reg_select_pulse_out	(stage_2_default_grp_int_mondo_data_0_reg_select_pulse),
	.int_mondo_data_1_reg_select_pulse	(int_mondo_data_1_reg_select_pulse),
	.int_mondo_data_1_reg_select_pulse_out	(stage_2_default_grp_int_mondo_data_1_reg_select_pulse),
	.daemon_csrbus_wr_in	(daemon_csrbus_wr),
	.daemon_csrbus_wr_out	(stage_mux_only_daemon_csrbus_wr),
	.daemon_csrbus_wr_data_in	(daemon_csrbus_wr_data),
	.daemon_csrbus_wr_data_out	(stage_mux_only_daemon_csrbus_wr_data),
	.ext_addr_in	(daemon_csrbus_addr[7:0]),
	.ext_addr_out	(stage_mux_only_ext_addr),
	.read_data_0_out	(stage_mux_only_read_data_0_out),
	.rst_l	(rst_l),
	.rst_l_out	(stage_mux_only_rst_l)
	);

//----- OUTPUT: csrbus_read_data
assign csrbus_read_data = stage_mux_only_read_data_0_out;

endmodule // dmu_imu_rds_msi_csr
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_imu_rds_msi_csr.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_imu_rds_msi_csr
	36	(
	37	clk,
	38	csrbus_addr,
	39	csrbus_wr_data,
	40	csrbus_wr,
	41	csrbus_valid,
	42	csrbus_mapped,
	43	csrbus_done,
	44	csrbus_read_data,
	45	rst_l,
	46	csrbus_src_bus,
	47	csrbus_acc_vio,
	48	instance_id,
	49	ext_addr,
	50	ext_wr,
	51	msi_mapping_v_ext_wr_data,
	52	msi_mapping_eqnum_ext_wr_data,
	53	msi_mapping_ext_select,
	54	msi_mapping_ext_read_data,
	55	msi_clear_reg_eqwr_n_ext_wr_data,
	56	msi_clear_reg_ext_select,
	57	msi_clear_reg_ext_read_data,
	58	int_mondo_data_0_reg_data_hw_read,
	59	int_mondo_data_1_reg_hw_read
	60	);
	61
	62	//====================================================
	63	// Polarity declarations
	64	//====================================================
65	input clk; // Clock signal
66	input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
67	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
68	input csrbus_wr; // Read/Write signal
69	input csrbus_valid; // Valid address
70	output csrbus_mapped; // Address is mapped
71	output csrbus_done; // Operation is done
72	output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
73	input rst_l; // Reset signal
74	input [1:0] csrbus_src_bus; // Source bus
75	output csrbus_acc_vio; // Violation signal
76	input instance_id; // Instance ID
77	output [7:0] ext_addr; // External address bus for dcm msi
78	output ext_wr; // When one, csr operation is a write. When zero, operation is a
79	// read.
80	output msi_mapping_v_ext_wr_data; // Provides SW write data for external
81	// register "msi_mapping", field "v"
82	output [5:0] msi_mapping_eqnum_ext_wr_data; // Provides SW write data for
83	// external register "msi_mapping",
84	// field "eqnum"
85	output msi_mapping_ext_select; // When set, register msi_mapping is selected.
86	// This signal is a pulse.
87	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_mapping_ext_read_data; // Read data
88	// from the
89	// external
90	// bypass
91	// register
92	output msi_clear_reg_eqwr_n_ext_wr_data; // Provides SW write data for external
93	// register "msi_clear_reg", field
94	// "eqwr_n"
95	output msi_clear_reg_ext_select; // When set, register msi_clear_reg is
96	// selected. This signal is a pulse.
97	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_clear_reg_ext_read_data;
98	// Read data from the external bypass register
99	output [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_INT_SLC] int_mondo_data_0_reg_data_hw_read;
100	// This signal provides the current value of int_mondo_data_0_reg_data.
101	output [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WIDTH-1:0] int_mondo_data_1_reg_hw_read;
102	// This signal provides the current value of int_mondo_data_1_reg.
103
104	//====================================================
105	// Type declarations
106	//====================================================
107	wire clk; // Clock signal
108	wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
109	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
110	wire csrbus_wr; // Read/Write signal
111	wire csrbus_valid; // Valid address
112	wire csrbus_mapped; // Address is mapped
113	wire csrbus_done; // Operation is done
114	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
115	wire rst_l; // Reset signal
116	wire [1:0] csrbus_src_bus; // Source bus
117	wire csrbus_acc_vio; // Violation signal
118	wire instance_id; // Instance ID
119	wire [7:0] ext_addr; // External address bus for dcm msi
120	wire ext_wr; // When one, csr operation is a write. When zero, operation is a
121	// read.
122	wire msi_mapping_v_ext_wr_data; // Provides SW write data for external register
123	// "msi_mapping", field "v"
124	wire [5:0] msi_mapping_eqnum_ext_wr_data; // Provides SW write data for
125	// external register "msi_mapping",
126	// field "eqnum"
127	wire msi_mapping_ext_select; // When set, register msi_mapping is selected.
128	// This signal is a pulse.
129	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_mapping_ext_read_data; // Read data from
130	// the external
131	// bypass
132	// register
133	wire msi_clear_reg_eqwr_n_ext_wr_data; // Provides SW write data for external
134	// register "msi_clear_reg", field
135	// "eqwr_n"
136	wire msi_clear_reg_ext_select; // When set, register msi_clear_reg is selected.
137	// This signal is a pulse.
138	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] msi_clear_reg_ext_read_data; // Read data
139	// from the
140	// external
141	// bypass
142	// register
143	wire [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_INT_SLC] int_mondo_data_0_reg_data_hw_read;
144	// This signal provides the current value of int_mondo_data_0_reg_data.
145	wire [`FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WIDTH-1:0] int_mondo_data_1_reg_hw_read;
146	// This signal provides the current value of int_mondo_data_1_reg.
147
148	//====================================================
149	// Logic
150	//====================================================
151	wire daemon_transaction_in_progress;
152	wire daemon_csrbus_mapped;
153	wire daemon_csrbus_valid;
154	// vlint flag_dangling_net_within_module off
155	// vlint flag_net_has_no_load off
156	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp;
157	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data;
158	// vlint flag_dangling_net_within_module on
159	// vlint flag_net_has_no_load on
160	wire daemon_csrbus_done;
161	wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr;
162	wire daemon_csrbus_wr_tmp;
163	wire daemon_csrbus_wr;
164
165	//summit modcovoff -bepgnv
166	pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon (
167	.daemon_csrbus_valid (daemon_csrbus_valid),
168	.daemon_csrbus_mapped (daemon_csrbus_mapped),
169	.daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
170	.daemon_csrbus_done (daemon_csrbus_done),
171	.daemon_csrbus_addr (daemon_csrbus_addr),
172	.daemon_csrbus_wr (daemon_csrbus_wr_tmp),
173	.daemon_transaction_in_progress (daemon_transaction_in_progress),
174	// synopsys translate_off
175	.clk(clk),
176	.rst_l(rst_l),
177	.csrbus_read_data (csrbus_read_data),
178	// synopsys translate_on
179	.csrbus_valid (csrbus_valid),
180	.csrbus_mapped (csrbus_mapped),
181	.csrbus_wr_data (csrbus_wr_data),
182	.csrbus_done (csrbus_done),
183	.csrbus_addr (csrbus_addr),
184	.csrbus_wr (csrbus_wr)
185	);
186	//summit modcovon -bepgnv
187
188	//====================================================================
189	// Address decode
190	//====================================================================
191	wire msi_mapping_select;
192	wire msi_clear_reg_select;
193	wire int_mondo_data_0_reg_select_pulse;
194	wire int_mondo_data_1_reg_select_pulse;
195
196	dmu_imu_rds_msi_addr_decode dmu_imu_rds_msi_addr_decode
197	(
198	.clk (clk),
199	.rst_l (rst_l),
200	.daemon_csrbus_valid (daemon_csrbus_valid),
201	.daemon_csrbus_addr (daemon_csrbus_addr),
202	.csrbus_src_bus (csrbus_src_bus),
203	.daemon_csrbus_wr (daemon_csrbus_wr_tmp),
204	.daemon_csrbus_wr_out (daemon_csrbus_wr),
205	.daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
206	.daemon_csrbus_wr_data_out (daemon_csrbus_wr_data),
207	.daemon_csrbus_mapped (daemon_csrbus_mapped),
208	.csrbus_acc_vio (csrbus_acc_vio),
209	.daemon_transaction_in_progress (daemon_transaction_in_progress),
210	.instance_id (instance_id),
211	.daemon_csrbus_done (daemon_csrbus_done),
212	.msi_mapping_select (msi_mapping_select),
213	.msi_clear_reg_select (msi_clear_reg_select),
214	.int_mondo_data_0_reg_select_pulse (int_mondo_data_0_reg_select_pulse),
215	.int_mondo_data_1_reg_select_pulse (int_mondo_data_1_reg_select_pulse)
216	);
217
218	//====================================================================
219	// OUTPUT: csrbus_read_data (pipelining)
220	//====================================================================
221	//----- connecting wires
222	wire stage_2_default_grp_rst_l;
223	wire stage_mux_only_rst_l;
224	wire [7:0] stage_2_default_grp_ext_addr;
225	wire stage_2_default_grp_daemon_csrbus_wr;
226	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_2_default_grp_daemon_csrbus_wr_data;
227	wire [7:0] stage_mux_only_ext_addr;
228	wire stage_mux_only_daemon_csrbus_wr;
229	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data;
230
231	//----- Stage: 1 / Grp: default_grp (4 inputs / 2 outputs)
232	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out;
233	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_1_out;
234	wire default_grp_msi_mapping_select;
235	wire default_grp_msi_clear_reg_select;
236	wire default_grp_int_mondo_data_0_reg_select_pulse;
237	wire default_grp_int_mondo_data_1_reg_select_pulse;
238
239	dmu_imu_rds_msi_default_grp dmu_imu_rds_msi_default_grp
240	(
241	.clk (clk),
242	.msi_mapping_ext_select (msi_mapping_ext_select),
243	.msi_mapping_select (default_grp_msi_mapping_select),
244	.msi_mapping_ext_read_data (msi_mapping_ext_read_data),
245	.msi_mapping_v_ext_wr_data (msi_mapping_v_ext_wr_data),
246	.msi_mapping_eqnum_ext_wr_data (msi_mapping_eqnum_ext_wr_data),
247	.msi_clear_reg_ext_select (msi_clear_reg_ext_select),
248	.msi_clear_reg_select (default_grp_msi_clear_reg_select),
249	.msi_clear_reg_ext_read_data (msi_clear_reg_ext_read_data),
250	.msi_clear_reg_eqwr_n_ext_wr_data (msi_clear_reg_eqwr_n_ext_wr_data),
251	.int_mondo_data_0_reg_data_hw_read (int_mondo_data_0_reg_data_hw_read),
252	.int_mondo_data_0_reg_select_pulse (default_grp_int_mondo_data_0_reg_select_pulse),
253	.int_mondo_data_1_reg_hw_read (int_mondo_data_1_reg_hw_read),
254	.int_mondo_data_1_reg_select_pulse (default_grp_int_mondo_data_1_reg_select_pulse),
255	.rst_l (stage_2_default_grp_rst_l),
256	.daemon_csrbus_wr_in (stage_2_default_grp_daemon_csrbus_wr),
257	.daemon_csrbus_wr_out (ext_wr),
258	.daemon_csrbus_wr_data_in (stage_2_default_grp_daemon_csrbus_wr_data),
259	.ext_addr_in (stage_2_default_grp_ext_addr[7:0]),
260	.ext_addr_out (ext_addr),
261	.read_data_0_out (default_grp_read_data_0_out),
262	.read_data_1_out (default_grp_read_data_1_out)
263	);
264
265	//----- Stage: 2 / Grp: stage_2_default_grp (2 inputs / 1 outputs)
266	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_2_default_grp_read_data_0_out;
267	wire stage_2_default_grp_msi_mapping_select;
268	wire stage_2_default_grp_msi_clear_reg_select;
269	wire stage_2_default_grp_int_mondo_data_0_reg_select_pulse;
270	wire stage_2_default_grp_int_mondo_data_1_reg_select_pulse;
271
272	dmu_imu_rds_msi_stage_2_default_grp dmu_imu_rds_msi_stage_2_default_grp
273	(
274	.clk (clk),
275	.read_data_0 (default_grp_read_data_0_out),
276	.read_data_1 (default_grp_read_data_1_out),
277	.msi_mapping_select (stage_2_default_grp_msi_mapping_select),
278	.msi_mapping_select_out (default_grp_msi_mapping_select),
279	.msi_clear_reg_select (stage_2_default_grp_msi_clear_reg_select),
280	.msi_clear_reg_select_out (default_grp_msi_clear_reg_select),
281	.int_mondo_data_0_reg_select_pulse (stage_2_default_grp_int_mondo_data_0_reg_select_pulse),
282	.int_mondo_data_0_reg_select_pulse_out (default_grp_int_mondo_data_0_reg_select_pulse),
283	.int_mondo_data_1_reg_select_pulse (stage_2_default_grp_int_mondo_data_1_reg_select_pulse),
284	.int_mondo_data_1_reg_select_pulse_out (default_grp_int_mondo_data_1_reg_select_pulse),
285	.rst_l (stage_mux_only_rst_l),
286	.rst_l_out (stage_2_default_grp_rst_l),
287	.daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr),
288	.daemon_csrbus_wr_out (stage_2_default_grp_daemon_csrbus_wr),
289	.daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data),
290	.daemon_csrbus_wr_data_out (stage_2_default_grp_daemon_csrbus_wr_data),
291	.ext_addr_in (stage_mux_only_ext_addr[7:0]),
292	.ext_addr_out (stage_2_default_grp_ext_addr),
293	.read_data_0_out (stage_2_default_grp_read_data_0_out)
294	);
295
296	//----- Stage: 3 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only)
297	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out;
298
299	dmu_imu_rds_msi_stage_mux_only dmu_imu_rds_msi_stage_mux_only
300	(
301	.clk (clk),
302	.read_data_0 (stage_2_default_grp_read_data_0_out),
303	.msi_mapping_select (msi_mapping_select),
304	.msi_mapping_select_out (stage_2_default_grp_msi_mapping_select),
305	.msi_clear_reg_select (msi_clear_reg_select),
306	.msi_clear_reg_select_out (stage_2_default_grp_msi_clear_reg_select),
307	.int_mondo_data_0_reg_select_pulse (int_mondo_data_0_reg_select_pulse),
308	.int_mondo_data_0_reg_select_pulse_out (stage_2_default_grp_int_mondo_data_0_reg_select_pulse),
309	.int_mondo_data_1_reg_select_pulse (int_mondo_data_1_reg_select_pulse),
310	.int_mondo_data_1_reg_select_pulse_out (stage_2_default_grp_int_mondo_data_1_reg_select_pulse),
311	.daemon_csrbus_wr_in (daemon_csrbus_wr),
312	.daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr),
313	.daemon_csrbus_wr_data_in (daemon_csrbus_wr_data),
314	.daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data),
315	.ext_addr_in (daemon_csrbus_addr[7:0]),
316	.ext_addr_out (stage_mux_only_ext_addr),
317	.read_data_0_out (stage_mux_only_read_data_0_out),
318	.rst_l (rst_l),
319	.rst_l_out (stage_mux_only_rst_l)
320	);
321
322	//----- OUTPUT: csrbus_read_data
323	assign csrbus_read_data = stage_mux_only_read_data_0_out;
324
325	endmodule // dmu_imu_rds_msi_csr