Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_rds_msi_stage_2_default_grp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_rds_msi_stage_2_default_grp | |
36 | ( | |
37 | clk, | |
38 | read_data_0, | |
39 | read_data_1, | |
40 | msi_mapping_select, | |
41 | msi_mapping_select_out, | |
42 | msi_clear_reg_select, | |
43 | msi_clear_reg_select_out, | |
44 | int_mondo_data_0_reg_select_pulse, | |
45 | int_mondo_data_0_reg_select_pulse_out, | |
46 | int_mondo_data_1_reg_select_pulse, | |
47 | int_mondo_data_1_reg_select_pulse_out, | |
48 | rst_l, | |
49 | rst_l_out, | |
50 | daemon_csrbus_wr_in, | |
51 | daemon_csrbus_wr_out, | |
52 | daemon_csrbus_wr_data_in, | |
53 | daemon_csrbus_wr_data_out, | |
54 | ext_addr_in, | |
55 | ext_addr_out, | |
56 | read_data_0_out | |
57 | ); | |
58 | ||
59 | //==================================================== | |
60 | // Polarity declarations | |
61 | //==================================================== | |
62 | input clk; // Clock signal | |
63 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
64 | input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data | |
65 | input msi_mapping_select; // select | |
66 | output msi_mapping_select_out; // select | |
67 | input msi_clear_reg_select; // select | |
68 | output msi_clear_reg_select_out; // select | |
69 | input int_mondo_data_0_reg_select_pulse; // select | |
70 | output int_mondo_data_0_reg_select_pulse_out; // select | |
71 | input int_mondo_data_1_reg_select_pulse; // select | |
72 | output int_mondo_data_1_reg_select_pulse_out; // select | |
73 | input rst_l; // HW reset | |
74 | output rst_l_out; // HW reset | |
75 | input daemon_csrbus_wr_in; // csrbus_wr | |
76 | output daemon_csrbus_wr_out; // csrbus_wr | |
77 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
78 | output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write | |
79 | // data | |
80 | input [7:0] ext_addr_in; // Ext addr | |
81 | output [7:0] ext_addr_out; // Ext addr | |
82 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
83 | ||
84 | //==================================================== | |
85 | // Type declarations | |
86 | //==================================================== | |
87 | wire clk; // Clock signal | |
88 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data | |
89 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1; // Read Data | |
90 | wire msi_mapping_select; // select | |
91 | reg msi_mapping_select_out; // select | |
92 | wire msi_clear_reg_select; // select | |
93 | reg msi_clear_reg_select_out; // select | |
94 | wire int_mondo_data_0_reg_select_pulse; // select | |
95 | reg int_mondo_data_0_reg_select_pulse_out; // select | |
96 | wire int_mondo_data_1_reg_select_pulse; // select | |
97 | reg int_mondo_data_1_reg_select_pulse_out; // select | |
98 | wire rst_l; // HW reset | |
99 | wire rst_l_out; // HW reset | |
100 | wire daemon_csrbus_wr_in; // csrbus_wr | |
101 | wire daemon_csrbus_wr_out; // csrbus_wr | |
102 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
103 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data | |
104 | wire [7:0] ext_addr_in; // Ext addr | |
105 | wire [7:0] ext_addr_out; // Ext addr | |
106 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
107 | ||
108 | ||
109 | //==================================================== | |
110 | // Pipelining | |
111 | //==================================================== | |
112 | always @(posedge clk) | |
113 | begin | |
114 | if(~rst_l) | |
115 | begin | |
116 | msi_mapping_select_out <= 1'b0; | |
117 | msi_clear_reg_select_out <= 1'b0; | |
118 | int_mondo_data_0_reg_select_pulse_out <= 1'b0; | |
119 | int_mondo_data_1_reg_select_pulse_out <= 1'b0; | |
120 | end | |
121 | else | |
122 | begin | |
123 | msi_mapping_select_out <= msi_mapping_select; | |
124 | msi_clear_reg_select_out <= msi_clear_reg_select; | |
125 | int_mondo_data_0_reg_select_pulse_out <= int_mondo_data_0_reg_select_pulse; | |
126 | int_mondo_data_1_reg_select_pulse_out <= int_mondo_data_1_reg_select_pulse; | |
127 | end | |
128 | end | |
129 | ||
130 | ||
131 | //==================================================== | |
132 | // Assignments only | |
133 | //==================================================== | |
134 | assign daemon_csrbus_wr_out = daemon_csrbus_wr_in; | |
135 | assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in; | |
136 | assign ext_addr_out = ext_addr_in; | |
137 | assign rst_l_out = rst_l; | |
138 | ||
139 | //===================================================== | |
140 | // OUTPUT: read_data_out | |
141 | //===================================================== | |
142 | dmu_imu_rds_msi_csrpipe_3 dmu_imu_rds_msi_csrpipe_3_inst_1 | |
143 | ( | |
144 | .clk (clk), | |
145 | .rst_l (rst_l), | |
146 | .reg_in (1'b0), | |
147 | .reg_out (1'b1), | |
148 | .data0 (read_data_0), | |
149 | .sel0 (1'b1), | |
150 | .data1 (read_data_1), | |
151 | .sel1 (1'b1), | |
152 | .data2 (64'b0), | |
153 | .sel2 (1'b1), | |
154 | .out (read_data_0_out) | |
155 | ); | |
156 | ||
157 | endmodule // dmu_imu_rds_msi_stage_2_default_grp |