Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_rss.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_rss.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
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// 
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// ========== Copyright Header End ============================================
module dmu_imu_rss (
		
		// Clock and Reset 
		
		clk,
		rst_l,
		
		// Inputs from RMU block

		rm2im_rply,
		rm2im_rply_enq,
		
		// Outputs to GCS state Sub-block 

		rss2gcs_rply,
		rss2gcs_id, 
		rss2gcs_valid, 
		
		
		// Debug Ports 
		
		rss2dbg_dbg_a,
		rss2dbg_dbg_b, 
		
		//Perf Counters

		rss2ics_perf_mondo_nacks  

		
		);
		
				
//############################################################################
//				PORT DECLARATIONS
//############################################################################


  //------------------------------------------------------------------------
  //  Clock and Reset Signals      
  //------------------------------------------------------------------------
  input 				clk;
  input					rst_l; 
  
  //------------------------------------------------------------------------
  //  Input Signals from RRM Block  Signals      
  //------------------------------------------------------------------------
  
  input 				rm2im_rply_enq; 	// Enqueue Signal from RRM
  input	[`FIRE_DLC_MRR_REC_WDTH-1:0]	rm2im_rply; 		// 1:0 - group id 2: ACK/NACK 0 = NACK 1= ACK
    
  //-----------------------------------------------------
  // Interface for Group Controller Arbiter
  //-----------------------------------------------------
  
  output				rss2gcs_rply; 		// Reply type from RSS ack =1 nack =0
  output [`FIRE_DLC_MRR_TAG_WDTH-1:0]	rss2gcs_id; 		// Group controller ID for response
  output 				rss2gcs_valid; 		// Valid signal to validate respose
  
  //------------------------------------------------------------------------
  // Debug Ports   
  //------------------------------------------------------------------------
  output   [`FIRE_DEBUG_WDTH-1:0]	rss2dbg_dbg_a;
  output   [`FIRE_DEBUG_WDTH-1:0]	rss2dbg_dbg_b;
 
  //------------------------------------------------------------------------
  // Perf Counters   
  //------------------------------------------------------------------------
  output					rss2ics_perf_mondo_nacks;

//############################################################################
//				SIGNAL DECLARATIONS
//############################################################################
  //**************************************************
  // Wires 
  //**************************************************
 
  wire   [`FIRE_DEBUG_WDTH-1:0] 	n_dbg_a;
  wire   [`FIRE_DEBUG_WDTH-1:0] 	n_dbg_b;

  
  //**************************************************
  // Registers that Are Flops 
  //**************************************************
  reg   [`FIRE_DEBUG_WDTH-1:0] 		dbg_a;
  reg   [`FIRE_DEBUG_WDTH-1:0] 		dbg_b;

  reg					rss2gcs_rply; 		// Reply type from RSS ack =1 nack =0
  reg [`FIRE_DLC_MRR_TAG_WDTH-1:0]	rss2gcs_id; 		// Group controller ID for response
  reg 					rss2gcs_valid; 		// Valid signal to validate respose

//############################################################################
//		    		ZERO IN CHECKERS  
//############################################################################    
  
    

//############################################################################
//		    		SEQUENTIAL LOGIC
//############################################################################   

  //**************************************************
  // Register the inputs from, the RRM and send them
  // The the group controller sub-block 
  //**************************************************


always @ (posedge clk)
  if (!rst_l)
    begin
      rss2gcs_valid <= 1'b0;
      rss2gcs_rply  <= 1'b0;
      rss2gcs_id    <= 2'b0; 
    end
  else
    begin
      rss2gcs_valid <= rm2im_rply_enq;
      rss2gcs_rply  <= rm2im_rply[`FIRE_DLC_MRR_ACK_MSB];
      rss2gcs_id    <= rm2im_rply[`FIRE_DLC_MRR_TAG_MSB:`FIRE_DLC_MRR_TAG_LSB]; 
    end



//-----------------------------------------------------
//  Debug Ports  
//-----------------------------------------------------  

assign n_dbg_a = {4'h0, rss2gcs_valid, rss2gcs_rply, rss2gcs_id};
assign n_dbg_b = {4'h0, rss2gcs_valid, rss2gcs_rply, rss2gcs_id};


always @ (posedge clk)
     begin 
      if (!rst_l) begin
      dbg_a <= 8'b0;
      dbg_b <= 8'b0;
      end
      else begin
      dbg_a <= n_dbg_a;
      dbg_b <= n_dbg_b;
     end   
     end   
   

assign rss2dbg_dbg_a = dbg_a; 
assign rss2dbg_dbg_b = dbg_b; 


//-----------------------------------------------------
//  Performace Counters 
//----------------------------------------------------- 

assign rss2ics_perf_mondo_nacks  = rm2im_rply_enq & ~rm2im_rply[`FIRE_DLC_MRR_ACK_MSB]; 
 
endmodule