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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mb0.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mb0 ( | |
36 | dmu_mb0_run, | |
37 | dmu_mb0_addr, | |
38 | dmu_mb0_wdata, | |
39 | dmu_mb0_diu_wr_en, | |
40 | dmu_mb0_diu_rd_en, | |
41 | dmu_mb0_tdb_wr_en, | |
42 | dmu_mb0_tdb_rd_en, | |
43 | dmu_mb0_dou_dma_data_wr_en, | |
44 | dmu_mb0_dou_dma_data_rd_en, | |
45 | dmu_mb0_dou_pio_data_wr_en, | |
46 | dmu_mb0_dou_pio_data_rd_en, | |
47 | dmu_mb0_dev_wr_en, | |
48 | dmu_mb0_dev_rd_en, | |
49 | dmu_mb0_tsb_wr_en, | |
50 | dmu_mb0_tsb_rd_en, | |
51 | dmu_mb0_done, | |
52 | dmu_mb0_fail, | |
53 | scan_out, | |
54 | l1clk, | |
55 | scan_in, | |
56 | tcu_aclk, | |
57 | tcu_bclk, | |
58 | rst_, | |
59 | tcu_dmu_mb0_start, | |
60 | dmu_mb0_bisi_mode, | |
61 | dmu_mb0_user_mode, | |
62 | dmu_diu_read_data, | |
63 | dmu_tdb_read_data, | |
64 | dmu_dou_dma_read_data, | |
65 | dmu_dou_pio_read_data, | |
66 | dev_tsb_read_data); | |
67 | wire siclk; | |
68 | wire soclk; | |
69 | wire reset; | |
70 | wire config_reg_scanin; | |
71 | wire config_reg_scanout; | |
72 | wire [8:0] config_in; | |
73 | wire [8:0] config_out; | |
74 | wire start_transition; | |
75 | wire reset_engine; | |
76 | wire mbist_user_loop_mode; | |
77 | wire mbist_done; | |
78 | wire run; | |
79 | wire bisi; | |
80 | wire user_mode; | |
81 | wire user_data_mode; | |
82 | wire user_addr_mode; | |
83 | wire user_loop_mode; | |
84 | wire user_cmpsel_hold; | |
85 | wire ten_n_mode; | |
86 | wire mbist_user_data_mode; | |
87 | wire mbist_user_addr_mode; | |
88 | wire mbist_user_cmpsel_hold; | |
89 | wire mbist_ten_n_mode; | |
90 | wire user_data_reg_scanin; | |
91 | wire user_data_reg_scanout; | |
92 | wire [7:0] user_data_in; | |
93 | wire [7:0] user_data_out; | |
94 | wire user_start_addr_reg_scanin; | |
95 | wire user_start_addr_reg_scanout; | |
96 | wire [8:0] user_start_addr_in; | |
97 | wire [8:0] user_start_addr; | |
98 | wire user_stop_addr_reg_scanin; | |
99 | wire user_stop_addr_reg_scanout; | |
100 | wire [8:0] user_stop_addr_in; | |
101 | wire [8:0] user_stop_addr; | |
102 | wire user_incr_addr_reg_scanin; | |
103 | wire user_incr_addr_reg_scanout; | |
104 | wire [8:0] user_incr_addr_in; | |
105 | wire [8:0] user_incr_addr; | |
106 | wire user_array_sel_reg_scanin; | |
107 | wire user_array_sel_reg_scanout; | |
108 | wire [2:0] user_array_sel_in; | |
109 | wire [2:0] user_array_sel; | |
110 | wire user_cmpsel_reg_scanin; | |
111 | wire user_cmpsel_reg_scanout; | |
112 | wire [1:0] user_cmpsel_in; | |
113 | wire [1:0] user_cmpsel; | |
114 | wire user_bisi_wr_reg_scanin; | |
115 | wire user_bisi_wr_reg_scanout; | |
116 | wire user_bisi_wr_mode_in; | |
117 | wire user_bisi_wr_mode; | |
118 | wire user_bisi_rd_reg_scanin; | |
119 | wire user_bisi_rd_reg_scanout; | |
120 | wire user_bisi_rd_mode_in; | |
121 | wire user_bisi_rd_mode; | |
122 | wire mbist_user_bisi_wr_mode; | |
123 | wire mbist_user_bisi_wr_rd_mode; | |
124 | wire start_transition_reg_scanin; | |
125 | wire start_transition_reg_scanout; | |
126 | wire start_transition_piped; | |
127 | wire run_reg_scanin; | |
128 | wire run_reg_scanout; | |
129 | wire run1_reg_scanin; | |
130 | wire run1_reg_scanout; | |
131 | wire run1_in; | |
132 | wire run1_out; | |
133 | wire run2_reg_scanin; | |
134 | wire run2_reg_scanout; | |
135 | wire run2_in; | |
136 | wire run2_out; | |
137 | wire run_piped3; | |
138 | wire msb; | |
139 | wire addr_reg_scanin; | |
140 | wire addr_reg_scanout; | |
141 | wire [8:0] mbist_address; | |
142 | wire wdata_reg_scanin; | |
143 | wire wdata_reg_scanout; | |
144 | wire [7:0] mbist_wdata; | |
145 | wire wr_rd_en_reg_scanin; | |
146 | wire wr_rd_en_reg_scanout; | |
147 | wire diu_wr_en; | |
148 | wire diu_rd_en; | |
149 | wire tdb_wr_en; | |
150 | wire tdb_rd_en; | |
151 | wire dma_data_wr_en; | |
152 | wire dma_data_rd_en; | |
153 | wire pio_data_wr_en; | |
154 | wire pio_data_rd_en; | |
155 | wire dev_wr_en; | |
156 | wire dev_rd_en; | |
157 | wire tsb_wr_en; | |
158 | wire tsb_rd_en; | |
159 | wire done_reg_scanin; | |
160 | wire done_reg_scanout; | |
161 | wire mbist_fail_reg_scanin; | |
162 | wire mbist_fail_reg_scanout; | |
163 | wire fail; | |
164 | wire diu_sel_piped2; | |
165 | wire tdb_sel_piped2; | |
166 | wire dma_data_sel_piped2; | |
167 | wire pio_data_sel_piped2; | |
168 | wire dev_sel_piped2; | |
169 | wire tsb_sel_piped2; | |
170 | wire [1:0] cmpsel_piped2; | |
171 | wire res_read_data_reg_scanin; | |
172 | wire res_read_data_reg_scanout; | |
173 | wire [39:0] res_read_data_piped; | |
174 | wire control_reg_scanin; | |
175 | wire control_reg_scanout; | |
176 | wire [25:0] control_in; | |
177 | wire [25:0] control_out; | |
178 | wire bisi_wr_rd; | |
179 | wire [2:0] array_sel; | |
180 | wire [1:0] cmpsel; | |
181 | wire tdb_sel; | |
182 | wire dev_sel; | |
183 | wire tsb_sel; | |
184 | wire [1:0] data_control; | |
185 | wire address_mix; | |
186 | wire [3:0] march_element; | |
187 | wire [8:0] array_address; | |
188 | wire upaddress_march; | |
189 | wire [2:0] read_write_control; | |
190 | wire five_cycle_march; | |
191 | wire one_cycle_march; | |
192 | wire increment_addr; | |
193 | wire [8:0] start_addr; | |
194 | wire [8:0] next_array_address; | |
195 | wire next_upaddr_march; | |
196 | wire next_downaddr_march; | |
197 | wire [8:0] stop_addr; | |
198 | wire [9:0] overflow_addr; | |
199 | wire diu_sel; | |
200 | wire dma_data_sel; | |
201 | wire pio_data_sel; | |
202 | wire [8:0] incr_addr; | |
203 | wire overflow; | |
204 | wire [9:0] compare_addr; | |
205 | wire [8:0] add; | |
206 | wire [8:0] adj_address; | |
207 | wire increment_march_elem; | |
208 | wire [2:0] next_array_sel; | |
209 | wire [1:0] next_cmpsel; | |
210 | wire [1:0] next_data_control; | |
211 | wire next_address_mix; | |
212 | wire [3:0] next_march_element; | |
213 | wire array_write; | |
214 | wire array_read; | |
215 | wire true_data; | |
216 | wire [7:0] data_pattern; | |
217 | wire done_counter_reg_scanin; | |
218 | wire done_counter_reg_scanout; | |
219 | wire [2:0] done_counter_in; | |
220 | wire [2:0] done_counter_out; | |
221 | wire data_pipe_reg1_scanin; | |
222 | wire data_pipe_reg1_scanout; | |
223 | wire [7:0] data_pipe_reg1_in; | |
224 | wire [7:0] data_pipe_out1; | |
225 | wire data_pipe_reg2_scanin; | |
226 | wire data_pipe_reg2_scanout; | |
227 | wire [7:0] data_pipe_reg2_in; | |
228 | wire [7:0] data_pipe_out2; | |
229 | wire [7:0] dmu_mb0_piped_data; | |
230 | wire array_sel_pipe_reg1_scanin; | |
231 | wire array_sel_pipe_reg1_scanout; | |
232 | wire [2:0] array_sel_pipe_reg1_in; | |
233 | wire [2:0] array_sel_piped; | |
234 | wire array_sel_pipe_reg2_scanin; | |
235 | wire array_sel_pipe_reg2_scanout; | |
236 | wire [2:0] array_sel_pipe_reg2_in; | |
237 | wire [2:0] array_sel_piped2; | |
238 | wire diu_ren_pipe_reg1_scanin; | |
239 | wire diu_ren_pipe_reg1_scanout; | |
240 | wire diu_ren_pipe_reg1_in; | |
241 | wire diu_rd_en_piped; | |
242 | wire diu_ren_pipe_reg2_scanin; | |
243 | wire diu_ren_pipe_reg2_scanout; | |
244 | wire diu_ren_pipe_reg2_in; | |
245 | wire diu_rd_en_piped2; | |
246 | wire tdb_ren_pipe_reg1_scanin; | |
247 | wire tdb_ren_pipe_reg1_scanout; | |
248 | wire tdb_ren_pipe_reg1_in; | |
249 | wire tdb_rd_en_piped; | |
250 | wire tdb_ren_pipe_reg2_scanin; | |
251 | wire tdb_ren_pipe_reg2_scanout; | |
252 | wire tdb_ren_pipe_reg2_in; | |
253 | wire tdb_rd_en_piped2; | |
254 | wire dma_data_ren_pipe_reg1_scanin; | |
255 | wire dma_data_ren_pipe_reg1_scanout; | |
256 | wire dma_data_ren_pipe_reg1_in; | |
257 | wire dma_data_rd_en_piped; | |
258 | wire dma_data_ren_pipe_reg2_scanin; | |
259 | wire dma_data_ren_pipe_reg2_scanout; | |
260 | wire dma_data_ren_pipe_reg2_in; | |
261 | wire dma_data_rd_en_piped2; | |
262 | wire pio_data_ren_pipe_reg1_scanin; | |
263 | wire pio_data_ren_pipe_reg1_scanout; | |
264 | wire pio_data_ren_pipe_reg1_in; | |
265 | wire pio_data_rd_en_piped; | |
266 | wire pio_data_ren_pipe_reg2_scanin; | |
267 | wire pio_data_ren_pipe_reg2_scanout; | |
268 | wire pio_data_ren_pipe_reg2_in; | |
269 | wire pio_data_rd_en_piped2; | |
270 | wire dev_ren_pipe_reg1_scanin; | |
271 | wire dev_ren_pipe_reg1_scanout; | |
272 | wire dev_ren_pipe_reg1_in; | |
273 | wire dev_rd_en_piped; | |
274 | wire dev_ren_pipe_reg2_scanin; | |
275 | wire dev_ren_pipe_reg2_scanout; | |
276 | wire dev_ren_pipe_reg2_in; | |
277 | wire dev_rd_en_piped2; | |
278 | wire tsb_ren_pipe_reg1_scanin; | |
279 | wire tsb_ren_pipe_reg1_scanout; | |
280 | wire tsb_ren_pipe_reg1_in; | |
281 | wire tsb_rd_en_piped; | |
282 | wire tsb_ren_pipe_reg2_scanin; | |
283 | wire tsb_ren_pipe_reg2_scanout; | |
284 | wire tsb_ren_pipe_reg2_in; | |
285 | wire tsb_rd_en_piped2; | |
286 | wire cmpsel_pipe_reg1_scanin; | |
287 | wire cmpsel_pipe_reg1_scanout; | |
288 | wire [1:0] cmpsel_pipe_reg1_in; | |
289 | wire [1:0] cmpsel_pipe_out1; | |
290 | wire cmpsel_pipe_reg2_scanin; | |
291 | wire cmpsel_pipe_reg2_scanout; | |
292 | wire [1:0] cmpsel_pipe_reg2_in; | |
293 | wire [1:0] cmpsel_pipe_out2; | |
294 | wire cmpsel_pipe_reg3_scanin; | |
295 | wire cmpsel_pipe_reg3_scanout; | |
296 | wire [1:0] cmpsel_pipe_reg3_in; | |
297 | wire [1:0] cmpsel_pipe_out3; | |
298 | wire [1:0] cmpsel_piped3; | |
299 | wire fail_reg_scanin; | |
300 | wire fail_reg_scanout; | |
301 | wire [5:0] fail_reg_in; | |
302 | wire [5:0] fail_reg_out; | |
303 | wire qual_tsb_fail; | |
304 | wire qual_dev_fail; | |
305 | wire qual_pio_data_fail; | |
306 | wire qual_dma_data_fail; | |
307 | wire qual_tdb_fail; | |
308 | wire qual_diu_fail; | |
309 | wire fail_detect; | |
310 | ||
311 | ||
312 | ||
313 | output dmu_mb0_run; | |
314 | ||
315 | output [8:0] dmu_mb0_addr; | |
316 | output [7:0] dmu_mb0_wdata; | |
317 | //Removed as all the muxing was moved to bist rtl. | |
318 | // output [3:0] dmu_mb0_cmpsel; // Decoded comparator select lines | |
319 | // Used to reduce routed memory outputs to | |
320 | // the mbist engine. | |
321 | ||
322 | output dmu_mb0_diu_wr_en; | |
323 | output dmu_mb0_diu_rd_en; | |
324 | ||
325 | output dmu_mb0_tdb_wr_en; | |
326 | output dmu_mb0_tdb_rd_en; | |
327 | ||
328 | output dmu_mb0_dou_dma_data_wr_en; | |
329 | output dmu_mb0_dou_dma_data_rd_en; | |
330 | ||
331 | output dmu_mb0_dou_pio_data_wr_en; | |
332 | output dmu_mb0_dou_pio_data_rd_en; | |
333 | ||
334 | output dmu_mb0_dev_wr_en; | |
335 | output dmu_mb0_dev_rd_en; | |
336 | ||
337 | output dmu_mb0_tsb_wr_en; | |
338 | output dmu_mb0_tsb_rd_en; | |
339 | ||
340 | output dmu_mb0_done; | |
341 | output dmu_mb0_fail; | |
342 | ||
343 | output scan_out; | |
344 | ||
345 | // input l2clk; | |
346 | input l1clk; // Since l1clkhdr was removed to make asic flow easier. | |
347 | // input tcu_scan_en; | |
348 | input scan_in; | |
349 | input tcu_aclk; | |
350 | input tcu_bclk; | |
351 | // input tcu_pce_ov; | |
352 | // input tcu_clk_stop; | |
353 | input rst_; | |
354 | ||
355 | input tcu_dmu_mb0_start; | |
356 | input dmu_mb0_bisi_mode; | |
357 | input dmu_mb0_user_mode; | |
358 | ||
359 | // To minimize routing of the memory outputs to the mbist controller, | |
360 | // their outputs are muxed. Since the largest memory is x149, the | |
361 | // outputs are muxed 4:1 to get a maximum 38 lines going back to the | |
362 | // mbist engine. To make compare more consistent, this is increased to 40 bits. | |
363 | ||
364 | input [148:0] dmu_diu_read_data; | |
365 | ||
366 | input [59:0] dmu_tdb_read_data; // dmu_mmu_tdb | |
367 | ||
368 | input [131:0] dmu_dou_dma_read_data; | |
369 | input [131:0] dmu_dou_pio_read_data; | |
370 | ||
371 | input [63:0] dev_tsb_read_data; // dmu_mmu_tdb | |
372 | ||
373 | ||
374 | ||
375 | /////////////////////////////////////// | |
376 | // Scan chain connections | |
377 | /////////////////////////////////////// | |
378 | // scan renames | |
379 | // assign se = tcu_scan_en; | |
380 | assign siclk = tcu_aclk; | |
381 | assign soclk = tcu_bclk; | |
382 | // assign pce_ov = tcu_pce_ov; | |
383 | // assign stop = tcu_clk_stop; | |
384 | // end scan | |
385 | ||
386 | // l1clkhdr_ctl_macro clkgen (library=a1) ( | |
387 | // .l2clk (l2clk ), | |
388 | // .l1en (1'b1 ), | |
389 | // .l1clk (l1clk) | |
390 | // ); | |
391 | ||
392 | assign reset = rst_; | |
393 | ||
394 | // ///////////////////////////////////////////////////////////////////////////// | |
395 | // | |
396 | // MBIST Config Register | |
397 | // | |
398 | // ///////////////////////////////////////////////////////////////////////////// | |
399 | // | |
400 | // A low to high transition on mbist_start will reset and start the engine. | |
401 | // mbist_start must remain active high for the duration of MBIST. | |
402 | // If mbist_start deasserts the engine will stop but not reset. | |
403 | // Once MBIST has completed mbist_done will assert and the fail status | |
404 | // signals will be valid. | |
405 | // To run MBIST again the mbist_start signal must transition low then high. | |
406 | // | |
407 | // Loop on Address will disable the address mix function. | |
408 | // | |
409 | // ///////////////////////////////////////////////////////////////////////////// | |
410 | ||
411 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 config_reg ( | |
412 | .scan_in(config_reg_scanin), | |
413 | .scan_out(config_reg_scanout), | |
414 | .din ( config_in[8:0] ), | |
415 | .dout ( config_out[8:0] ), | |
416 | .reset(reset), | |
417 | .l1clk(l1clk), | |
418 | .siclk(siclk), | |
419 | .soclk(soclk)); | |
420 | ||
421 | ||
422 | ||
423 | assign config_in[0] = tcu_dmu_mb0_start; | |
424 | assign config_in[1] = config_out[0]; | |
425 | assign start_transition = config_out[0] & ~config_out[1]; | |
426 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); | |
427 | // assign run = config_out[1] & ~mbist_done; | |
428 | // assign run = config_out[1] & (mbist_user_loop_mode | ~mbist_done); | |
429 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! | |
430 | ||
431 | assign config_in[2] = start_transition ? dmu_mb0_bisi_mode: config_out[2]; | |
432 | assign bisi = config_out[2]; | |
433 | ||
434 | assign config_in[3] = start_transition ? dmu_mb0_user_mode: config_out[3]; | |
435 | assign user_mode = config_out[3]; | |
436 | ||
437 | assign config_in[4] = config_out[4]; | |
438 | assign user_data_mode = config_out[4]; | |
439 | ||
440 | assign config_in[5] = config_out[5]; | |
441 | assign user_addr_mode = config_out[5]; | |
442 | ||
443 | assign config_in[6] = config_out[6]; | |
444 | assign user_loop_mode = config_out[6]; | |
445 | ||
446 | assign config_in[7] = config_out[7]; | |
447 | assign user_cmpsel_hold = config_out[7]; //cmpsel_hold = 0 : Default, All cominations | |
448 | // = 1 : User-specified cmpsel | |
449 | assign config_in[8] = config_out[8]; | |
450 | assign ten_n_mode = config_out[8]; | |
451 | ||
452 | ||
453 | assign mbist_user_data_mode = user_mode & user_data_mode; | |
454 | assign mbist_user_addr_mode = user_mode & user_addr_mode; | |
455 | assign mbist_user_loop_mode = user_mode & user_loop_mode; | |
456 | assign mbist_user_cmpsel_hold = user_mode & user_cmpsel_hold; | |
457 | assign mbist_ten_n_mode = user_mode & ten_n_mode; | |
458 | ||
459 | ||
460 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( | |
461 | .scan_in(user_data_reg_scanin), | |
462 | .scan_out(user_data_reg_scanout), | |
463 | .din ( user_data_in[7:0] ), | |
464 | .dout ( user_data_out[7:0] ), | |
465 | .reset(reset), | |
466 | .l1clk(l1clk), | |
467 | .siclk(siclk), | |
468 | .soclk(soclk)); | |
469 | ||
470 | ||
471 | assign user_data_in[7:0] = user_data_out[7:0]; | |
472 | ||
473 | ||
474 | // Defining User start, stop, and increment addresses. | |
475 | ||
476 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 user_start_addr_reg ( | |
477 | .scan_in(user_start_addr_reg_scanin), | |
478 | .scan_out(user_start_addr_reg_scanout), | |
479 | .din ( user_start_addr_in[8:0] ), | |
480 | .dout ( user_start_addr[8:0] ), | |
481 | .reset(reset), | |
482 | .l1clk(l1clk), | |
483 | .siclk(siclk), | |
484 | .soclk(soclk)); | |
485 | ||
486 | assign user_start_addr_in[8:0] = user_start_addr[8:0]; | |
487 | ||
488 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 user_stop_addr_reg ( | |
489 | .scan_in(user_stop_addr_reg_scanin), | |
490 | .scan_out(user_stop_addr_reg_scanout), | |
491 | .din ( user_stop_addr_in[8:0] ), | |
492 | .dout ( user_stop_addr[8:0] ), | |
493 | .reset(reset), | |
494 | .l1clk(l1clk), | |
495 | .siclk(siclk), | |
496 | .soclk(soclk)); | |
497 | ||
498 | assign user_stop_addr_in[8:0] = user_stop_addr[8:0]; | |
499 | ||
500 | ||
501 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 user_incr_addr_reg ( | |
502 | .scan_in(user_incr_addr_reg_scanin), | |
503 | .scan_out(user_incr_addr_reg_scanout), | |
504 | .din ( user_incr_addr_in[8:0] ), | |
505 | .dout ( user_incr_addr[8:0] ), | |
506 | .reset(reset), | |
507 | .l1clk(l1clk), | |
508 | .siclk(siclk), | |
509 | .soclk(soclk)); | |
510 | ||
511 | assign user_incr_addr_in[8:0] = user_incr_addr[8:0]; | |
512 | ||
513 | // Defining User array_sel. | |
514 | ||
515 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 user_array_sel_reg ( | |
516 | .scan_in(user_array_sel_reg_scanin), | |
517 | .scan_out(user_array_sel_reg_scanout), | |
518 | .din ( user_array_sel_in[2:0] ), | |
519 | .dout ( user_array_sel[2:0] ), | |
520 | .reset(reset), | |
521 | .l1clk(l1clk), | |
522 | .siclk(siclk), | |
523 | .soclk(soclk)); | |
524 | ||
525 | assign user_array_sel_in[2:0] = user_array_sel[2:0]; | |
526 | ||
527 | // Defining User cmpsel. | |
528 | ||
529 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 user_cmpsel_reg ( | |
530 | .scan_in(user_cmpsel_reg_scanin), | |
531 | .scan_out(user_cmpsel_reg_scanout), | |
532 | .din ( user_cmpsel_in[1:0] ), | |
533 | .dout ( user_cmpsel[1:0] ), | |
534 | .reset(reset), | |
535 | .l1clk(l1clk), | |
536 | .siclk(siclk), | |
537 | .soclk(soclk)); | |
538 | ||
539 | assign user_cmpsel_in[1:0] = user_cmpsel[1:0]; | |
540 | ||
541 | // Defining user_bisi write and read registers | |
542 | ||
543 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( | |
544 | .scan_in(user_bisi_wr_reg_scanin), | |
545 | .scan_out(user_bisi_wr_reg_scanout), | |
546 | .din ( user_bisi_wr_mode_in ), | |
547 | .dout ( user_bisi_wr_mode ), | |
548 | .reset(reset), | |
549 | .l1clk(l1clk), | |
550 | .siclk(siclk), | |
551 | .soclk(soclk)); | |
552 | ||
553 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; | |
554 | ||
555 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( | |
556 | .scan_in(user_bisi_rd_reg_scanin), | |
557 | .scan_out(user_bisi_rd_reg_scanout), | |
558 | .din ( user_bisi_rd_mode_in ), | |
559 | .dout ( user_bisi_rd_mode ), | |
560 | .reset(reset), | |
561 | .l1clk(l1clk), | |
562 | .siclk(siclk), | |
563 | .soclk(soclk)); | |
564 | ||
565 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; | |
566 | ||
567 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; | |
568 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; | |
569 | ||
570 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & | |
571 | ((user_bisi_wr_mode & user_bisi_rd_mode) | | |
572 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); | |
573 | ||
574 | //////////////////////////////////////////////////////////////////////////////// | |
575 | // Piping start_transition | |
576 | //////////////////////////////////////////////////////////////////////////////// | |
577 | ||
578 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( | |
579 | .scan_in(start_transition_reg_scanin), | |
580 | .scan_out(start_transition_reg_scanout), | |
581 | .din ( start_transition ), | |
582 | .dout ( start_transition_piped ), | |
583 | .reset(reset), | |
584 | .l1clk(l1clk), | |
585 | .siclk(siclk), | |
586 | .soclk(soclk)); | |
587 | ||
588 | //////////////////////////////////////////////////////////////////////////////// | |
589 | // Staging run for 3 cycles | |
590 | //////////////////////////////////////////////////////////////////////////////// | |
591 | ||
592 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( | |
593 | .scan_in(run_reg_scanin), | |
594 | .scan_out(run_reg_scanout), | |
595 | .din ( run ), | |
596 | .dout ( dmu_mb0_run ), | |
597 | .reset(reset), | |
598 | .l1clk(l1clk), | |
599 | .siclk(siclk), | |
600 | .soclk(soclk)); | |
601 | ||
602 | //Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. | |
603 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( | |
604 | .scan_in(run1_reg_scanin), | |
605 | .scan_out(run1_reg_scanout), | |
606 | .din ( run1_in ), | |
607 | .dout ( run1_out ), | |
608 | .reset(reset), | |
609 | .l1clk(l1clk), | |
610 | .siclk(siclk), | |
611 | .soclk(soclk)); | |
612 | ||
613 | assign run1_in = reset_engine ? 1'b0: dmu_mb0_run; | |
614 | ||
615 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( | |
616 | .scan_in(run2_reg_scanin), | |
617 | .scan_out(run2_reg_scanout), | |
618 | .din ( run2_in ), | |
619 | .dout ( run2_out ), | |
620 | .reset(reset), | |
621 | .l1clk(l1clk), | |
622 | .siclk(siclk), | |
623 | .soclk(soclk)); | |
624 | ||
625 | assign run2_in = reset_engine ? 1'b0: run1_out; | |
626 | // assign run_piped3 = run2_out & run; | |
627 | assign run_piped3 = config_out[0] & run2_out & ~msb; | |
628 | ||
629 | ||
630 | //////////////////////////////////////////////////////////////////////////////// | |
631 | // Creating flop boundaries for the outputs of the mbist | |
632 | //////////////////////////////////////////////////////////////////////////////// | |
633 | ||
634 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 addr_reg ( | |
635 | .scan_in(addr_reg_scanin), | |
636 | .scan_out(addr_reg_scanout), | |
637 | .din ( mbist_address[8:0] ), | |
638 | .dout ( dmu_mb0_addr[8:0] ), | |
639 | .reset(reset), | |
640 | .l1clk(l1clk), | |
641 | .siclk(siclk), | |
642 | .soclk(soclk)); | |
643 | ||
644 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 wdata_reg ( | |
645 | .scan_in(wdata_reg_scanin), | |
646 | .scan_out(wdata_reg_scanout), | |
647 | .din ( mbist_wdata[7:0] ), | |
648 | .dout ( dmu_mb0_wdata[7:0] ), | |
649 | .reset(reset), | |
650 | .l1clk(l1clk), | |
651 | .siclk(siclk), | |
652 | .soclk(soclk)); | |
653 | ||
654 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_12 wr_rd_en_reg ( | |
655 | .scan_in(wr_rd_en_reg_scanin), | |
656 | .scan_out(wr_rd_en_reg_scanout), | |
657 | .din ( {diu_wr_en, diu_rd_en, tdb_wr_en, tdb_rd_en, dma_data_wr_en, dma_data_rd_en, pio_data_wr_en, pio_data_rd_en, dev_wr_en, dev_rd_en, tsb_wr_en, tsb_rd_en } ), | |
658 | .dout ( {dmu_mb0_diu_wr_en, dmu_mb0_diu_rd_en, dmu_mb0_tdb_wr_en, dmu_mb0_tdb_rd_en, dmu_mb0_dou_dma_data_wr_en, dmu_mb0_dou_dma_data_rd_en, dmu_mb0_dou_pio_data_wr_en, dmu_mb0_dou_pio_data_rd_en, dmu_mb0_dev_wr_en, dmu_mb0_dev_rd_en, dmu_mb0_tsb_wr_en, dmu_mb0_tsb_rd_en } ), | |
659 | .reset(reset), | |
660 | .l1clk(l1clk), | |
661 | .siclk(siclk), | |
662 | .soclk(soclk)); | |
663 | ||
664 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( | |
665 | .scan_in(done_reg_scanin), | |
666 | .scan_out(done_reg_scanout), | |
667 | .din ( mbist_done ), | |
668 | .dout ( dmu_mb0_done ), | |
669 | .reset(reset), | |
670 | .l1clk(l1clk), | |
671 | .siclk(siclk), | |
672 | .soclk(soclk)); | |
673 | ||
674 | ||
675 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 mbist_fail_reg ( | |
676 | .scan_in(mbist_fail_reg_scanin), | |
677 | .scan_out(mbist_fail_reg_scanout), | |
678 | .din ( fail ), | |
679 | .dout ( dmu_mb0_fail ), | |
680 | .reset(reset), | |
681 | .l1clk(l1clk), | |
682 | .siclk(siclk), | |
683 | .soclk(soclk)); | |
684 | ||
685 | //////////////////////////////////////////////////////////////////////////////// | |
686 | // Creating 40 bit resultant read_data by muxing the memories outputs | |
687 | //////////////////////////////////////////////////////////////////////////////// | |
688 | ||
689 | reg [39:0] res_read_data; | |
690 | ||
691 | always @ (diu_sel_piped2 or tdb_sel_piped2 or dma_data_sel_piped2 or pio_data_sel_piped2 or dev_sel_piped2 or tsb_sel_piped2 or cmpsel_piped2[1:0] or dmu_diu_read_data or dmu_tdb_read_data or dmu_dou_dma_read_data or dmu_dou_pio_read_data or dev_tsb_read_data) begin | |
692 | case({diu_sel_piped2,tdb_sel_piped2,dma_data_sel_piped2,pio_data_sel_piped2,dev_sel_piped2,tsb_sel_piped2,cmpsel_piped2[1:0]}) //synopsys parallel_case full_case | |
693 | ||
694 | 8'b10000000 : res_read_data[39:0] = dmu_diu_read_data[39:0]; | |
695 | 8'b10000001 : res_read_data[39:0] = dmu_diu_read_data[79:40]; | |
696 | 8'b10000010 : res_read_data[39:0] = dmu_diu_read_data[119:80]; | |
697 | 8'b10000011 : res_read_data[39:0] = {11'b0,dmu_diu_read_data[148:120]}; | |
698 | 8'b01000010 : res_read_data[39:0] = dmu_tdb_read_data[39:0]; | |
699 | 8'b01000011 : res_read_data[39:0] = {20'b0,dmu_tdb_read_data[59:40]}; | |
700 | 8'b00100000 : res_read_data[39:0] = dmu_dou_dma_read_data[39:0]; | |
701 | 8'b00100001 : res_read_data[39:0] = dmu_dou_dma_read_data[79:40]; | |
702 | 8'b00100010 : res_read_data[39:0] = dmu_dou_dma_read_data[119:80]; | |
703 | 8'b00100011 : res_read_data[39:0] = {28'b0,dmu_dou_dma_read_data[131:120]}; | |
704 | 8'b00010000 : res_read_data[39:0] = dmu_dou_pio_read_data[39:0]; | |
705 | 8'b00010001 : res_read_data[39:0] = dmu_dou_pio_read_data[79:40]; | |
706 | 8'b00010010 : res_read_data[39:0] = dmu_dou_pio_read_data[119:80]; | |
707 | 8'b00010011 : res_read_data[39:0] = {28'b0,dmu_dou_pio_read_data[131:120]}; | |
708 | 8'b00001010 : res_read_data[39:0] = dev_tsb_read_data[39:0]; //dev | |
709 | 8'b00001011 : res_read_data[39:0] = {16'b0,dev_tsb_read_data[63:40]}; | |
710 | 8'b00000110 : res_read_data[39:0] = dev_tsb_read_data[39:0]; //tsb | |
711 | 8'b00000111 : res_read_data[39:0] = {16'b0,dev_tsb_read_data[63:40]}; | |
712 | default : res_read_data[39:0] = dmu_diu_read_data[39:0]; | |
713 | endcase | |
714 | end | |
715 | ||
716 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_40 res_read_data_reg ( | |
717 | .scan_in(res_read_data_reg_scanin), | |
718 | .scan_out(res_read_data_reg_scanout), | |
719 | .din ( res_read_data[39:0] ), | |
720 | .dout ( res_read_data_piped[39:0] ), | |
721 | .reset(reset), | |
722 | .l1clk(l1clk), | |
723 | .siclk(siclk), | |
724 | .soclk(soclk)); | |
725 | ||
726 | ||
727 | // ///////////////////////////////////////////////////////////////////////////// | |
728 | // | |
729 | // MBIST Control Register | |
730 | // | |
731 | // ///////////////////////////////////////////////////////////////////////////// | |
732 | // Remove Address mix disable before delivery | |
733 | // ///////////////////////////////////////////////////////////////////////////// | |
734 | ||
735 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_26 control_reg ( | |
736 | .scan_in(control_reg_scanin), | |
737 | .scan_out(control_reg_scanout), | |
738 | .din ( control_in[25:0] ), | |
739 | .dout ( control_out[25:0] ), | |
740 | .reset(reset), | |
741 | .l1clk(l1clk), | |
742 | .siclk(siclk), | |
743 | .soclk(soclk)); | |
744 | ||
745 | assign msb = control_out[25]; | |
746 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[24] : 1'b1; | |
747 | assign array_sel[2:0] = user_mode ? user_array_sel[2:0] : control_out[23:21]; | |
748 | assign cmpsel[1:0] = mbist_user_cmpsel_hold ? user_cmpsel : | |
749 | (tdb_sel || dev_sel || tsb_sel) ? {1'b1, control_out[19]}: | |
750 | control_out[20:19]; | |
751 | assign data_control[1:0] = control_out[18:17]; | |
752 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[16]; | |
753 | assign march_element[3:0] = control_out[15:12]; | |
754 | assign array_address[8:0] = upaddress_march ? control_out[11:3] : ~control_out[11:3]; | |
755 | ||
756 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : | |
757 | control_out[2:0]; | |
758 | ||
759 | ||
760 | assign control_in[2:0] = reset_engine ? 3'b0: | |
761 | ~run_piped3 ? control_out[2:0]: | |
762 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: | |
763 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: | |
764 | control_out[2:0] + 3'b001; | |
765 | ||
766 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || | |
767 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || | |
768 | (read_write_control[2:0] == 3'b111); | |
769 | ||
770 | // start_transition_piped was added to have the correct start_addr at the start | |
771 | // of mbist during user_addr_mode | |
772 | assign control_in[11:3] = start_transition_piped || reset_engine ? start_addr[8:0]: | |
773 | ~run_piped3 || ~increment_addr ? control_out[11:3]: | |
774 | next_array_address[8:0]; | |
775 | ||
776 | assign next_array_address[8:0] = next_upaddr_march ? start_addr[8:0]: | |
777 | next_downaddr_march ? ~stop_addr[8:0]: | |
778 | (overflow_addr[8:0]); // array_addr + incr_addr | |
779 | ||
780 | assign start_addr[8:0] = mbist_user_addr_mode ? user_start_addr[8:0]: 9'h000; | |
781 | assign stop_addr[8:0] = mbist_user_addr_mode ? user_stop_addr[8:0] : | |
782 | diu_sel ? 9'h08F : | |
783 | dma_data_sel ? 9'h07F : | |
784 | pio_data_sel || dev_sel? 9'h00F : | |
785 | tsb_sel ? 9'h01F : 9'h1FF; | |
786 | assign incr_addr[8:0] = mbist_user_addr_mode ? user_incr_addr[8:0] : 9'h001; | |
787 | ||
788 | assign overflow_addr[9:0] = {1'b0,control_out[11:3]} + {1'b0,incr_addr[8:0]}; | |
789 | assign overflow = compare_addr[9:0] < overflow_addr[9:0]; | |
790 | ||
791 | assign compare_addr[9:0] = upaddress_march ? {1'b0, stop_addr[8:0]} : | |
792 | {1'b0, ~start_addr[8:0]}; | |
793 | ||
794 | ||
795 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
796 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || | |
797 | (march_element[3:0] == 4'h8) ) && overflow; | |
798 | ||
799 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || | |
800 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && | |
801 | overflow; | |
802 | ||
803 | ||
804 | ||
805 | assign add[8:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || | |
806 | (read_write_control[2:0] == 3'h3)) ? | |
807 | adj_address[8:0]: array_address[8:0]; | |
808 | ||
809 | // Addresses (MSB:LSB) | |
810 | // diu: 6R, 2B | |
811 | // tdb: 2B, 5R, 2C | |
812 | // dma_data: 2B, 5R | |
813 | // pio_data: 4R | |
814 | // dev: 1B, 3R | |
815 | // tsb: 1B, 4R | |
816 | ||
817 | assign adj_address[8:0] = address_mix & (tdb_sel || diu_sel) ? {array_address[8:1], ~array_address[0]} : | |
818 | tdb_sel || diu_sel ? { array_address[8:3], ~array_address[2], array_address[1:0]} : //2 bit col addr | |
819 | { array_address[8:3], ~array_address[2], array_address[1:0] }; // For all other memories, addresses are bank or row!! | |
820 | ||
821 | assign mbist_address[8:0] = address_mix & tdb_sel ? {add[8:7], add[4:0], add[6:5]}: // Fast row, then column, then bank | |
822 | address_mix & diu_sel ? {add[8], add[7:4], add[1:0], add[3:2]}: // Fast 4 row, then bank, next set of rows--- This is easiest way not to get into the address hole problem. | |
823 | address_mix & dma_data_sel ? {add[8:7], add[1:0], add[6:2]}: // Fast bank | |
824 | address_mix & pio_data_sel ? {add[8:4], add[0], add[3:1]}: // Random | |
825 | address_mix & dev_sel ? {add[8:4], add[0], add[3:1]}: // Fast bank | |
826 | address_mix & tsb_sel ? {add[8:5], add[0], add[4:1]}: // Fast bank | |
827 | add[8:0]; | |
828 | ||
829 | // Definition of the rest of the control register | |
830 | ||
831 | assign increment_march_elem = increment_addr && overflow; | |
832 | ||
833 | assign control_in[25:12] = reset_engine ? 14'b0: | |
834 | ~run_piped3 ? control_out[25:12]: | |
835 | {msb, bisi_wr_rd, next_array_sel[2:0], next_cmpsel[1:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} + | |
836 | {13'b0, increment_march_elem}; | |
837 | ||
838 | ||
839 | assign next_array_sel[2:0] = user_mode ? 3'b111: | |
840 | bisi & (array_sel[2:0] == 3'b101) & | |
841 | (cmpsel[1:0] == 2'b11) & (array_address == stop_addr) ? 3'b111: | |
842 | (array_sel[2:0] == 3'b101) & (cmpsel[1:0] == 2'b11) & (data_control[1:0] == 2'b11) & | |
843 | (next_address_mix == 1'b1) & (march_element[3:0] == 4'b1000) & | |
844 | (array_address == 9'b0) & (read_write_control[2:0] == 3'h4) ? 3'b111: control_out[23:21]; | |
845 | ||
846 | assign next_cmpsel[1:0] = mbist_user_cmpsel_hold || ~bisi_wr_rd || mbist_user_bisi_wr_mode ? 2'b11: | |
847 | (tdb_sel || dev_sel || tsb_sel) ? {1'b1, control_out[19]}: | |
848 | control_out[20:19]; | |
849 | ||
850 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: | |
851 | data_control[1:0]; | |
852 | ||
853 | assign next_address_mix = bisi | mbist_user_addr_mode ? 1'b1 : address_mix; | |
854 | ||
855 | // Incorporated ten_n_mode! | |
856 | assign next_march_element[3:0] = ( bisi || | |
857 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || | |
858 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
859 | && overflow ? 4'b1111: march_element[3:0]; | |
860 | ||
861 | ||
862 | // assign next_march_element[3:0] = (bisi || ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
863 | // && overflow ? 4'b1111: march_element[3:0]; | |
864 | ||
865 | ||
866 | assign array_write = ~run_piped3 ? 1'b0: | |
867 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || | |
868 | (read_write_control[2:0] == 3'h1) || | |
869 | (read_write_control[2:0] == 3'h4): | |
870 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: | |
871 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); | |
872 | ||
873 | assign array_read = ~array_write && run_piped3; // && ~initialize; | |
874 | // assign mbist_done = msb; | |
875 | ||
876 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; | |
877 | ||
878 | ||
879 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); | |
880 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || | |
881 | (march_element[3:0] == 4'h7); | |
882 | ||
883 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
884 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || | |
885 | (march_element[3:0] == 4'h7); | |
886 | ||
887 | // assign true_data = read_write_control[1] ^ ~march_element[0]; | |
888 | ||
889 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? | |
890 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): | |
891 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? | |
892 | ((read_write_control[2:0] == 3'h1) || | |
893 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): | |
894 | one_cycle_march ? (march_element[3:0] == 4'h7): | |
895 | ~(read_write_control[0] ^ march_element[0]); | |
896 | ||
897 | ||
898 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: | |
899 | mbist_user_data_mode ? user_data_out[7:0]: | |
900 | bisi ? 8'hFF: // true_data function will invert to 8'h00 | |
901 | (data_control[1:0] == 2'h0) ? 8'hAA: | |
902 | (data_control[1:0] == 2'h1) ? 8'h99: | |
903 | (data_control[1:0] == 2'h2) ? 8'hCC: | |
904 | 8'h00; | |
905 | ||
906 | ///////////////////////////////////////////////////////////////////////// | |
907 | // Creating the mbist_done signal | |
908 | ///////////////////////////////////////////////////////////////////////// | |
909 | // Delaying mbist_done 8 clock signals after msb going high, to provide | |
910 | // a generic solution for done going high after the last fail has come back! | |
911 | ||
912 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( | |
913 | .scan_in(done_counter_reg_scanin), | |
914 | .scan_out(done_counter_reg_scanout), | |
915 | .din ( done_counter_in[2:0] ), | |
916 | .dout ( done_counter_out[2:0] ), | |
917 | .reset(reset), | |
918 | .l1clk(l1clk), | |
919 | .siclk(siclk), | |
920 | .soclk(soclk)); | |
921 | ||
922 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start | |
923 | // goes low. | |
924 | ||
925 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; | |
926 | assign done_counter_in[2:0] = reset_engine ? 3'b000: | |
927 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: | |
928 | done_counter_out[2:0]; | |
929 | ||
930 | ||
931 | ///////////////////////////////////////////////////////////////////////// | |
932 | // Creating the select and enable lines. | |
933 | ///////////////////////////////////////////////////////////////////////// | |
934 | ||
935 | assign diu_sel = ~array_sel[2] & ~array_sel[1] & ~array_sel[0]; | |
936 | assign tdb_sel = ~array_sel[2] & ~array_sel[1] & array_sel[0]; | |
937 | ||
938 | assign dma_data_sel = ~array_sel[2] & array_sel[1] & ~array_sel[0]; | |
939 | assign pio_data_sel = ~array_sel[2] & array_sel[1] & array_sel[0]; | |
940 | ||
941 | assign dev_sel = array_sel[2] & ~array_sel[1] & ~array_sel[0]; | |
942 | assign tsb_sel = array_sel[2] & ~array_sel[1] & array_sel[0]; | |
943 | ||
944 | assign diu_rd_en = diu_sel && array_read; | |
945 | assign diu_wr_en = diu_sel && array_write; | |
946 | ||
947 | assign tdb_rd_en = tdb_sel && array_read; | |
948 | assign tdb_wr_en = tdb_sel && array_write; | |
949 | ||
950 | assign dma_data_rd_en = dma_data_sel && array_read; | |
951 | assign dma_data_wr_en = dma_data_sel && array_write; | |
952 | ||
953 | assign pio_data_rd_en = pio_data_sel && array_read; | |
954 | assign pio_data_wr_en = pio_data_sel && array_write; | |
955 | ||
956 | assign dev_rd_en = dev_sel && array_read; | |
957 | assign dev_wr_en = dev_sel && array_write; | |
958 | ||
959 | assign tsb_rd_en = tsb_sel && array_read; | |
960 | assign tsb_wr_en = tsb_sel && array_write; | |
961 | ||
962 | ||
963 | // ///////////////////////////////////////////////////////////////////////////// | |
964 | // Pipeline for Address, wdata, and Read_en | |
965 | // ///////////////////////////////////////////////////////////////////////////// | |
966 | ||
967 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( | |
968 | .scan_in(data_pipe_reg1_scanin), | |
969 | .scan_out(data_pipe_reg1_scanout), | |
970 | .din ( data_pipe_reg1_in[7:0] ), | |
971 | .dout ( data_pipe_out1[7:0] ), | |
972 | .reset(reset), | |
973 | .l1clk(l1clk), | |
974 | .siclk(siclk), | |
975 | .soclk(soclk)); | |
976 | ||
977 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( | |
978 | .scan_in(data_pipe_reg2_scanin), | |
979 | .scan_out(data_pipe_reg2_scanout), | |
980 | .din ( data_pipe_reg2_in[7:0] ), | |
981 | .dout ( data_pipe_out2[7:0] ), | |
982 | .reset(reset), | |
983 | .l1clk(l1clk), | |
984 | .siclk(siclk), | |
985 | .soclk(soclk)); | |
986 | ||
987 | //Adding an extra level of pipe since piping the read_data | |
988 | // msff_ctl_macro data_pipe_reg3 (width=8, library=a1)( | |
989 | // .scan_in(data_pipe_reg3_scanin), | |
990 | // .scan_out(data_pipe_reg3_scanout), | |
991 | // .din ( date_pipe_reg3_in[7:0] ), | |
992 | // .dout ( data_pipe_out3[7:0] )); | |
993 | ||
994 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: dmu_mb0_wdata[7:0]; | |
995 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; | |
996 | // assign date_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; | |
997 | ||
998 | assign dmu_mb0_piped_data[7:0] = data_pipe_out2[7:0]; | |
999 | ||
1000 | // Creating pipelined array_sel's | |
1001 | ||
1002 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 array_sel_pipe_reg1 ( | |
1003 | .scan_in(array_sel_pipe_reg1_scanin), | |
1004 | .scan_out(array_sel_pipe_reg1_scanout), | |
1005 | .din ( array_sel_pipe_reg1_in[2:0] ), | |
1006 | .dout ( array_sel_piped[2:0] ), | |
1007 | .reset(reset), | |
1008 | .l1clk(l1clk), | |
1009 | .siclk(siclk), | |
1010 | .soclk(soclk)); | |
1011 | ||
1012 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 array_sel_pipe_reg2 ( | |
1013 | .scan_in(array_sel_pipe_reg2_scanin), | |
1014 | .scan_out(array_sel_pipe_reg2_scanout), | |
1015 | .din ( array_sel_pipe_reg2_in[2:0] ), | |
1016 | .dout ( array_sel_piped2[2:0] ), | |
1017 | .reset(reset), | |
1018 | .l1clk(l1clk), | |
1019 | .siclk(siclk), | |
1020 | .soclk(soclk)); | |
1021 | ||
1022 | assign array_sel_pipe_reg1_in[2:0] = reset_engine ? 3'b0: array_sel[2:0]; | |
1023 | assign array_sel_pipe_reg2_in[2:0] = reset_engine ? 3'b0: array_sel_piped[2:0]; | |
1024 | ||
1025 | assign diu_sel_piped2 = ~array_sel_piped2[2] & ~array_sel_piped2[1] & ~array_sel_piped2[0]; | |
1026 | assign tdb_sel_piped2 = ~array_sel_piped2[2] & ~array_sel_piped2[1] & array_sel_piped2[0]; | |
1027 | ||
1028 | assign dma_data_sel_piped2 = ~array_sel_piped2[2] & array_sel_piped2[1] & ~array_sel_piped2[0]; | |
1029 | assign pio_data_sel_piped2 = ~array_sel_piped2[2] & array_sel_piped2[1] & array_sel_piped2[0]; | |
1030 | ||
1031 | assign dev_sel_piped2 = array_sel_piped2[2] & ~array_sel_piped2[1] & ~array_sel_piped2[0]; | |
1032 | assign tsb_sel_piped2 = array_sel_piped2[2] & ~array_sel_piped2[1] & array_sel_piped2[0]; | |
1033 | ||
1034 | ||
1035 | // Creating pipelined array rd_en's | |
1036 | ||
1037 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 diu_ren_pipe_reg1 ( | |
1038 | .scan_in(diu_ren_pipe_reg1_scanin), | |
1039 | .scan_out(diu_ren_pipe_reg1_scanout), | |
1040 | .din ( diu_ren_pipe_reg1_in ), | |
1041 | .dout ( diu_rd_en_piped ), | |
1042 | .reset(reset), | |
1043 | .l1clk(l1clk), | |
1044 | .siclk(siclk), | |
1045 | .soclk(soclk)); | |
1046 | ||
1047 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 diu_ren_pipe_reg2 ( | |
1048 | .scan_in(diu_ren_pipe_reg2_scanin), | |
1049 | .scan_out(diu_ren_pipe_reg2_scanout), | |
1050 | .din ( diu_ren_pipe_reg2_in ), | |
1051 | .dout ( diu_rd_en_piped2 ), | |
1052 | .reset(reset), | |
1053 | .l1clk(l1clk), | |
1054 | .siclk(siclk), | |
1055 | .soclk(soclk)); | |
1056 | ||
1057 | assign diu_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_mb0_diu_rd_en; | |
1058 | assign diu_ren_pipe_reg2_in = reset_engine ? 1'b0: diu_rd_en_piped; | |
1059 | ||
1060 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 tdb_ren_pipe_reg1 ( | |
1061 | .scan_in(tdb_ren_pipe_reg1_scanin), | |
1062 | .scan_out(tdb_ren_pipe_reg1_scanout), | |
1063 | .din ( tdb_ren_pipe_reg1_in ), | |
1064 | .dout ( tdb_rd_en_piped ), | |
1065 | .reset(reset), | |
1066 | .l1clk(l1clk), | |
1067 | .siclk(siclk), | |
1068 | .soclk(soclk)); | |
1069 | ||
1070 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 tdb_ren_pipe_reg2 ( | |
1071 | .scan_in(tdb_ren_pipe_reg2_scanin), | |
1072 | .scan_out(tdb_ren_pipe_reg2_scanout), | |
1073 | .din ( tdb_ren_pipe_reg2_in ), | |
1074 | .dout ( tdb_rd_en_piped2 ), | |
1075 | .reset(reset), | |
1076 | .l1clk(l1clk), | |
1077 | .siclk(siclk), | |
1078 | .soclk(soclk)); | |
1079 | ||
1080 | assign tdb_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_mb0_tdb_rd_en; | |
1081 | assign tdb_ren_pipe_reg2_in = reset_engine ? 1'b0: tdb_rd_en_piped; | |
1082 | ||
1083 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 dma_data_ren_pipe_reg1 ( | |
1084 | .scan_in(dma_data_ren_pipe_reg1_scanin), | |
1085 | .scan_out(dma_data_ren_pipe_reg1_scanout), | |
1086 | .din ( dma_data_ren_pipe_reg1_in ), | |
1087 | .dout ( dma_data_rd_en_piped ), | |
1088 | .reset(reset), | |
1089 | .l1clk(l1clk), | |
1090 | .siclk(siclk), | |
1091 | .soclk(soclk)); | |
1092 | ||
1093 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 dma_data_ren_pipe_reg2 ( | |
1094 | .scan_in(dma_data_ren_pipe_reg2_scanin), | |
1095 | .scan_out(dma_data_ren_pipe_reg2_scanout), | |
1096 | .din ( dma_data_ren_pipe_reg2_in ), | |
1097 | .dout ( dma_data_rd_en_piped2 ), | |
1098 | .reset(reset), | |
1099 | .l1clk(l1clk), | |
1100 | .siclk(siclk), | |
1101 | .soclk(soclk)); | |
1102 | ||
1103 | assign dma_data_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_mb0_dou_dma_data_rd_en; | |
1104 | assign dma_data_ren_pipe_reg2_in = reset_engine ? 1'b0: dma_data_rd_en_piped; | |
1105 | ||
1106 | ||
1107 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 pio_data_ren_pipe_reg1 ( | |
1108 | .scan_in(pio_data_ren_pipe_reg1_scanin), | |
1109 | .scan_out(pio_data_ren_pipe_reg1_scanout), | |
1110 | .din ( pio_data_ren_pipe_reg1_in ), | |
1111 | .dout ( pio_data_rd_en_piped ), | |
1112 | .reset(reset), | |
1113 | .l1clk(l1clk), | |
1114 | .siclk(siclk), | |
1115 | .soclk(soclk)); | |
1116 | ||
1117 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 pio_data_ren_pipe_reg2 ( | |
1118 | .scan_in(pio_data_ren_pipe_reg2_scanin), | |
1119 | .scan_out(pio_data_ren_pipe_reg2_scanout), | |
1120 | .din ( pio_data_ren_pipe_reg2_in ), | |
1121 | .dout ( pio_data_rd_en_piped2 ), | |
1122 | .reset(reset), | |
1123 | .l1clk(l1clk), | |
1124 | .siclk(siclk), | |
1125 | .soclk(soclk)); | |
1126 | ||
1127 | assign pio_data_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_mb0_dou_pio_data_rd_en; | |
1128 | assign pio_data_ren_pipe_reg2_in = reset_engine ? 1'b0: pio_data_rd_en_piped; | |
1129 | ||
1130 | ||
1131 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 dev_ren_pipe_reg1 ( | |
1132 | .scan_in(dev_ren_pipe_reg1_scanin), | |
1133 | .scan_out(dev_ren_pipe_reg1_scanout), | |
1134 | .din ( dev_ren_pipe_reg1_in ), | |
1135 | .dout ( dev_rd_en_piped ), | |
1136 | .reset(reset), | |
1137 | .l1clk(l1clk), | |
1138 | .siclk(siclk), | |
1139 | .soclk(soclk)); | |
1140 | ||
1141 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 dev_ren_pipe_reg2 ( | |
1142 | .scan_in(dev_ren_pipe_reg2_scanin), | |
1143 | .scan_out(dev_ren_pipe_reg2_scanout), | |
1144 | .din ( dev_ren_pipe_reg2_in ), | |
1145 | .dout ( dev_rd_en_piped2 ), | |
1146 | .reset(reset), | |
1147 | .l1clk(l1clk), | |
1148 | .siclk(siclk), | |
1149 | .soclk(soclk)); | |
1150 | ||
1151 | assign dev_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_mb0_dev_rd_en; | |
1152 | assign dev_ren_pipe_reg2_in = reset_engine ? 1'b0: dev_rd_en_piped; | |
1153 | ||
1154 | ||
1155 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 tsb_ren_pipe_reg1 ( | |
1156 | .scan_in(tsb_ren_pipe_reg1_scanin), | |
1157 | .scan_out(tsb_ren_pipe_reg1_scanout), | |
1158 | .din ( tsb_ren_pipe_reg1_in ), | |
1159 | .dout ( tsb_rd_en_piped ), | |
1160 | .reset(reset), | |
1161 | .l1clk(l1clk), | |
1162 | .siclk(siclk), | |
1163 | .soclk(soclk)); | |
1164 | ||
1165 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 tsb_ren_pipe_reg2 ( | |
1166 | .scan_in(tsb_ren_pipe_reg2_scanin), | |
1167 | .scan_out(tsb_ren_pipe_reg2_scanout), | |
1168 | .din ( tsb_ren_pipe_reg2_in ), | |
1169 | .dout ( tsb_rd_en_piped2 ), | |
1170 | .reset(reset), | |
1171 | .l1clk(l1clk), | |
1172 | .siclk(siclk), | |
1173 | .soclk(soclk)); | |
1174 | ||
1175 | assign tsb_ren_pipe_reg1_in = reset_engine ? 1'b0: dmu_mb0_tsb_rd_en; | |
1176 | assign tsb_ren_pipe_reg2_in = reset_engine ? 1'b0: tsb_rd_en_piped; | |
1177 | ||
1178 | // Pipelining cmpsel | |
1179 | ||
1180 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 cmpsel_pipe_reg1 ( | |
1181 | .scan_in(cmpsel_pipe_reg1_scanin), | |
1182 | .scan_out(cmpsel_pipe_reg1_scanout), | |
1183 | .din ( cmpsel_pipe_reg1_in[1:0] ), | |
1184 | .dout ( cmpsel_pipe_out1[1:0] ), | |
1185 | .reset(reset), | |
1186 | .l1clk(l1clk), | |
1187 | .siclk(siclk), | |
1188 | .soclk(soclk)); | |
1189 | ||
1190 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 cmpsel_pipe_reg2 ( | |
1191 | .scan_in(cmpsel_pipe_reg2_scanin), | |
1192 | .scan_out(cmpsel_pipe_reg2_scanout), | |
1193 | .din ( cmpsel_pipe_reg2_in[1:0] ), | |
1194 | .dout ( cmpsel_pipe_out2[1:0] ), | |
1195 | .reset(reset), | |
1196 | .l1clk(l1clk), | |
1197 | .siclk(siclk), | |
1198 | .soclk(soclk)); | |
1199 | ||
1200 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 cmpsel_pipe_reg3 ( | |
1201 | .scan_in(cmpsel_pipe_reg3_scanin), | |
1202 | .scan_out(cmpsel_pipe_reg3_scanout), | |
1203 | .din ( cmpsel_pipe_reg3_in[1:0] ), | |
1204 | .dout ( cmpsel_pipe_out3[1:0] ), | |
1205 | .reset(reset), | |
1206 | .l1clk(l1clk), | |
1207 | .siclk(siclk), | |
1208 | .soclk(soclk)); | |
1209 | ||
1210 | assign cmpsel_pipe_reg1_in[1:0] = reset_engine ? 2'b0: cmpsel[1:0]; | |
1211 | assign cmpsel_pipe_reg2_in[1:0] = reset_engine ? 2'b0: cmpsel_pipe_out1[1:0]; | |
1212 | assign cmpsel_pipe_reg3_in[1:0] = reset_engine ? 2'b0: cmpsel_pipe_out2[1:0]; | |
1213 | assign cmpsel_piped2[1:0] = cmpsel_pipe_out2[1:0]; | |
1214 | assign cmpsel_piped3[1:0] = cmpsel_pipe_out3[1:0]; | |
1215 | ||
1216 | ||
1217 | ||
1218 | // ///////////////////////////////////////////////////////////////////////////// | |
1219 | // Shared Fail Detection | |
1220 | // ///////////////////////////////////////////////////////////////////////////// | |
1221 | // 05/10/05: Updated to meet these new features: | |
1222 | // 1.When mbist_done signal is asserted when it completes all the | |
1223 | // tests, it also need to assert static membist fail signal if | |
1224 | // there were any failures during the tests. | |
1225 | // 2.The mbist_fail signal won't be sticky bit from membist | |
1226 | // engine. The TCU will make it sticky fail bit as needed. | |
1227 | ||
1228 | ||
1229 | dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_6 fail_reg ( | |
1230 | .scan_in(fail_reg_scanin), | |
1231 | .scan_out(fail_reg_scanout), | |
1232 | .din ( fail_reg_in[5:0] ), | |
1233 | .dout ( fail_reg_out[5:0] ), | |
1234 | .reset(reset), | |
1235 | .l1clk(l1clk), | |
1236 | .siclk(siclk), | |
1237 | .soclk(soclk)); | |
1238 | ||
1239 | ||
1240 | assign fail_reg_in[5:0] = reset_engine ? 6'b0: {qual_tsb_fail,qual_dev_fail,qual_pio_data_fail,qual_dma_data_fail,qual_tdb_fail,qual_diu_fail} | fail_reg_out[5:0]; | |
1241 | ||
1242 | ||
1243 | assign qual_diu_fail = fail_detect && diu_rd_en_piped2; | |
1244 | assign qual_tdb_fail = fail_detect && tdb_rd_en_piped2; | |
1245 | assign qual_dma_data_fail = fail_detect && dma_data_rd_en_piped2; | |
1246 | assign qual_pio_data_fail = fail_detect && pio_data_rd_en_piped2; | |
1247 | assign qual_dev_fail = fail_detect && dev_rd_en_piped2; | |
1248 | assign qual_tsb_fail = fail_detect && tsb_rd_en_piped2; | |
1249 | ||
1250 | assign fail = mbist_done ? |fail_reg_out[5:0]: | |
1251 | qual_diu_fail | qual_tdb_fail | qual_dma_data_fail | | |
1252 | qual_pio_data_fail | qual_dev_fail | qual_tsb_fail; | |
1253 | ||
1254 | ||
1255 | assign fail_detect = (diu_rd_en_piped2 && (cmpsel_piped3[1:0] == 2'b11)) ? | |
1256 | ({dmu_mb0_piped_data[4:0], {3{dmu_mb0_piped_data[7:0]}} } != res_read_data_piped[28:0]): | |
1257 | (tdb_rd_en_piped2 && (cmpsel_piped3[1:0] == 2'b11)) ? | |
1258 | ({dmu_mb0_piped_data[3:0], {2{dmu_mb0_piped_data[7:0]}} } != res_read_data_piped[19:0]): | |
1259 | ((dma_data_rd_en_piped2 || pio_data_rd_en_piped2) && (cmpsel_piped3[1:0] == 2'b11)) ? | |
1260 | ({dmu_mb0_piped_data[3:0], dmu_mb0_piped_data[7:0] } != res_read_data_piped[11:0]): | |
1261 | ((dev_rd_en_piped2 || tsb_rd_en_piped2) && (cmpsel_piped3[1:0] == 2'b11)) ? | |
1262 | ({3{dmu_mb0_piped_data[7:0]} } != res_read_data_piped[23:0]): | |
1263 | ({5{dmu_mb0_piped_data[7:0]} } != res_read_data_piped[39:0]) ; | |
1264 | ||
1265 | ||
1266 | // fixscan start: | |
1267 | assign config_reg_scanin = scan_in ; | |
1268 | assign user_data_reg_scanin = config_reg_scanout ; | |
1269 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; | |
1270 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
1271 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
1272 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; | |
1273 | assign user_cmpsel_reg_scanin = user_array_sel_reg_scanout; | |
1274 | assign user_bisi_wr_reg_scanin = user_cmpsel_reg_scanout ; | |
1275 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; | |
1276 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; | |
1277 | assign run_reg_scanin = start_transition_reg_scanout; | |
1278 | assign run1_reg_scanin = run_reg_scanout ; | |
1279 | assign run2_reg_scanin = run1_reg_scanout ; | |
1280 | assign addr_reg_scanin = run2_reg_scanout ; | |
1281 | assign wdata_reg_scanin = addr_reg_scanout ; | |
1282 | assign wr_rd_en_reg_scanin = wdata_reg_scanout ; | |
1283 | assign done_reg_scanin = wr_rd_en_reg_scanout ; | |
1284 | assign mbist_fail_reg_scanin = done_reg_scanout ; | |
1285 | assign res_read_data_reg_scanin = mbist_fail_reg_scanout ; | |
1286 | assign control_reg_scanin = res_read_data_reg_scanout; | |
1287 | assign done_counter_reg_scanin = control_reg_scanout ; | |
1288 | assign data_pipe_reg1_scanin = done_counter_reg_scanout ; | |
1289 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; | |
1290 | assign array_sel_pipe_reg1_scanin = data_pipe_reg2_scanout ; | |
1291 | assign array_sel_pipe_reg2_scanin = array_sel_pipe_reg1_scanout; | |
1292 | assign diu_ren_pipe_reg1_scanin = array_sel_pipe_reg2_scanout; | |
1293 | assign diu_ren_pipe_reg2_scanin = diu_ren_pipe_reg1_scanout; | |
1294 | assign tdb_ren_pipe_reg1_scanin = diu_ren_pipe_reg2_scanout; | |
1295 | assign tdb_ren_pipe_reg2_scanin = tdb_ren_pipe_reg1_scanout; | |
1296 | assign dma_data_ren_pipe_reg1_scanin = tdb_ren_pipe_reg2_scanout; | |
1297 | assign dma_data_ren_pipe_reg2_scanin = dma_data_ren_pipe_reg1_scanout; | |
1298 | assign pio_data_ren_pipe_reg1_scanin = dma_data_ren_pipe_reg2_scanout; | |
1299 | assign pio_data_ren_pipe_reg2_scanin = pio_data_ren_pipe_reg1_scanout; | |
1300 | assign dev_ren_pipe_reg1_scanin = pio_data_ren_pipe_reg2_scanout; | |
1301 | assign dev_ren_pipe_reg2_scanin = dev_ren_pipe_reg1_scanout; | |
1302 | assign tsb_ren_pipe_reg1_scanin = dev_ren_pipe_reg2_scanout; | |
1303 | assign tsb_ren_pipe_reg2_scanin = tsb_ren_pipe_reg1_scanout; | |
1304 | assign cmpsel_pipe_reg1_scanin = tsb_ren_pipe_reg2_scanout; | |
1305 | assign cmpsel_pipe_reg2_scanin = cmpsel_pipe_reg1_scanout ; | |
1306 | assign cmpsel_pipe_reg3_scanin = cmpsel_pipe_reg2_scanout ; | |
1307 | assign fail_reg_scanin = cmpsel_pipe_reg3_scanout ; | |
1308 | assign scan_out = fail_reg_scanout ; | |
1309 | // fixscan end: | |
1310 | endmodule | |
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | ||
1316 | ||
1317 | // any PARAMS parms go into naming of macro | |
1318 | ||
1319 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_9 ( | |
1320 | din, | |
1321 | reset, | |
1322 | l1clk, | |
1323 | scan_in, | |
1324 | siclk, | |
1325 | soclk, | |
1326 | dout, | |
1327 | scan_out); | |
1328 | wire [8:0] fdin; | |
1329 | wire [8:1] sout; | |
1330 | ||
1331 | input [8:0] din; | |
1332 | input reset; | |
1333 | input l1clk; | |
1334 | input scan_in; | |
1335 | ||
1336 | ||
1337 | input siclk; | |
1338 | input soclk; | |
1339 | ||
1340 | output [8:0] dout; | |
1341 | output scan_out; | |
1342 | assign fdin[8:0] = din[8:0] & {9 {reset}}; | |
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | ||
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | cl_a1_msff_syrst_4x d0_0 ( | |
1361 | .l1clk(l1clk), | |
1362 | .siclk(siclk), | |
1363 | .soclk(soclk), | |
1364 | .d(fdin[0]), | |
1365 | .si(sout[1]), | |
1366 | .so(scan_out), | |
1367 | .reset(reset), | |
1368 | .q(dout[0]) | |
1369 | ); | |
1370 | cl_a1_msff_syrst_4x d0_1 ( | |
1371 | .l1clk(l1clk), | |
1372 | .siclk(siclk), | |
1373 | .soclk(soclk), | |
1374 | .d(fdin[1]), | |
1375 | .si(sout[2]), | |
1376 | .so(sout[1]), | |
1377 | .reset(reset), | |
1378 | .q(dout[1]) | |
1379 | ); | |
1380 | cl_a1_msff_syrst_4x d0_2 ( | |
1381 | .l1clk(l1clk), | |
1382 | .siclk(siclk), | |
1383 | .soclk(soclk), | |
1384 | .d(fdin[2]), | |
1385 | .si(sout[3]), | |
1386 | .so(sout[2]), | |
1387 | .reset(reset), | |
1388 | .q(dout[2]) | |
1389 | ); | |
1390 | cl_a1_msff_syrst_4x d0_3 ( | |
1391 | .l1clk(l1clk), | |
1392 | .siclk(siclk), | |
1393 | .soclk(soclk), | |
1394 | .d(fdin[3]), | |
1395 | .si(sout[4]), | |
1396 | .so(sout[3]), | |
1397 | .reset(reset), | |
1398 | .q(dout[3]) | |
1399 | ); | |
1400 | cl_a1_msff_syrst_4x d0_4 ( | |
1401 | .l1clk(l1clk), | |
1402 | .siclk(siclk), | |
1403 | .soclk(soclk), | |
1404 | .d(fdin[4]), | |
1405 | .si(sout[5]), | |
1406 | .so(sout[4]), | |
1407 | .reset(reset), | |
1408 | .q(dout[4]) | |
1409 | ); | |
1410 | cl_a1_msff_syrst_4x d0_5 ( | |
1411 | .l1clk(l1clk), | |
1412 | .siclk(siclk), | |
1413 | .soclk(soclk), | |
1414 | .d(fdin[5]), | |
1415 | .si(sout[6]), | |
1416 | .so(sout[5]), | |
1417 | .reset(reset), | |
1418 | .q(dout[5]) | |
1419 | ); | |
1420 | cl_a1_msff_syrst_4x d0_6 ( | |
1421 | .l1clk(l1clk), | |
1422 | .siclk(siclk), | |
1423 | .soclk(soclk), | |
1424 | .d(fdin[6]), | |
1425 | .si(sout[7]), | |
1426 | .so(sout[6]), | |
1427 | .reset(reset), | |
1428 | .q(dout[6]) | |
1429 | ); | |
1430 | cl_a1_msff_syrst_4x d0_7 ( | |
1431 | .l1clk(l1clk), | |
1432 | .siclk(siclk), | |
1433 | .soclk(soclk), | |
1434 | .d(fdin[7]), | |
1435 | .si(sout[8]), | |
1436 | .so(sout[7]), | |
1437 | .reset(reset), | |
1438 | .q(dout[7]) | |
1439 | ); | |
1440 | cl_a1_msff_syrst_4x d0_8 ( | |
1441 | .l1clk(l1clk), | |
1442 | .siclk(siclk), | |
1443 | .soclk(soclk), | |
1444 | .d(fdin[8]), | |
1445 | .si(scan_in), | |
1446 | .so(sout[8]), | |
1447 | .reset(reset), | |
1448 | .q(dout[8]) | |
1449 | ); | |
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | endmodule | |
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | // any PARAMS parms go into naming of macro | |
1469 | ||
1470 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_8 ( | |
1471 | din, | |
1472 | reset, | |
1473 | l1clk, | |
1474 | scan_in, | |
1475 | siclk, | |
1476 | soclk, | |
1477 | dout, | |
1478 | scan_out); | |
1479 | wire [7:0] fdin; | |
1480 | wire [7:1] sout; | |
1481 | ||
1482 | input [7:0] din; | |
1483 | input reset; | |
1484 | input l1clk; | |
1485 | input scan_in; | |
1486 | ||
1487 | ||
1488 | input siclk; | |
1489 | input soclk; | |
1490 | ||
1491 | output [7:0] dout; | |
1492 | output scan_out; | |
1493 | assign fdin[7:0] = din[7:0] & {8 {reset}}; | |
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | ||
1511 | cl_a1_msff_syrst_4x d0_0 ( | |
1512 | .l1clk(l1clk), | |
1513 | .siclk(siclk), | |
1514 | .soclk(soclk), | |
1515 | .d(fdin[0]), | |
1516 | .si(sout[1]), | |
1517 | .so(scan_out), | |
1518 | .reset(reset), | |
1519 | .q(dout[0]) | |
1520 | ); | |
1521 | cl_a1_msff_syrst_4x d0_1 ( | |
1522 | .l1clk(l1clk), | |
1523 | .siclk(siclk), | |
1524 | .soclk(soclk), | |
1525 | .d(fdin[1]), | |
1526 | .si(sout[2]), | |
1527 | .so(sout[1]), | |
1528 | .reset(reset), | |
1529 | .q(dout[1]) | |
1530 | ); | |
1531 | cl_a1_msff_syrst_4x d0_2 ( | |
1532 | .l1clk(l1clk), | |
1533 | .siclk(siclk), | |
1534 | .soclk(soclk), | |
1535 | .d(fdin[2]), | |
1536 | .si(sout[3]), | |
1537 | .so(sout[2]), | |
1538 | .reset(reset), | |
1539 | .q(dout[2]) | |
1540 | ); | |
1541 | cl_a1_msff_syrst_4x d0_3 ( | |
1542 | .l1clk(l1clk), | |
1543 | .siclk(siclk), | |
1544 | .soclk(soclk), | |
1545 | .d(fdin[3]), | |
1546 | .si(sout[4]), | |
1547 | .so(sout[3]), | |
1548 | .reset(reset), | |
1549 | .q(dout[3]) | |
1550 | ); | |
1551 | cl_a1_msff_syrst_4x d0_4 ( | |
1552 | .l1clk(l1clk), | |
1553 | .siclk(siclk), | |
1554 | .soclk(soclk), | |
1555 | .d(fdin[4]), | |
1556 | .si(sout[5]), | |
1557 | .so(sout[4]), | |
1558 | .reset(reset), | |
1559 | .q(dout[4]) | |
1560 | ); | |
1561 | cl_a1_msff_syrst_4x d0_5 ( | |
1562 | .l1clk(l1clk), | |
1563 | .siclk(siclk), | |
1564 | .soclk(soclk), | |
1565 | .d(fdin[5]), | |
1566 | .si(sout[6]), | |
1567 | .so(sout[5]), | |
1568 | .reset(reset), | |
1569 | .q(dout[5]) | |
1570 | ); | |
1571 | cl_a1_msff_syrst_4x d0_6 ( | |
1572 | .l1clk(l1clk), | |
1573 | .siclk(siclk), | |
1574 | .soclk(soclk), | |
1575 | .d(fdin[6]), | |
1576 | .si(sout[7]), | |
1577 | .so(sout[6]), | |
1578 | .reset(reset), | |
1579 | .q(dout[6]) | |
1580 | ); | |
1581 | cl_a1_msff_syrst_4x d0_7 ( | |
1582 | .l1clk(l1clk), | |
1583 | .siclk(siclk), | |
1584 | .soclk(soclk), | |
1585 | .d(fdin[7]), | |
1586 | .si(scan_in), | |
1587 | .so(sout[7]), | |
1588 | .reset(reset), | |
1589 | .q(dout[7]) | |
1590 | ); | |
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | endmodule | |
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | // any PARAMS parms go into naming of macro | |
1610 | ||
1611 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_3 ( | |
1612 | din, | |
1613 | reset, | |
1614 | l1clk, | |
1615 | scan_in, | |
1616 | siclk, | |
1617 | soclk, | |
1618 | dout, | |
1619 | scan_out); | |
1620 | wire [2:0] fdin; | |
1621 | wire [2:1] sout; | |
1622 | ||
1623 | input [2:0] din; | |
1624 | input reset; | |
1625 | input l1clk; | |
1626 | input scan_in; | |
1627 | ||
1628 | ||
1629 | input siclk; | |
1630 | input soclk; | |
1631 | ||
1632 | output [2:0] dout; | |
1633 | output scan_out; | |
1634 | assign fdin[2:0] = din[2:0] & {3 {reset}}; | |
1635 | ||
1636 | ||
1637 | ||
1638 | ||
1639 | ||
1640 | ||
1641 | ||
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | ||
1652 | cl_a1_msff_syrst_4x d0_0 ( | |
1653 | .l1clk(l1clk), | |
1654 | .siclk(siclk), | |
1655 | .soclk(soclk), | |
1656 | .d(fdin[0]), | |
1657 | .si(sout[1]), | |
1658 | .so(scan_out), | |
1659 | .reset(reset), | |
1660 | .q(dout[0]) | |
1661 | ); | |
1662 | cl_a1_msff_syrst_4x d0_1 ( | |
1663 | .l1clk(l1clk), | |
1664 | .siclk(siclk), | |
1665 | .soclk(soclk), | |
1666 | .d(fdin[1]), | |
1667 | .si(sout[2]), | |
1668 | .so(sout[1]), | |
1669 | .reset(reset), | |
1670 | .q(dout[1]) | |
1671 | ); | |
1672 | cl_a1_msff_syrst_4x d0_2 ( | |
1673 | .l1clk(l1clk), | |
1674 | .siclk(siclk), | |
1675 | .soclk(soclk), | |
1676 | .d(fdin[2]), | |
1677 | .si(scan_in), | |
1678 | .so(sout[2]), | |
1679 | .reset(reset), | |
1680 | .q(dout[2]) | |
1681 | ); | |
1682 | ||
1683 | ||
1684 | ||
1685 | ||
1686 | endmodule | |
1687 | ||
1688 | ||
1689 | ||
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | ||
1695 | ||
1696 | ||
1697 | ||
1698 | ||
1699 | ||
1700 | // any PARAMS parms go into naming of macro | |
1701 | ||
1702 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_2 ( | |
1703 | din, | |
1704 | reset, | |
1705 | l1clk, | |
1706 | scan_in, | |
1707 | siclk, | |
1708 | soclk, | |
1709 | dout, | |
1710 | scan_out); | |
1711 | wire [1:0] fdin; | |
1712 | wire [1:1] sout; | |
1713 | ||
1714 | input [1:0] din; | |
1715 | input reset; | |
1716 | input l1clk; | |
1717 | input scan_in; | |
1718 | ||
1719 | ||
1720 | input siclk; | |
1721 | input soclk; | |
1722 | ||
1723 | output [1:0] dout; | |
1724 | output scan_out; | |
1725 | assign fdin[1:0] = din[1:0] & {2 {reset}}; | |
1726 | ||
1727 | ||
1728 | ||
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | ||
1742 | ||
1743 | cl_a1_msff_syrst_4x d0_0 ( | |
1744 | .l1clk(l1clk), | |
1745 | .siclk(siclk), | |
1746 | .soclk(soclk), | |
1747 | .d(fdin[0]), | |
1748 | .si(sout[1]), | |
1749 | .so(scan_out), | |
1750 | .reset(reset), | |
1751 | .q(dout[0]) | |
1752 | ); | |
1753 | cl_a1_msff_syrst_4x d0_1 ( | |
1754 | .l1clk(l1clk), | |
1755 | .siclk(siclk), | |
1756 | .soclk(soclk), | |
1757 | .d(fdin[1]), | |
1758 | .si(scan_in), | |
1759 | .so(sout[1]), | |
1760 | .reset(reset), | |
1761 | .q(dout[1]) | |
1762 | ); | |
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | endmodule | |
1768 | ||
1769 | ||
1770 | ||
1771 | ||
1772 | ||
1773 | ||
1774 | ||
1775 | ||
1776 | ||
1777 | ||
1778 | ||
1779 | ||
1780 | ||
1781 | // any PARAMS parms go into naming of macro | |
1782 | ||
1783 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_1 ( | |
1784 | din, | |
1785 | reset, | |
1786 | l1clk, | |
1787 | scan_in, | |
1788 | siclk, | |
1789 | soclk, | |
1790 | dout, | |
1791 | scan_out); | |
1792 | wire [0:0] fdin; | |
1793 | ||
1794 | input [0:0] din; | |
1795 | input reset; | |
1796 | input l1clk; | |
1797 | input scan_in; | |
1798 | ||
1799 | ||
1800 | input siclk; | |
1801 | input soclk; | |
1802 | ||
1803 | output [0:0] dout; | |
1804 | output scan_out; | |
1805 | assign fdin[0:0] = din[0:0] & {1 {reset}}; | |
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | ||
1818 | ||
1819 | ||
1820 | ||
1821 | ||
1822 | ||
1823 | cl_a1_msff_syrst_4x d0_0 ( | |
1824 | .l1clk(l1clk), | |
1825 | .siclk(siclk), | |
1826 | .soclk(soclk), | |
1827 | .d(fdin[0]), | |
1828 | .si(scan_in), | |
1829 | .so(scan_out), | |
1830 | .reset(reset), | |
1831 | .q(dout[0]) | |
1832 | ); | |
1833 | ||
1834 | ||
1835 | ||
1836 | ||
1837 | endmodule | |
1838 | ||
1839 | ||
1840 | ||
1841 | ||
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | ||
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | // any PARAMS parms go into naming of macro | |
1852 | ||
1853 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_12 ( | |
1854 | din, | |
1855 | reset, | |
1856 | l1clk, | |
1857 | scan_in, | |
1858 | siclk, | |
1859 | soclk, | |
1860 | dout, | |
1861 | scan_out); | |
1862 | wire [11:0] fdin; | |
1863 | wire [11:1] sout; | |
1864 | ||
1865 | input [11:0] din; | |
1866 | input reset; | |
1867 | input l1clk; | |
1868 | input scan_in; | |
1869 | ||
1870 | ||
1871 | input siclk; | |
1872 | input soclk; | |
1873 | ||
1874 | output [11:0] dout; | |
1875 | output scan_out; | |
1876 | assign fdin[11:0] = din[11:0] & {12 {reset}}; | |
1877 | ||
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | cl_a1_msff_syrst_4x d0_0 ( | |
1895 | .l1clk(l1clk), | |
1896 | .siclk(siclk), | |
1897 | .soclk(soclk), | |
1898 | .d(fdin[0]), | |
1899 | .si(sout[1]), | |
1900 | .so(scan_out), | |
1901 | .reset(reset), | |
1902 | .q(dout[0]) | |
1903 | ); | |
1904 | cl_a1_msff_syrst_4x d0_1 ( | |
1905 | .l1clk(l1clk), | |
1906 | .siclk(siclk), | |
1907 | .soclk(soclk), | |
1908 | .d(fdin[1]), | |
1909 | .si(sout[2]), | |
1910 | .so(sout[1]), | |
1911 | .reset(reset), | |
1912 | .q(dout[1]) | |
1913 | ); | |
1914 | cl_a1_msff_syrst_4x d0_2 ( | |
1915 | .l1clk(l1clk), | |
1916 | .siclk(siclk), | |
1917 | .soclk(soclk), | |
1918 | .d(fdin[2]), | |
1919 | .si(sout[3]), | |
1920 | .so(sout[2]), | |
1921 | .reset(reset), | |
1922 | .q(dout[2]) | |
1923 | ); | |
1924 | cl_a1_msff_syrst_4x d0_3 ( | |
1925 | .l1clk(l1clk), | |
1926 | .siclk(siclk), | |
1927 | .soclk(soclk), | |
1928 | .d(fdin[3]), | |
1929 | .si(sout[4]), | |
1930 | .so(sout[3]), | |
1931 | .reset(reset), | |
1932 | .q(dout[3]) | |
1933 | ); | |
1934 | cl_a1_msff_syrst_4x d0_4 ( | |
1935 | .l1clk(l1clk), | |
1936 | .siclk(siclk), | |
1937 | .soclk(soclk), | |
1938 | .d(fdin[4]), | |
1939 | .si(sout[5]), | |
1940 | .so(sout[4]), | |
1941 | .reset(reset), | |
1942 | .q(dout[4]) | |
1943 | ); | |
1944 | cl_a1_msff_syrst_4x d0_5 ( | |
1945 | .l1clk(l1clk), | |
1946 | .siclk(siclk), | |
1947 | .soclk(soclk), | |
1948 | .d(fdin[5]), | |
1949 | .si(sout[6]), | |
1950 | .so(sout[5]), | |
1951 | .reset(reset), | |
1952 | .q(dout[5]) | |
1953 | ); | |
1954 | cl_a1_msff_syrst_4x d0_6 ( | |
1955 | .l1clk(l1clk), | |
1956 | .siclk(siclk), | |
1957 | .soclk(soclk), | |
1958 | .d(fdin[6]), | |
1959 | .si(sout[7]), | |
1960 | .so(sout[6]), | |
1961 | .reset(reset), | |
1962 | .q(dout[6]) | |
1963 | ); | |
1964 | cl_a1_msff_syrst_4x d0_7 ( | |
1965 | .l1clk(l1clk), | |
1966 | .siclk(siclk), | |
1967 | .soclk(soclk), | |
1968 | .d(fdin[7]), | |
1969 | .si(sout[8]), | |
1970 | .so(sout[7]), | |
1971 | .reset(reset), | |
1972 | .q(dout[7]) | |
1973 | ); | |
1974 | cl_a1_msff_syrst_4x d0_8 ( | |
1975 | .l1clk(l1clk), | |
1976 | .siclk(siclk), | |
1977 | .soclk(soclk), | |
1978 | .d(fdin[8]), | |
1979 | .si(sout[9]), | |
1980 | .so(sout[8]), | |
1981 | .reset(reset), | |
1982 | .q(dout[8]) | |
1983 | ); | |
1984 | cl_a1_msff_syrst_4x d0_9 ( | |
1985 | .l1clk(l1clk), | |
1986 | .siclk(siclk), | |
1987 | .soclk(soclk), | |
1988 | .d(fdin[9]), | |
1989 | .si(sout[10]), | |
1990 | .so(sout[9]), | |
1991 | .reset(reset), | |
1992 | .q(dout[9]) | |
1993 | ); | |
1994 | cl_a1_msff_syrst_4x d0_10 ( | |
1995 | .l1clk(l1clk), | |
1996 | .siclk(siclk), | |
1997 | .soclk(soclk), | |
1998 | .d(fdin[10]), | |
1999 | .si(sout[11]), | |
2000 | .so(sout[10]), | |
2001 | .reset(reset), | |
2002 | .q(dout[10]) | |
2003 | ); | |
2004 | cl_a1_msff_syrst_4x d0_11 ( | |
2005 | .l1clk(l1clk), | |
2006 | .siclk(siclk), | |
2007 | .soclk(soclk), | |
2008 | .d(fdin[11]), | |
2009 | .si(scan_in), | |
2010 | .so(sout[11]), | |
2011 | .reset(reset), | |
2012 | .q(dout[11]) | |
2013 | ); | |
2014 | ||
2015 | ||
2016 | ||
2017 | ||
2018 | endmodule | |
2019 | ||
2020 | ||
2021 | ||
2022 | ||
2023 | ||
2024 | ||
2025 | ||
2026 | ||
2027 | ||
2028 | ||
2029 | ||
2030 | ||
2031 | ||
2032 | // any PARAMS parms go into naming of macro | |
2033 | ||
2034 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_40 ( | |
2035 | din, | |
2036 | reset, | |
2037 | l1clk, | |
2038 | scan_in, | |
2039 | siclk, | |
2040 | soclk, | |
2041 | dout, | |
2042 | scan_out); | |
2043 | wire [39:0] fdin; | |
2044 | wire [39:1] sout; | |
2045 | ||
2046 | input [39:0] din; | |
2047 | input reset; | |
2048 | input l1clk; | |
2049 | input scan_in; | |
2050 | ||
2051 | ||
2052 | input siclk; | |
2053 | input soclk; | |
2054 | ||
2055 | output [39:0] dout; | |
2056 | output scan_out; | |
2057 | assign fdin[39:0] = din[39:0] & {40 {reset}}; | |
2058 | ||
2059 | ||
2060 | ||
2061 | ||
2062 | ||
2063 | ||
2064 | ||
2065 | ||
2066 | ||
2067 | ||
2068 | ||
2069 | ||
2070 | ||
2071 | ||
2072 | ||
2073 | ||
2074 | ||
2075 | cl_a1_msff_syrst_4x d0_0 ( | |
2076 | .l1clk(l1clk), | |
2077 | .siclk(siclk), | |
2078 | .soclk(soclk), | |
2079 | .d(fdin[0]), | |
2080 | .si(sout[1]), | |
2081 | .so(scan_out), | |
2082 | .reset(reset), | |
2083 | .q(dout[0]) | |
2084 | ); | |
2085 | cl_a1_msff_syrst_4x d0_1 ( | |
2086 | .l1clk(l1clk), | |
2087 | .siclk(siclk), | |
2088 | .soclk(soclk), | |
2089 | .d(fdin[1]), | |
2090 | .si(sout[2]), | |
2091 | .so(sout[1]), | |
2092 | .reset(reset), | |
2093 | .q(dout[1]) | |
2094 | ); | |
2095 | cl_a1_msff_syrst_4x d0_2 ( | |
2096 | .l1clk(l1clk), | |
2097 | .siclk(siclk), | |
2098 | .soclk(soclk), | |
2099 | .d(fdin[2]), | |
2100 | .si(sout[3]), | |
2101 | .so(sout[2]), | |
2102 | .reset(reset), | |
2103 | .q(dout[2]) | |
2104 | ); | |
2105 | cl_a1_msff_syrst_4x d0_3 ( | |
2106 | .l1clk(l1clk), | |
2107 | .siclk(siclk), | |
2108 | .soclk(soclk), | |
2109 | .d(fdin[3]), | |
2110 | .si(sout[4]), | |
2111 | .so(sout[3]), | |
2112 | .reset(reset), | |
2113 | .q(dout[3]) | |
2114 | ); | |
2115 | cl_a1_msff_syrst_4x d0_4 ( | |
2116 | .l1clk(l1clk), | |
2117 | .siclk(siclk), | |
2118 | .soclk(soclk), | |
2119 | .d(fdin[4]), | |
2120 | .si(sout[5]), | |
2121 | .so(sout[4]), | |
2122 | .reset(reset), | |
2123 | .q(dout[4]) | |
2124 | ); | |
2125 | cl_a1_msff_syrst_4x d0_5 ( | |
2126 | .l1clk(l1clk), | |
2127 | .siclk(siclk), | |
2128 | .soclk(soclk), | |
2129 | .d(fdin[5]), | |
2130 | .si(sout[6]), | |
2131 | .so(sout[5]), | |
2132 | .reset(reset), | |
2133 | .q(dout[5]) | |
2134 | ); | |
2135 | cl_a1_msff_syrst_4x d0_6 ( | |
2136 | .l1clk(l1clk), | |
2137 | .siclk(siclk), | |
2138 | .soclk(soclk), | |
2139 | .d(fdin[6]), | |
2140 | .si(sout[7]), | |
2141 | .so(sout[6]), | |
2142 | .reset(reset), | |
2143 | .q(dout[6]) | |
2144 | ); | |
2145 | cl_a1_msff_syrst_4x d0_7 ( | |
2146 | .l1clk(l1clk), | |
2147 | .siclk(siclk), | |
2148 | .soclk(soclk), | |
2149 | .d(fdin[7]), | |
2150 | .si(sout[8]), | |
2151 | .so(sout[7]), | |
2152 | .reset(reset), | |
2153 | .q(dout[7]) | |
2154 | ); | |
2155 | cl_a1_msff_syrst_4x d0_8 ( | |
2156 | .l1clk(l1clk), | |
2157 | .siclk(siclk), | |
2158 | .soclk(soclk), | |
2159 | .d(fdin[8]), | |
2160 | .si(sout[9]), | |
2161 | .so(sout[8]), | |
2162 | .reset(reset), | |
2163 | .q(dout[8]) | |
2164 | ); | |
2165 | cl_a1_msff_syrst_4x d0_9 ( | |
2166 | .l1clk(l1clk), | |
2167 | .siclk(siclk), | |
2168 | .soclk(soclk), | |
2169 | .d(fdin[9]), | |
2170 | .si(sout[10]), | |
2171 | .so(sout[9]), | |
2172 | .reset(reset), | |
2173 | .q(dout[9]) | |
2174 | ); | |
2175 | cl_a1_msff_syrst_4x d0_10 ( | |
2176 | .l1clk(l1clk), | |
2177 | .siclk(siclk), | |
2178 | .soclk(soclk), | |
2179 | .d(fdin[10]), | |
2180 | .si(sout[11]), | |
2181 | .so(sout[10]), | |
2182 | .reset(reset), | |
2183 | .q(dout[10]) | |
2184 | ); | |
2185 | cl_a1_msff_syrst_4x d0_11 ( | |
2186 | .l1clk(l1clk), | |
2187 | .siclk(siclk), | |
2188 | .soclk(soclk), | |
2189 | .d(fdin[11]), | |
2190 | .si(sout[12]), | |
2191 | .so(sout[11]), | |
2192 | .reset(reset), | |
2193 | .q(dout[11]) | |
2194 | ); | |
2195 | cl_a1_msff_syrst_4x d0_12 ( | |
2196 | .l1clk(l1clk), | |
2197 | .siclk(siclk), | |
2198 | .soclk(soclk), | |
2199 | .d(fdin[12]), | |
2200 | .si(sout[13]), | |
2201 | .so(sout[12]), | |
2202 | .reset(reset), | |
2203 | .q(dout[12]) | |
2204 | ); | |
2205 | cl_a1_msff_syrst_4x d0_13 ( | |
2206 | .l1clk(l1clk), | |
2207 | .siclk(siclk), | |
2208 | .soclk(soclk), | |
2209 | .d(fdin[13]), | |
2210 | .si(sout[14]), | |
2211 | .so(sout[13]), | |
2212 | .reset(reset), | |
2213 | .q(dout[13]) | |
2214 | ); | |
2215 | cl_a1_msff_syrst_4x d0_14 ( | |
2216 | .l1clk(l1clk), | |
2217 | .siclk(siclk), | |
2218 | .soclk(soclk), | |
2219 | .d(fdin[14]), | |
2220 | .si(sout[15]), | |
2221 | .so(sout[14]), | |
2222 | .reset(reset), | |
2223 | .q(dout[14]) | |
2224 | ); | |
2225 | cl_a1_msff_syrst_4x d0_15 ( | |
2226 | .l1clk(l1clk), | |
2227 | .siclk(siclk), | |
2228 | .soclk(soclk), | |
2229 | .d(fdin[15]), | |
2230 | .si(sout[16]), | |
2231 | .so(sout[15]), | |
2232 | .reset(reset), | |
2233 | .q(dout[15]) | |
2234 | ); | |
2235 | cl_a1_msff_syrst_4x d0_16 ( | |
2236 | .l1clk(l1clk), | |
2237 | .siclk(siclk), | |
2238 | .soclk(soclk), | |
2239 | .d(fdin[16]), | |
2240 | .si(sout[17]), | |
2241 | .so(sout[16]), | |
2242 | .reset(reset), | |
2243 | .q(dout[16]) | |
2244 | ); | |
2245 | cl_a1_msff_syrst_4x d0_17 ( | |
2246 | .l1clk(l1clk), | |
2247 | .siclk(siclk), | |
2248 | .soclk(soclk), | |
2249 | .d(fdin[17]), | |
2250 | .si(sout[18]), | |
2251 | .so(sout[17]), | |
2252 | .reset(reset), | |
2253 | .q(dout[17]) | |
2254 | ); | |
2255 | cl_a1_msff_syrst_4x d0_18 ( | |
2256 | .l1clk(l1clk), | |
2257 | .siclk(siclk), | |
2258 | .soclk(soclk), | |
2259 | .d(fdin[18]), | |
2260 | .si(sout[19]), | |
2261 | .so(sout[18]), | |
2262 | .reset(reset), | |
2263 | .q(dout[18]) | |
2264 | ); | |
2265 | cl_a1_msff_syrst_4x d0_19 ( | |
2266 | .l1clk(l1clk), | |
2267 | .siclk(siclk), | |
2268 | .soclk(soclk), | |
2269 | .d(fdin[19]), | |
2270 | .si(sout[20]), | |
2271 | .so(sout[19]), | |
2272 | .reset(reset), | |
2273 | .q(dout[19]) | |
2274 | ); | |
2275 | cl_a1_msff_syrst_4x d0_20 ( | |
2276 | .l1clk(l1clk), | |
2277 | .siclk(siclk), | |
2278 | .soclk(soclk), | |
2279 | .d(fdin[20]), | |
2280 | .si(sout[21]), | |
2281 | .so(sout[20]), | |
2282 | .reset(reset), | |
2283 | .q(dout[20]) | |
2284 | ); | |
2285 | cl_a1_msff_syrst_4x d0_21 ( | |
2286 | .l1clk(l1clk), | |
2287 | .siclk(siclk), | |
2288 | .soclk(soclk), | |
2289 | .d(fdin[21]), | |
2290 | .si(sout[22]), | |
2291 | .so(sout[21]), | |
2292 | .reset(reset), | |
2293 | .q(dout[21]) | |
2294 | ); | |
2295 | cl_a1_msff_syrst_4x d0_22 ( | |
2296 | .l1clk(l1clk), | |
2297 | .siclk(siclk), | |
2298 | .soclk(soclk), | |
2299 | .d(fdin[22]), | |
2300 | .si(sout[23]), | |
2301 | .so(sout[22]), | |
2302 | .reset(reset), | |
2303 | .q(dout[22]) | |
2304 | ); | |
2305 | cl_a1_msff_syrst_4x d0_23 ( | |
2306 | .l1clk(l1clk), | |
2307 | .siclk(siclk), | |
2308 | .soclk(soclk), | |
2309 | .d(fdin[23]), | |
2310 | .si(sout[24]), | |
2311 | .so(sout[23]), | |
2312 | .reset(reset), | |
2313 | .q(dout[23]) | |
2314 | ); | |
2315 | cl_a1_msff_syrst_4x d0_24 ( | |
2316 | .l1clk(l1clk), | |
2317 | .siclk(siclk), | |
2318 | .soclk(soclk), | |
2319 | .d(fdin[24]), | |
2320 | .si(sout[25]), | |
2321 | .so(sout[24]), | |
2322 | .reset(reset), | |
2323 | .q(dout[24]) | |
2324 | ); | |
2325 | cl_a1_msff_syrst_4x d0_25 ( | |
2326 | .l1clk(l1clk), | |
2327 | .siclk(siclk), | |
2328 | .soclk(soclk), | |
2329 | .d(fdin[25]), | |
2330 | .si(sout[26]), | |
2331 | .so(sout[25]), | |
2332 | .reset(reset), | |
2333 | .q(dout[25]) | |
2334 | ); | |
2335 | cl_a1_msff_syrst_4x d0_26 ( | |
2336 | .l1clk(l1clk), | |
2337 | .siclk(siclk), | |
2338 | .soclk(soclk), | |
2339 | .d(fdin[26]), | |
2340 | .si(sout[27]), | |
2341 | .so(sout[26]), | |
2342 | .reset(reset), | |
2343 | .q(dout[26]) | |
2344 | ); | |
2345 | cl_a1_msff_syrst_4x d0_27 ( | |
2346 | .l1clk(l1clk), | |
2347 | .siclk(siclk), | |
2348 | .soclk(soclk), | |
2349 | .d(fdin[27]), | |
2350 | .si(sout[28]), | |
2351 | .so(sout[27]), | |
2352 | .reset(reset), | |
2353 | .q(dout[27]) | |
2354 | ); | |
2355 | cl_a1_msff_syrst_4x d0_28 ( | |
2356 | .l1clk(l1clk), | |
2357 | .siclk(siclk), | |
2358 | .soclk(soclk), | |
2359 | .d(fdin[28]), | |
2360 | .si(sout[29]), | |
2361 | .so(sout[28]), | |
2362 | .reset(reset), | |
2363 | .q(dout[28]) | |
2364 | ); | |
2365 | cl_a1_msff_syrst_4x d0_29 ( | |
2366 | .l1clk(l1clk), | |
2367 | .siclk(siclk), | |
2368 | .soclk(soclk), | |
2369 | .d(fdin[29]), | |
2370 | .si(sout[30]), | |
2371 | .so(sout[29]), | |
2372 | .reset(reset), | |
2373 | .q(dout[29]) | |
2374 | ); | |
2375 | cl_a1_msff_syrst_4x d0_30 ( | |
2376 | .l1clk(l1clk), | |
2377 | .siclk(siclk), | |
2378 | .soclk(soclk), | |
2379 | .d(fdin[30]), | |
2380 | .si(sout[31]), | |
2381 | .so(sout[30]), | |
2382 | .reset(reset), | |
2383 | .q(dout[30]) | |
2384 | ); | |
2385 | cl_a1_msff_syrst_4x d0_31 ( | |
2386 | .l1clk(l1clk), | |
2387 | .siclk(siclk), | |
2388 | .soclk(soclk), | |
2389 | .d(fdin[31]), | |
2390 | .si(sout[32]), | |
2391 | .so(sout[31]), | |
2392 | .reset(reset), | |
2393 | .q(dout[31]) | |
2394 | ); | |
2395 | cl_a1_msff_syrst_4x d0_32 ( | |
2396 | .l1clk(l1clk), | |
2397 | .siclk(siclk), | |
2398 | .soclk(soclk), | |
2399 | .d(fdin[32]), | |
2400 | .si(sout[33]), | |
2401 | .so(sout[32]), | |
2402 | .reset(reset), | |
2403 | .q(dout[32]) | |
2404 | ); | |
2405 | cl_a1_msff_syrst_4x d0_33 ( | |
2406 | .l1clk(l1clk), | |
2407 | .siclk(siclk), | |
2408 | .soclk(soclk), | |
2409 | .d(fdin[33]), | |
2410 | .si(sout[34]), | |
2411 | .so(sout[33]), | |
2412 | .reset(reset), | |
2413 | .q(dout[33]) | |
2414 | ); | |
2415 | cl_a1_msff_syrst_4x d0_34 ( | |
2416 | .l1clk(l1clk), | |
2417 | .siclk(siclk), | |
2418 | .soclk(soclk), | |
2419 | .d(fdin[34]), | |
2420 | .si(sout[35]), | |
2421 | .so(sout[34]), | |
2422 | .reset(reset), | |
2423 | .q(dout[34]) | |
2424 | ); | |
2425 | cl_a1_msff_syrst_4x d0_35 ( | |
2426 | .l1clk(l1clk), | |
2427 | .siclk(siclk), | |
2428 | .soclk(soclk), | |
2429 | .d(fdin[35]), | |
2430 | .si(sout[36]), | |
2431 | .so(sout[35]), | |
2432 | .reset(reset), | |
2433 | .q(dout[35]) | |
2434 | ); | |
2435 | cl_a1_msff_syrst_4x d0_36 ( | |
2436 | .l1clk(l1clk), | |
2437 | .siclk(siclk), | |
2438 | .soclk(soclk), | |
2439 | .d(fdin[36]), | |
2440 | .si(sout[37]), | |
2441 | .so(sout[36]), | |
2442 | .reset(reset), | |
2443 | .q(dout[36]) | |
2444 | ); | |
2445 | cl_a1_msff_syrst_4x d0_37 ( | |
2446 | .l1clk(l1clk), | |
2447 | .siclk(siclk), | |
2448 | .soclk(soclk), | |
2449 | .d(fdin[37]), | |
2450 | .si(sout[38]), | |
2451 | .so(sout[37]), | |
2452 | .reset(reset), | |
2453 | .q(dout[37]) | |
2454 | ); | |
2455 | cl_a1_msff_syrst_4x d0_38 ( | |
2456 | .l1clk(l1clk), | |
2457 | .siclk(siclk), | |
2458 | .soclk(soclk), | |
2459 | .d(fdin[38]), | |
2460 | .si(sout[39]), | |
2461 | .so(sout[38]), | |
2462 | .reset(reset), | |
2463 | .q(dout[38]) | |
2464 | ); | |
2465 | cl_a1_msff_syrst_4x d0_39 ( | |
2466 | .l1clk(l1clk), | |
2467 | .siclk(siclk), | |
2468 | .soclk(soclk), | |
2469 | .d(fdin[39]), | |
2470 | .si(scan_in), | |
2471 | .so(sout[39]), | |
2472 | .reset(reset), | |
2473 | .q(dout[39]) | |
2474 | ); | |
2475 | ||
2476 | ||
2477 | ||
2478 | ||
2479 | endmodule | |
2480 | ||
2481 | ||
2482 | ||
2483 | ||
2484 | ||
2485 | ||
2486 | ||
2487 | ||
2488 | ||
2489 | ||
2490 | ||
2491 | ||
2492 | ||
2493 | // any PARAMS parms go into naming of macro | |
2494 | ||
2495 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_26 ( | |
2496 | din, | |
2497 | reset, | |
2498 | l1clk, | |
2499 | scan_in, | |
2500 | siclk, | |
2501 | soclk, | |
2502 | dout, | |
2503 | scan_out); | |
2504 | wire [25:0] fdin; | |
2505 | wire [25:1] sout; | |
2506 | ||
2507 | input [25:0] din; | |
2508 | input reset; | |
2509 | input l1clk; | |
2510 | input scan_in; | |
2511 | ||
2512 | ||
2513 | input siclk; | |
2514 | input soclk; | |
2515 | ||
2516 | output [25:0] dout; | |
2517 | output scan_out; | |
2518 | assign fdin[25:0] = din[25:0] & {26 {reset}}; | |
2519 | ||
2520 | ||
2521 | ||
2522 | ||
2523 | ||
2524 | ||
2525 | ||
2526 | ||
2527 | ||
2528 | ||
2529 | ||
2530 | ||
2531 | ||
2532 | ||
2533 | ||
2534 | ||
2535 | ||
2536 | cl_a1_msff_syrst_4x d0_0 ( | |
2537 | .l1clk(l1clk), | |
2538 | .siclk(siclk), | |
2539 | .soclk(soclk), | |
2540 | .d(fdin[0]), | |
2541 | .si(sout[1]), | |
2542 | .so(scan_out), | |
2543 | .reset(reset), | |
2544 | .q(dout[0]) | |
2545 | ); | |
2546 | cl_a1_msff_syrst_4x d0_1 ( | |
2547 | .l1clk(l1clk), | |
2548 | .siclk(siclk), | |
2549 | .soclk(soclk), | |
2550 | .d(fdin[1]), | |
2551 | .si(sout[2]), | |
2552 | .so(sout[1]), | |
2553 | .reset(reset), | |
2554 | .q(dout[1]) | |
2555 | ); | |
2556 | cl_a1_msff_syrst_4x d0_2 ( | |
2557 | .l1clk(l1clk), | |
2558 | .siclk(siclk), | |
2559 | .soclk(soclk), | |
2560 | .d(fdin[2]), | |
2561 | .si(sout[3]), | |
2562 | .so(sout[2]), | |
2563 | .reset(reset), | |
2564 | .q(dout[2]) | |
2565 | ); | |
2566 | cl_a1_msff_syrst_4x d0_3 ( | |
2567 | .l1clk(l1clk), | |
2568 | .siclk(siclk), | |
2569 | .soclk(soclk), | |
2570 | .d(fdin[3]), | |
2571 | .si(sout[4]), | |
2572 | .so(sout[3]), | |
2573 | .reset(reset), | |
2574 | .q(dout[3]) | |
2575 | ); | |
2576 | cl_a1_msff_syrst_4x d0_4 ( | |
2577 | .l1clk(l1clk), | |
2578 | .siclk(siclk), | |
2579 | .soclk(soclk), | |
2580 | .d(fdin[4]), | |
2581 | .si(sout[5]), | |
2582 | .so(sout[4]), | |
2583 | .reset(reset), | |
2584 | .q(dout[4]) | |
2585 | ); | |
2586 | cl_a1_msff_syrst_4x d0_5 ( | |
2587 | .l1clk(l1clk), | |
2588 | .siclk(siclk), | |
2589 | .soclk(soclk), | |
2590 | .d(fdin[5]), | |
2591 | .si(sout[6]), | |
2592 | .so(sout[5]), | |
2593 | .reset(reset), | |
2594 | .q(dout[5]) | |
2595 | ); | |
2596 | cl_a1_msff_syrst_4x d0_6 ( | |
2597 | .l1clk(l1clk), | |
2598 | .siclk(siclk), | |
2599 | .soclk(soclk), | |
2600 | .d(fdin[6]), | |
2601 | .si(sout[7]), | |
2602 | .so(sout[6]), | |
2603 | .reset(reset), | |
2604 | .q(dout[6]) | |
2605 | ); | |
2606 | cl_a1_msff_syrst_4x d0_7 ( | |
2607 | .l1clk(l1clk), | |
2608 | .siclk(siclk), | |
2609 | .soclk(soclk), | |
2610 | .d(fdin[7]), | |
2611 | .si(sout[8]), | |
2612 | .so(sout[7]), | |
2613 | .reset(reset), | |
2614 | .q(dout[7]) | |
2615 | ); | |
2616 | cl_a1_msff_syrst_4x d0_8 ( | |
2617 | .l1clk(l1clk), | |
2618 | .siclk(siclk), | |
2619 | .soclk(soclk), | |
2620 | .d(fdin[8]), | |
2621 | .si(sout[9]), | |
2622 | .so(sout[8]), | |
2623 | .reset(reset), | |
2624 | .q(dout[8]) | |
2625 | ); | |
2626 | cl_a1_msff_syrst_4x d0_9 ( | |
2627 | .l1clk(l1clk), | |
2628 | .siclk(siclk), | |
2629 | .soclk(soclk), | |
2630 | .d(fdin[9]), | |
2631 | .si(sout[10]), | |
2632 | .so(sout[9]), | |
2633 | .reset(reset), | |
2634 | .q(dout[9]) | |
2635 | ); | |
2636 | cl_a1_msff_syrst_4x d0_10 ( | |
2637 | .l1clk(l1clk), | |
2638 | .siclk(siclk), | |
2639 | .soclk(soclk), | |
2640 | .d(fdin[10]), | |
2641 | .si(sout[11]), | |
2642 | .so(sout[10]), | |
2643 | .reset(reset), | |
2644 | .q(dout[10]) | |
2645 | ); | |
2646 | cl_a1_msff_syrst_4x d0_11 ( | |
2647 | .l1clk(l1clk), | |
2648 | .siclk(siclk), | |
2649 | .soclk(soclk), | |
2650 | .d(fdin[11]), | |
2651 | .si(sout[12]), | |
2652 | .so(sout[11]), | |
2653 | .reset(reset), | |
2654 | .q(dout[11]) | |
2655 | ); | |
2656 | cl_a1_msff_syrst_4x d0_12 ( | |
2657 | .l1clk(l1clk), | |
2658 | .siclk(siclk), | |
2659 | .soclk(soclk), | |
2660 | .d(fdin[12]), | |
2661 | .si(sout[13]), | |
2662 | .so(sout[12]), | |
2663 | .reset(reset), | |
2664 | .q(dout[12]) | |
2665 | ); | |
2666 | cl_a1_msff_syrst_4x d0_13 ( | |
2667 | .l1clk(l1clk), | |
2668 | .siclk(siclk), | |
2669 | .soclk(soclk), | |
2670 | .d(fdin[13]), | |
2671 | .si(sout[14]), | |
2672 | .so(sout[13]), | |
2673 | .reset(reset), | |
2674 | .q(dout[13]) | |
2675 | ); | |
2676 | cl_a1_msff_syrst_4x d0_14 ( | |
2677 | .l1clk(l1clk), | |
2678 | .siclk(siclk), | |
2679 | .soclk(soclk), | |
2680 | .d(fdin[14]), | |
2681 | .si(sout[15]), | |
2682 | .so(sout[14]), | |
2683 | .reset(reset), | |
2684 | .q(dout[14]) | |
2685 | ); | |
2686 | cl_a1_msff_syrst_4x d0_15 ( | |
2687 | .l1clk(l1clk), | |
2688 | .siclk(siclk), | |
2689 | .soclk(soclk), | |
2690 | .d(fdin[15]), | |
2691 | .si(sout[16]), | |
2692 | .so(sout[15]), | |
2693 | .reset(reset), | |
2694 | .q(dout[15]) | |
2695 | ); | |
2696 | cl_a1_msff_syrst_4x d0_16 ( | |
2697 | .l1clk(l1clk), | |
2698 | .siclk(siclk), | |
2699 | .soclk(soclk), | |
2700 | .d(fdin[16]), | |
2701 | .si(sout[17]), | |
2702 | .so(sout[16]), | |
2703 | .reset(reset), | |
2704 | .q(dout[16]) | |
2705 | ); | |
2706 | cl_a1_msff_syrst_4x d0_17 ( | |
2707 | .l1clk(l1clk), | |
2708 | .siclk(siclk), | |
2709 | .soclk(soclk), | |
2710 | .d(fdin[17]), | |
2711 | .si(sout[18]), | |
2712 | .so(sout[17]), | |
2713 | .reset(reset), | |
2714 | .q(dout[17]) | |
2715 | ); | |
2716 | cl_a1_msff_syrst_4x d0_18 ( | |
2717 | .l1clk(l1clk), | |
2718 | .siclk(siclk), | |
2719 | .soclk(soclk), | |
2720 | .d(fdin[18]), | |
2721 | .si(sout[19]), | |
2722 | .so(sout[18]), | |
2723 | .reset(reset), | |
2724 | .q(dout[18]) | |
2725 | ); | |
2726 | cl_a1_msff_syrst_4x d0_19 ( | |
2727 | .l1clk(l1clk), | |
2728 | .siclk(siclk), | |
2729 | .soclk(soclk), | |
2730 | .d(fdin[19]), | |
2731 | .si(sout[20]), | |
2732 | .so(sout[19]), | |
2733 | .reset(reset), | |
2734 | .q(dout[19]) | |
2735 | ); | |
2736 | cl_a1_msff_syrst_4x d0_20 ( | |
2737 | .l1clk(l1clk), | |
2738 | .siclk(siclk), | |
2739 | .soclk(soclk), | |
2740 | .d(fdin[20]), | |
2741 | .si(sout[21]), | |
2742 | .so(sout[20]), | |
2743 | .reset(reset), | |
2744 | .q(dout[20]) | |
2745 | ); | |
2746 | cl_a1_msff_syrst_4x d0_21 ( | |
2747 | .l1clk(l1clk), | |
2748 | .siclk(siclk), | |
2749 | .soclk(soclk), | |
2750 | .d(fdin[21]), | |
2751 | .si(sout[22]), | |
2752 | .so(sout[21]), | |
2753 | .reset(reset), | |
2754 | .q(dout[21]) | |
2755 | ); | |
2756 | cl_a1_msff_syrst_4x d0_22 ( | |
2757 | .l1clk(l1clk), | |
2758 | .siclk(siclk), | |
2759 | .soclk(soclk), | |
2760 | .d(fdin[22]), | |
2761 | .si(sout[23]), | |
2762 | .so(sout[22]), | |
2763 | .reset(reset), | |
2764 | .q(dout[22]) | |
2765 | ); | |
2766 | cl_a1_msff_syrst_4x d0_23 ( | |
2767 | .l1clk(l1clk), | |
2768 | .siclk(siclk), | |
2769 | .soclk(soclk), | |
2770 | .d(fdin[23]), | |
2771 | .si(sout[24]), | |
2772 | .so(sout[23]), | |
2773 | .reset(reset), | |
2774 | .q(dout[23]) | |
2775 | ); | |
2776 | cl_a1_msff_syrst_4x d0_24 ( | |
2777 | .l1clk(l1clk), | |
2778 | .siclk(siclk), | |
2779 | .soclk(soclk), | |
2780 | .d(fdin[24]), | |
2781 | .si(sout[25]), | |
2782 | .so(sout[24]), | |
2783 | .reset(reset), | |
2784 | .q(dout[24]) | |
2785 | ); | |
2786 | cl_a1_msff_syrst_4x d0_25 ( | |
2787 | .l1clk(l1clk), | |
2788 | .siclk(siclk), | |
2789 | .soclk(soclk), | |
2790 | .d(fdin[25]), | |
2791 | .si(scan_in), | |
2792 | .so(sout[25]), | |
2793 | .reset(reset), | |
2794 | .q(dout[25]) | |
2795 | ); | |
2796 | ||
2797 | ||
2798 | ||
2799 | ||
2800 | endmodule | |
2801 | ||
2802 | ||
2803 | ||
2804 | ||
2805 | ||
2806 | ||
2807 | ||
2808 | ||
2809 | ||
2810 | ||
2811 | ||
2812 | ||
2813 | ||
2814 | // any PARAMS parms go into naming of macro | |
2815 | ||
2816 | module dmu_mb0_msff_ctl_macro__library_a1__reset_1__width_6 ( | |
2817 | din, | |
2818 | reset, | |
2819 | l1clk, | |
2820 | scan_in, | |
2821 | siclk, | |
2822 | soclk, | |
2823 | dout, | |
2824 | scan_out); | |
2825 | wire [5:0] fdin; | |
2826 | wire [5:1] sout; | |
2827 | ||
2828 | input [5:0] din; | |
2829 | input reset; | |
2830 | input l1clk; | |
2831 | input scan_in; | |
2832 | ||
2833 | ||
2834 | input siclk; | |
2835 | input soclk; | |
2836 | ||
2837 | output [5:0] dout; | |
2838 | output scan_out; | |
2839 | assign fdin[5:0] = din[5:0] & {6 {reset}}; | |
2840 | ||
2841 | ||
2842 | ||
2843 | ||
2844 | ||
2845 | ||
2846 | ||
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | ||
2853 | ||
2854 | ||
2855 | ||
2856 | ||
2857 | cl_a1_msff_syrst_4x d0_0 ( | |
2858 | .l1clk(l1clk), | |
2859 | .siclk(siclk), | |
2860 | .soclk(soclk), | |
2861 | .d(fdin[0]), | |
2862 | .si(sout[1]), | |
2863 | .so(scan_out), | |
2864 | .reset(reset), | |
2865 | .q(dout[0]) | |
2866 | ); | |
2867 | cl_a1_msff_syrst_4x d0_1 ( | |
2868 | .l1clk(l1clk), | |
2869 | .siclk(siclk), | |
2870 | .soclk(soclk), | |
2871 | .d(fdin[1]), | |
2872 | .si(sout[2]), | |
2873 | .so(sout[1]), | |
2874 | .reset(reset), | |
2875 | .q(dout[1]) | |
2876 | ); | |
2877 | cl_a1_msff_syrst_4x d0_2 ( | |
2878 | .l1clk(l1clk), | |
2879 | .siclk(siclk), | |
2880 | .soclk(soclk), | |
2881 | .d(fdin[2]), | |
2882 | .si(sout[3]), | |
2883 | .so(sout[2]), | |
2884 | .reset(reset), | |
2885 | .q(dout[2]) | |
2886 | ); | |
2887 | cl_a1_msff_syrst_4x d0_3 ( | |
2888 | .l1clk(l1clk), | |
2889 | .siclk(siclk), | |
2890 | .soclk(soclk), | |
2891 | .d(fdin[3]), | |
2892 | .si(sout[4]), | |
2893 | .so(sout[3]), | |
2894 | .reset(reset), | |
2895 | .q(dout[3]) | |
2896 | ); | |
2897 | cl_a1_msff_syrst_4x d0_4 ( | |
2898 | .l1clk(l1clk), | |
2899 | .siclk(siclk), | |
2900 | .soclk(soclk), | |
2901 | .d(fdin[4]), | |
2902 | .si(sout[5]), | |
2903 | .so(sout[4]), | |
2904 | .reset(reset), | |
2905 | .q(dout[4]) | |
2906 | ); | |
2907 | cl_a1_msff_syrst_4x d0_5 ( | |
2908 | .l1clk(l1clk), | |
2909 | .siclk(siclk), | |
2910 | .soclk(soclk), | |
2911 | .d(fdin[5]), | |
2912 | .si(scan_in), | |
2913 | .so(sout[5]), | |
2914 | .reset(reset), | |
2915 | .q(dout[5]) | |
2916 | ); | |
2917 | ||
2918 | ||
2919 | ||
2920 | ||
2921 | endmodule | |
2922 | ||
2923 | ||
2924 | ||
2925 | ||
2926 | ||
2927 | ||
2928 | ||
2929 |