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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_csr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_mmu_csr_csr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
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19// along with this program; if not, write to the Free Software
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21//
22// For the avoidance of doubt, and except that if any non-GPL license
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24// the General Public License version 2 (GPLv2) at this time for any
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_mmu_csr_csr
36 (
37 clk,
38 csrbus_addr,
39 csrbus_wr_data,
40 csrbus_wr,
41 csrbus_valid,
42 csrbus_mapped,
43 csrbus_done,
44 csrbus_read_data,
45 rst_l,
46 por_l,
47 csrbus_src_bus,
48 csrbus_acc_vio,
49 instance_id,
50 ext_addr,
51 ext_wr,
52 ext_wr_data,
53 ctl_spares_hw_write,
54 ctl_paq_hw_write,
55 ctl_vaq_hw_write,
56 ctl_tpl_hw_write,
57 ctl_tip_hw_write,
58 ctl_tcm_hw_write,
59 ctl_sparec_hw_read,
60 ctl_pd_hw_read,
61 ctl_se_hw_read,
62 ctl_cm_hw_read,
63 ctl_busid_sel_hw_read,
64 ctl_sun4v_en_hw_read,
65 ctl_be_hw_read,
66 ctl_te_hw_read,
67 tsb_tb_hw_read,
68 tsb_ps_hw_read,
69 tsb_ts_hw_read,
70 inv_ext_select,
71 log_en_hw_read,
72 int_en_hw_read,
73 en_err_err_s_ext_read_data,
74 en_err_err_p_ext_read_data,
75 err_hw_set,
76 err_hw_read,
77 flta_va_hw_ld,
78 flta_va_hw_write,
79 flts_entry_hw_ld,
80 flts_entry_hw_write,
81 flts_type_hw_ld,
82 flts_type_hw_write,
83 flts_id_hw_ld,
84 flts_id_hw_write,
85 prfc_sel1_hw_read,
86 prfc_sel0_hw_read,
87 prf0_cnt_hw_write,
88 prf0_cnt_hw_read,
89 prf1_cnt_hw_write,
90 prf1_cnt_hw_read,
91 vtb_hw_acc_jtag_rd,
92 vtb_hw_acc_jtag_wr,
93 vtb_hw_acc_pio_slow_rd,
94 vtb_hw_acc_pio_slow_wr,
95 vtb_hw_acc_pio_med_rd,
96 vtb_hw_acc_pio_med_wr,
97 vtb_hw_acc_pio_fast_rd,
98 vtb_hw_acc_pio_fast_wr,
99 vtb_ext_select,
100 vtb_ext_read_data,
101 ptb_hw_acc_jtag_rd,
102 ptb_hw_acc_jtag_wr,
103 ptb_hw_acc_pio_slow_rd,
104 ptb_hw_acc_pio_slow_wr,
105 ptb_hw_acc_pio_med_rd,
106 ptb_hw_acc_pio_med_wr,
107 ptb_hw_acc_pio_fast_rd,
108 ptb_hw_acc_pio_fast_wr,
109 ptb_ext_select,
110 ptb_ext_read_data,
111 tdb_hw_acc_jtag_rd,
112 tdb_hw_acc_jtag_wr,
113 tdb_hw_acc_pio_slow_rd,
114 tdb_hw_acc_pio_slow_wr,
115 tdb_hw_acc_pio_med_rd,
116 tdb_hw_acc_pio_med_wr,
117 tdb_hw_acc_pio_fast_rd,
118 tdb_hw_acc_pio_fast_wr,
119 tdb_ext_select,
120 tdb_ext_read_data,
121 dev2iotsb_hw_acc_jtag_rd,
122 dev2iotsb_hw_acc_jtag_wr,
123 dev2iotsb_hw_acc_pio_slow_rd,
124 dev2iotsb_hw_acc_pio_slow_wr,
125 dev2iotsb_hw_acc_pio_med_rd,
126 dev2iotsb_hw_acc_pio_med_wr,
127 dev2iotsb_hw_acc_pio_fast_rd,
128 dev2iotsb_hw_acc_pio_fast_wr,
129 dev2iotsb_ext_select,
130 dev2iotsb_ext_read_data,
131 dev2iotsb_ext_done,
132 IotsbDesc_hw_acc_jtag_rd,
133 IotsbDesc_hw_acc_jtag_wr,
134 IotsbDesc_hw_acc_pio_slow_rd,
135 IotsbDesc_hw_acc_pio_slow_wr,
136 IotsbDesc_hw_acc_pio_med_rd,
137 IotsbDesc_hw_acc_pio_med_wr,
138 IotsbDesc_hw_acc_pio_fast_rd,
139 IotsbDesc_hw_acc_pio_fast_wr,
140 IotsbDesc_ext_select,
141 IotsbDesc_ext_read_data,
142 IotsbDesc_ext_done
143 );
144
145//====================================================
146// Polarity declarations
147//====================================================
148input clk; // Clock signal
149input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
150input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
151input csrbus_wr; // Read/Write signal
152input csrbus_valid; // Valid address
153output csrbus_mapped; // Address is mapped
154output csrbus_done; // Operation is done
155output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
156input rst_l; // Reset signal
157input por_l; // Reset signal
158input [1:0] csrbus_src_bus; // Source bus
159output csrbus_acc_vio; // Violation signal
160input instance_id; // Instance ID
161output [8:0] ext_addr; // External address bus for dcm csr
162output ext_wr; // When one, csr operation is a write. When zero, operation is a
163 // read.
164output [`FIRE_CSRBUS_DATA_WIDTH-1:0] ext_wr_data; // Provides SW write data for
165 // all external registers in
166 // default_grp
167input [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write;
168 // data bus for hw loading of ctl_spares.
169input ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
170input ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
171input ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
172input ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
173input [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
174 // loading of
175 // ctl_tcm.
176output [`FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC] ctl_sparec_hw_read;
177 // This signal provides the current value of ctl_sparec.
178output ctl_pd_hw_read; // This signal provides the current value of ctl_pd.
179output ctl_se_hw_read; // This signal provides the current value of ctl_se.
180output [`FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC] ctl_cm_hw_read; // This signal
181 // provides the
182 // current value of
183 // ctl_cm.
184output ctl_busid_sel_hw_read; // This signal provides the current value of
185 // ctl_busid_sel.
186output ctl_sun4v_en_hw_read; // This signal provides the current value of
187 // ctl_sun4v_en.
188output ctl_be_hw_read; // This signal provides the current value of ctl_be.
189output ctl_te_hw_read; // This signal provides the current value of ctl_te.
190output [`FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC] tsb_tb_hw_read; // This signal
191 // provides the
192 // current value of
193 // tsb_tb.
194output tsb_ps_hw_read; // This signal provides the current value of tsb_ps.
195output [`FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC] tsb_ts_hw_read; // This signal
196 // provides the
197 // current value of
198 // tsb_ts.
199output inv_ext_select; // When set, register inv is selected. This signal is a
200 // pulse.
201output [`FIRE_DLC_MMU_CSR_LOG_EN_INT_SLC] log_en_hw_read; // This signal
202 // provides the
203 // current value of
204 // log_en.
205output [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_hw_read; // This signal
206 // provides the
207 // current value of
208 // int_en.
209input [20:0] en_err_err_s_ext_read_data; // Ext read data (decode)
210input [20:0] en_err_err_p_ext_read_data; // Ext read data (decode)
211input [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_set; // Hardware set
212 // signal for
213 // err. When
214 // set err will
215 // be set to
216 // one.
217output [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_read; // This signal
218 // provides
219 // the current
220 // value of
221 // err.
222input flta_va_hw_ld; // Hardware load enable for flta_va. When set, <hw write
223 // signal> will be loaded into flta.
224input [`FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC] flta_va_hw_write; // data bus for hw
225 // loading of
226 // flta_va.
227input flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw
228 // write signal> will be loaded into flts.
229input [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write;
230 // data bus for hw loading of flts_entry.
231input flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw
232 // write signal> will be loaded into flts.
233input [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus
234 // for hw
235 // loading of
236 // flts_type.
237input flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write
238 // signal> will be loaded into flts.
239input [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw
240 // loading of
241 // flts_id.
242output [`FIRE_DLC_MMU_CSR_PRFC_SEL1_INT_SLC] prfc_sel1_hw_read; // This signal
243 // provides the
244 // current
245 // value of
246 // prfc_sel1.
247output [`FIRE_DLC_MMU_CSR_PRFC_SEL0_INT_SLC] prfc_sel0_hw_read; // This signal
248 // provides the
249 // current
250 // value of
251 // prfc_sel0.
252input [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_write; // data bus for
253 // hw loading of
254 // prf0_cnt.
255output [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_read; // This signal
256 // provides the
257 // current value
258 // of prf0_cnt.
259input [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_write; // data bus for
260 // hw loading of
261 // prf1_cnt.
262output [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_read; // This signal
263 // provides the
264 // current value
265 // of prf1_cnt.
266input vtb_hw_acc_jtag_rd; // This signal enables reading of register vtb by
267 // jtag.
268input vtb_hw_acc_jtag_wr; // This signal enables writing of register vtb by
269 // jtag.
270input vtb_hw_acc_pio_slow_rd; // This signal enables reading of register vtb
271 // by pio_slow.
272input vtb_hw_acc_pio_slow_wr; // This signal enables writing of register vtb
273 // by pio_slow.
274input vtb_hw_acc_pio_med_rd; // This signal enables reading of register vtb by
275 // pio_med.
276input vtb_hw_acc_pio_med_wr; // This signal enables writing of register vtb by
277 // pio_med.
278input vtb_hw_acc_pio_fast_rd; // This signal enables reading of register vtb
279 // by pio_fast.
280input vtb_hw_acc_pio_fast_wr; // This signal enables writing of register vtb
281 // by pio_fast.
282output vtb_ext_select; // When set, register vtb is selected. This signal is a
283 // pulse.
284input [`FIRE_CSRBUS_DATA_WIDTH-1:0] vtb_ext_read_data; // Read data from the
285 // external bypass
286 // register
287input ptb_hw_acc_jtag_rd; // This signal enables reading of register ptb by
288 // jtag.
289input ptb_hw_acc_jtag_wr; // This signal enables writing of register ptb by
290 // jtag.
291input ptb_hw_acc_pio_slow_rd; // This signal enables reading of register ptb
292 // by pio_slow.
293input ptb_hw_acc_pio_slow_wr; // This signal enables writing of register ptb
294 // by pio_slow.
295input ptb_hw_acc_pio_med_rd; // This signal enables reading of register ptb by
296 // pio_med.
297input ptb_hw_acc_pio_med_wr; // This signal enables writing of register ptb by
298 // pio_med.
299input ptb_hw_acc_pio_fast_rd; // This signal enables reading of register ptb
300 // by pio_fast.
301input ptb_hw_acc_pio_fast_wr; // This signal enables writing of register ptb
302 // by pio_fast.
303output ptb_ext_select; // When set, register ptb is selected. This signal is a
304 // pulse.
305input [`FIRE_CSRBUS_DATA_WIDTH-1:0] ptb_ext_read_data; // Read data from the
306 // external bypass
307 // register
308input tdb_hw_acc_jtag_rd; // This signal enables reading of register tdb by
309 // jtag.
310input tdb_hw_acc_jtag_wr; // This signal enables writing of register tdb by
311 // jtag.
312input tdb_hw_acc_pio_slow_rd; // This signal enables reading of register tdb
313 // by pio_slow.
314input tdb_hw_acc_pio_slow_wr; // This signal enables writing of register tdb
315 // by pio_slow.
316input tdb_hw_acc_pio_med_rd; // This signal enables reading of register tdb by
317 // pio_med.
318input tdb_hw_acc_pio_med_wr; // This signal enables writing of register tdb by
319 // pio_med.
320input tdb_hw_acc_pio_fast_rd; // This signal enables reading of register tdb
321 // by pio_fast.
322input tdb_hw_acc_pio_fast_wr; // This signal enables writing of register tdb
323 // by pio_fast.
324output tdb_ext_select; // When set, register tdb is selected. This signal is a
325 // pulse.
326input [`FIRE_CSRBUS_DATA_WIDTH-1:0] tdb_ext_read_data; // Read data from the
327 // external bypass
328 // register
329input dev2iotsb_hw_acc_jtag_rd; // This signal enables reading of register
330 // dev2iotsb by jtag.
331input dev2iotsb_hw_acc_jtag_wr; // This signal enables writing of register
332 // dev2iotsb by jtag.
333input dev2iotsb_hw_acc_pio_slow_rd; // This signal enables reading of register
334 // dev2iotsb by pio_slow.
335input dev2iotsb_hw_acc_pio_slow_wr; // This signal enables writing of register
336 // dev2iotsb by pio_slow.
337input dev2iotsb_hw_acc_pio_med_rd; // This signal enables reading of register
338 // dev2iotsb by pio_med.
339input dev2iotsb_hw_acc_pio_med_wr; // This signal enables writing of register
340 // dev2iotsb by pio_med.
341input dev2iotsb_hw_acc_pio_fast_rd; // This signal enables reading of register
342 // dev2iotsb by pio_fast.
343input dev2iotsb_hw_acc_pio_fast_wr; // This signal enables writing of register
344 // dev2iotsb by pio_fast.
345output dev2iotsb_ext_select; // When set, register dev2iotsb is selected. This
346 // signal is a pulse.
347input [`FIRE_CSRBUS_DATA_WIDTH-1:0] dev2iotsb_ext_read_data; // Read data from
348 // the external
349 // bypass
350 // register
351input dev2iotsb_ext_done; // This signal acknowledges read and write
352 // operations for register dev2iotsb. For read
353 // operations, it indicates that the
354 // dev2iotsb_ext_read_data signals are valid. For
355 // write operations, it indicates that the write
356 // operation is complete, and that <dcm>_ext_wr_data
357 // may be removed on the next cycle.
358input IotsbDesc_hw_acc_jtag_rd; // This signal enables reading of register
359 // IotsbDesc by jtag.
360input IotsbDesc_hw_acc_jtag_wr; // This signal enables writing of register
361 // IotsbDesc by jtag.
362input IotsbDesc_hw_acc_pio_slow_rd; // This signal enables reading of register
363 // IotsbDesc by pio_slow.
364input IotsbDesc_hw_acc_pio_slow_wr; // This signal enables writing of register
365 // IotsbDesc by pio_slow.
366input IotsbDesc_hw_acc_pio_med_rd; // This signal enables reading of register
367 // IotsbDesc by pio_med.
368input IotsbDesc_hw_acc_pio_med_wr; // This signal enables writing of register
369 // IotsbDesc by pio_med.
370input IotsbDesc_hw_acc_pio_fast_rd; // This signal enables reading of register
371 // IotsbDesc by pio_fast.
372input IotsbDesc_hw_acc_pio_fast_wr; // This signal enables writing of register
373 // IotsbDesc by pio_fast.
374output IotsbDesc_ext_select; // When set, register IotsbDesc is selected. This
375 // signal is a pulse.
376input [`FIRE_CSRBUS_DATA_WIDTH-1:0] IotsbDesc_ext_read_data; // Read data from
377 // the external
378 // bypass
379 // register
380input IotsbDesc_ext_done; // This signal acknowledges read and write
381 // operations for register IotsbDesc. For read
382 // operations, it indicates that the
383 // IotsbDesc_ext_read_data signals are valid. For
384 // write operations, it indicates that the write
385 // operation is complete, and that <dcm>_ext_wr_data
386 // may be removed on the next cycle.
387
388//====================================================
389// Type declarations
390//====================================================
391wire clk; // Clock signal
392wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
393wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
394wire csrbus_wr; // Read/Write signal
395wire csrbus_valid; // Valid address
396wire csrbus_mapped; // Address is mapped
397wire csrbus_done; // Operation is done
398wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
399wire rst_l; // Reset signal
400wire por_l; // Reset signal
401wire [1:0] csrbus_src_bus; // Source bus
402wire csrbus_acc_vio; // Violation signal
403wire instance_id; // Instance ID
404wire [8:0] ext_addr; // External address bus for dcm csr
405wire ext_wr; // When one, csr operation is a write. When zero, operation is a
406 // read.
407wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] ext_wr_data; // Provides SW write data for
408 // all external registers in
409 // default_grp
410wire [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write; // data bus
411 // for hw
412 // loading of
413 // ctl_spares.
414wire ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
415wire ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
416wire ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
417wire ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
418wire [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
419 // loading of
420 // ctl_tcm.
421wire [`FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC] ctl_sparec_hw_read; // This signal
422 // provides the
423 // current
424 // value of
425 // ctl_sparec.
426wire ctl_pd_hw_read; // This signal provides the current value of ctl_pd.
427wire ctl_se_hw_read; // This signal provides the current value of ctl_se.
428wire [`FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC] ctl_cm_hw_read; // This signal provides
429 // the current value of
430 // ctl_cm.
431wire ctl_busid_sel_hw_read; // This signal provides the current value of
432 // ctl_busid_sel.
433wire ctl_sun4v_en_hw_read; // This signal provides the current value of
434 // ctl_sun4v_en.
435wire ctl_be_hw_read; // This signal provides the current value of ctl_be.
436wire ctl_te_hw_read; // This signal provides the current value of ctl_te.
437wire [`FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC] tsb_tb_hw_read; // This signal provides
438 // the current value of
439 // tsb_tb.
440wire tsb_ps_hw_read; // This signal provides the current value of tsb_ps.
441wire [`FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC] tsb_ts_hw_read; // This signal provides
442 // the current value of
443 // tsb_ts.
444wire inv_ext_select; // When set, register inv is selected. This signal is a
445 // pulse.
446wire [`FIRE_DLC_MMU_CSR_LOG_EN_INT_SLC] log_en_hw_read; // This signal provides
447 // the current value of
448 // log_en.
449wire [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_hw_read; // This signal
450 // provides the
451 // current value of
452 // int_en.
453wire [20:0] en_err_err_s_ext_read_data; // Ext read data (decode)
454wire [20:0] en_err_err_p_ext_read_data; // Ext read data (decode)
455wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_set; // Hardware set
456 // signal for
457 // err. When set
458 // err will be
459 // set to one.
460wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_read; // This signal
461 // provides the
462 // current value
463 // of err.
464wire flta_va_hw_ld; // Hardware load enable for flta_va. When set, <hw write
465 // signal> will be loaded into flta.
466wire [`FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC] flta_va_hw_write; // data bus for hw
467 // loading of
468 // flta_va.
469wire flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw
470 // write signal> will be loaded into flts.
471wire [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; // data bus
472 // for hw
473 // loading of
474 // flts_entry.
475wire flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw
476 // write signal> will be loaded into flts.
477wire [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus for
478 // hw loading of
479 // flts_type.
480wire flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write
481 // signal> will be loaded into flts.
482wire [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw
483 // loading of
484 // flts_id.
485wire [`FIRE_DLC_MMU_CSR_PRFC_SEL1_INT_SLC] prfc_sel1_hw_read; // This signal
486 // provides the
487 // current value
488 // of prfc_sel1.
489wire [`FIRE_DLC_MMU_CSR_PRFC_SEL0_INT_SLC] prfc_sel0_hw_read; // This signal
490 // provides the
491 // current value
492 // of prfc_sel0.
493wire [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_write; // data bus for hw
494 // loading of
495 // prf0_cnt.
496wire [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_read; // This signal
497 // provides the
498 // current value of
499 // prf0_cnt.
500wire [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_write; // data bus for hw
501 // loading of
502 // prf1_cnt.
503wire [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_read; // This signal
504 // provides the
505 // current value of
506 // prf1_cnt.
507wire vtb_hw_acc_jtag_rd; // This signal enables reading of register vtb by
508 // jtag.
509wire vtb_hw_acc_jtag_wr; // This signal enables writing of register vtb by
510 // jtag.
511wire vtb_hw_acc_pio_slow_rd; // This signal enables reading of register vtb by
512 // pio_slow.
513wire vtb_hw_acc_pio_slow_wr; // This signal enables writing of register vtb by
514 // pio_slow.
515wire vtb_hw_acc_pio_med_rd; // This signal enables reading of register vtb by
516 // pio_med.
517wire vtb_hw_acc_pio_med_wr; // This signal enables writing of register vtb by
518 // pio_med.
519wire vtb_hw_acc_pio_fast_rd; // This signal enables reading of register vtb by
520 // pio_fast.
521wire vtb_hw_acc_pio_fast_wr; // This signal enables writing of register vtb by
522 // pio_fast.
523wire vtb_ext_select; // When set, register vtb is selected. This signal is a
524 // pulse.
525wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] vtb_ext_read_data; // Read data from the
526 // external bypass
527 // register
528wire ptb_hw_acc_jtag_rd; // This signal enables reading of register ptb by
529 // jtag.
530wire ptb_hw_acc_jtag_wr; // This signal enables writing of register ptb by
531 // jtag.
532wire ptb_hw_acc_pio_slow_rd; // This signal enables reading of register ptb by
533 // pio_slow.
534wire ptb_hw_acc_pio_slow_wr; // This signal enables writing of register ptb by
535 // pio_slow.
536wire ptb_hw_acc_pio_med_rd; // This signal enables reading of register ptb by
537 // pio_med.
538wire ptb_hw_acc_pio_med_wr; // This signal enables writing of register ptb by
539 // pio_med.
540wire ptb_hw_acc_pio_fast_rd; // This signal enables reading of register ptb by
541 // pio_fast.
542wire ptb_hw_acc_pio_fast_wr; // This signal enables writing of register ptb by
543 // pio_fast.
544wire ptb_ext_select; // When set, register ptb is selected. This signal is a
545 // pulse.
546wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] ptb_ext_read_data; // Read data from the
547 // external bypass
548 // register
549wire tdb_hw_acc_jtag_rd; // This signal enables reading of register tdb by
550 // jtag.
551wire tdb_hw_acc_jtag_wr; // This signal enables writing of register tdb by
552 // jtag.
553wire tdb_hw_acc_pio_slow_rd; // This signal enables reading of register tdb by
554 // pio_slow.
555wire tdb_hw_acc_pio_slow_wr; // This signal enables writing of register tdb by
556 // pio_slow.
557wire tdb_hw_acc_pio_med_rd; // This signal enables reading of register tdb by
558 // pio_med.
559wire tdb_hw_acc_pio_med_wr; // This signal enables writing of register tdb by
560 // pio_med.
561wire tdb_hw_acc_pio_fast_rd; // This signal enables reading of register tdb by
562 // pio_fast.
563wire tdb_hw_acc_pio_fast_wr; // This signal enables writing of register tdb by
564 // pio_fast.
565wire tdb_ext_select; // When set, register tdb is selected. This signal is a
566 // pulse.
567wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] tdb_ext_read_data; // Read data from the
568 // external bypass
569 // register
570wire dev2iotsb_hw_acc_jtag_rd; // This signal enables reading of register
571 // dev2iotsb by jtag.
572wire dev2iotsb_hw_acc_jtag_wr; // This signal enables writing of register
573 // dev2iotsb by jtag.
574wire dev2iotsb_hw_acc_pio_slow_rd; // This signal enables reading of register
575 // dev2iotsb by pio_slow.
576wire dev2iotsb_hw_acc_pio_slow_wr; // This signal enables writing of register
577 // dev2iotsb by pio_slow.
578wire dev2iotsb_hw_acc_pio_med_rd; // This signal enables reading of register
579 // dev2iotsb by pio_med.
580wire dev2iotsb_hw_acc_pio_med_wr; // This signal enables writing of register
581 // dev2iotsb by pio_med.
582wire dev2iotsb_hw_acc_pio_fast_rd; // This signal enables reading of register
583 // dev2iotsb by pio_fast.
584wire dev2iotsb_hw_acc_pio_fast_wr; // This signal enables writing of register
585 // dev2iotsb by pio_fast.
586wire dev2iotsb_ext_select; // When set, register dev2iotsb is selected. This
587 // signal is a pulse.
588wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] dev2iotsb_ext_read_data; // Read data from
589 // the external
590 // bypass register
591wire dev2iotsb_ext_done; // This signal acknowledges read and write operations
592 // for register dev2iotsb. For read operations, it
593 // indicates that the dev2iotsb_ext_read_data signals
594 // are valid. For write operations, it indicates that
595 // the write operation is complete, and that
596 // <dcm>_ext_wr_data may be removed on the next cycle.
597wire IotsbDesc_hw_acc_jtag_rd; // This signal enables reading of register
598 // IotsbDesc by jtag.
599wire IotsbDesc_hw_acc_jtag_wr; // This signal enables writing of register
600 // IotsbDesc by jtag.
601wire IotsbDesc_hw_acc_pio_slow_rd; // This signal enables reading of register
602 // IotsbDesc by pio_slow.
603wire IotsbDesc_hw_acc_pio_slow_wr; // This signal enables writing of register
604 // IotsbDesc by pio_slow.
605wire IotsbDesc_hw_acc_pio_med_rd; // This signal enables reading of register
606 // IotsbDesc by pio_med.
607wire IotsbDesc_hw_acc_pio_med_wr; // This signal enables writing of register
608 // IotsbDesc by pio_med.
609wire IotsbDesc_hw_acc_pio_fast_rd; // This signal enables reading of register
610 // IotsbDesc by pio_fast.
611wire IotsbDesc_hw_acc_pio_fast_wr; // This signal enables writing of register
612 // IotsbDesc by pio_fast.
613wire IotsbDesc_ext_select; // When set, register IotsbDesc is selected. This
614 // signal is a pulse.
615wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] IotsbDesc_ext_read_data; // Read data from
616 // the external
617 // bypass register
618wire IotsbDesc_ext_done; // This signal acknowledges read and write operations
619 // for register IotsbDesc. For read operations, it
620 // indicates that the IotsbDesc_ext_read_data signals
621 // are valid. For write operations, it indicates that
622 // the write operation is complete, and that
623 // <dcm>_ext_wr_data may be removed on the next cycle.
624
625//====================================================
626// Logic
627//====================================================
628wire daemon_transaction_in_progress;
629wire daemon_csrbus_mapped;
630wire daemon_csrbus_valid;
631// vlint flag_dangling_net_within_module off
632// vlint flag_net_has_no_load off
633wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp;
634wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data;
635// vlint flag_dangling_net_within_module on
636// vlint flag_net_has_no_load on
637wire daemon_csrbus_done;
638wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr;
639wire daemon_csrbus_wr_tmp;
640wire daemon_csrbus_wr;
641
642//summit modcovoff -bepgnv
643pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon (
644 .daemon_csrbus_valid (daemon_csrbus_valid),
645 .daemon_csrbus_mapped (daemon_csrbus_mapped),
646 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
647 .daemon_csrbus_done (daemon_csrbus_done),
648 .daemon_csrbus_addr (daemon_csrbus_addr),
649 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
650 .daemon_transaction_in_progress (daemon_transaction_in_progress),
651// synopsys translate_off
652 .clk(clk),
653 .csrbus_read_data (csrbus_read_data),
654 .rst_l (rst_l),
655// synopsys translate_on
656 .csrbus_valid (csrbus_valid),
657 .csrbus_mapped (csrbus_mapped),
658 .csrbus_wr_data (csrbus_wr_data),
659 .csrbus_done (csrbus_done),
660 .csrbus_addr (csrbus_addr),
661 .csrbus_wr (csrbus_wr)
662 );
663//summit modcovon -bepgnv
664
665//====================================================================
666// Address decode
667//====================================================================
668wire ctl_select_pulse;
669wire tsb_select_pulse;
670wire fsh_select_pulse;
671wire inv_select;
672wire log_select_pulse;
673wire int_en_select_pulse;
674wire en_err_select;
675wire err_select_pulse;
676wire flta_select_pulse;
677wire flts_select_pulse;
678wire prfc_select_pulse;
679wire prf0_select_pulse;
680wire prf1_select_pulse;
681wire vtb_select;
682wire ptb_select;
683wire tdb_select;
684wire dev2iotsb_select;
685wire IotsbDesc_select;
686wire err_rw1c_alias;
687wire err_rw1s_alias;
688wire stage_mux_only_ext_done_0_out;
689
690dmu_mmu_csr_addr_decode dmu_mmu_csr_addr_decode
691 (
692 .clk (clk),
693 .rst_l (rst_l),
694 .daemon_csrbus_valid (daemon_csrbus_valid),
695 .daemon_csrbus_addr (daemon_csrbus_addr),
696 .csrbus_src_bus (csrbus_src_bus),
697 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
698 .daemon_csrbus_wr_out (daemon_csrbus_wr),
699 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
700 .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data),
701 .daemon_csrbus_mapped (daemon_csrbus_mapped),
702 .csrbus_acc_vio (csrbus_acc_vio),
703 .daemon_transaction_in_progress (daemon_transaction_in_progress),
704 .instance_id (instance_id),
705 .daemon_csrbus_done (daemon_csrbus_done),
706 .stage_mux_only_ext_done_0_out (stage_mux_only_ext_done_0_out),
707 .ctl_select_pulse (ctl_select_pulse),
708 .tsb_select_pulse (tsb_select_pulse),
709 .fsh_select_pulse (fsh_select_pulse),
710 .inv_select (inv_select),
711 .log_select_pulse (log_select_pulse),
712 .int_en_select_pulse (int_en_select_pulse),
713 .en_err_select (en_err_select),
714 .err_select_pulse (err_select_pulse),
715 .err_rw1c_alias (err_rw1c_alias),
716 .err_rw1s_alias (err_rw1s_alias),
717 .flta_select_pulse (flta_select_pulse),
718 .flts_select_pulse (flts_select_pulse),
719 .prfc_select_pulse (prfc_select_pulse),
720 .prf0_select_pulse (prf0_select_pulse),
721 .prf1_select_pulse (prf1_select_pulse),
722 .vtb_select (vtb_select),
723 .vtb_hw_acc_jtag_rd (vtb_hw_acc_jtag_rd),
724 .vtb_hw_acc_jtag_wr (vtb_hw_acc_jtag_wr),
725 .vtb_hw_acc_pio_slow_rd (vtb_hw_acc_pio_slow_rd),
726 .vtb_hw_acc_pio_slow_wr (vtb_hw_acc_pio_slow_wr),
727 .vtb_hw_acc_pio_med_rd (vtb_hw_acc_pio_med_rd),
728 .vtb_hw_acc_pio_med_wr (vtb_hw_acc_pio_med_wr),
729 .vtb_hw_acc_pio_fast_rd (vtb_hw_acc_pio_fast_rd),
730 .vtb_hw_acc_pio_fast_wr (vtb_hw_acc_pio_fast_wr),
731 .ptb_select (ptb_select),
732 .ptb_hw_acc_jtag_rd (ptb_hw_acc_jtag_rd),
733 .ptb_hw_acc_jtag_wr (ptb_hw_acc_jtag_wr),
734 .ptb_hw_acc_pio_slow_rd (ptb_hw_acc_pio_slow_rd),
735 .ptb_hw_acc_pio_slow_wr (ptb_hw_acc_pio_slow_wr),
736 .ptb_hw_acc_pio_med_rd (ptb_hw_acc_pio_med_rd),
737 .ptb_hw_acc_pio_med_wr (ptb_hw_acc_pio_med_wr),
738 .ptb_hw_acc_pio_fast_rd (ptb_hw_acc_pio_fast_rd),
739 .ptb_hw_acc_pio_fast_wr (ptb_hw_acc_pio_fast_wr),
740 .tdb_select (tdb_select),
741 .tdb_hw_acc_jtag_rd (tdb_hw_acc_jtag_rd),
742 .tdb_hw_acc_jtag_wr (tdb_hw_acc_jtag_wr),
743 .tdb_hw_acc_pio_slow_rd (tdb_hw_acc_pio_slow_rd),
744 .tdb_hw_acc_pio_slow_wr (tdb_hw_acc_pio_slow_wr),
745 .tdb_hw_acc_pio_med_rd (tdb_hw_acc_pio_med_rd),
746 .tdb_hw_acc_pio_med_wr (tdb_hw_acc_pio_med_wr),
747 .tdb_hw_acc_pio_fast_rd (tdb_hw_acc_pio_fast_rd),
748 .tdb_hw_acc_pio_fast_wr (tdb_hw_acc_pio_fast_wr),
749 .dev2iotsb_select (dev2iotsb_select),
750 .dev2iotsb_hw_acc_jtag_rd (dev2iotsb_hw_acc_jtag_rd),
751 .dev2iotsb_hw_acc_jtag_wr (dev2iotsb_hw_acc_jtag_wr),
752 .dev2iotsb_hw_acc_pio_slow_rd (dev2iotsb_hw_acc_pio_slow_rd),
753 .dev2iotsb_hw_acc_pio_slow_wr (dev2iotsb_hw_acc_pio_slow_wr),
754 .dev2iotsb_hw_acc_pio_med_rd (dev2iotsb_hw_acc_pio_med_rd),
755 .dev2iotsb_hw_acc_pio_med_wr (dev2iotsb_hw_acc_pio_med_wr),
756 .dev2iotsb_hw_acc_pio_fast_rd (dev2iotsb_hw_acc_pio_fast_rd),
757 .dev2iotsb_hw_acc_pio_fast_wr (dev2iotsb_hw_acc_pio_fast_wr),
758 .IotsbDesc_select (IotsbDesc_select),
759 .IotsbDesc_hw_acc_jtag_rd (IotsbDesc_hw_acc_jtag_rd),
760 .IotsbDesc_hw_acc_jtag_wr (IotsbDesc_hw_acc_jtag_wr),
761 .IotsbDesc_hw_acc_pio_slow_rd (IotsbDesc_hw_acc_pio_slow_rd),
762 .IotsbDesc_hw_acc_pio_slow_wr (IotsbDesc_hw_acc_pio_slow_wr),
763 .IotsbDesc_hw_acc_pio_med_rd (IotsbDesc_hw_acc_pio_med_rd),
764 .IotsbDesc_hw_acc_pio_med_wr (IotsbDesc_hw_acc_pio_med_wr),
765 .IotsbDesc_hw_acc_pio_fast_rd (IotsbDesc_hw_acc_pio_fast_rd),
766 .IotsbDesc_hw_acc_pio_fast_wr (IotsbDesc_hw_acc_pio_fast_wr)
767 );
768
769//====================================================================
770// OUTPUT: csrbus_read_data (pipelining)
771//====================================================================
772//----- connecting wires
773wire stage_2_default_grp_rst_l;
774wire stage_2_default_grp_por_l;
775wire stage_mux_only_rst_l;
776wire stage_mux_only_por_l;
777wire stage_2_default_grp_err_rw1c_alias;
778wire stage_2_default_grp_err_rw1s_alias;
779wire [8:0] stage_2_default_grp_ext_addr;
780wire stage_2_default_grp_daemon_csrbus_wr;
781wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_2_default_grp_daemon_csrbus_wr_data;
782wire stage_mux_only_err_rw1c_alias;
783wire stage_mux_only_err_rw1s_alias;
784wire [8:0] stage_mux_only_ext_addr;
785wire stage_mux_only_daemon_csrbus_wr;
786wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data;
787
788//----- Stage: 1 / Grp: default_grp (17 inputs / 2 outputs)
789wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out;
790wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_1_out;
791wire default_grp_ext_done_0_out;
792wire default_grp_ctl_select_pulse;
793wire default_grp_tsb_select_pulse;
794wire default_grp_fsh_select_pulse;
795wire default_grp_inv_select;
796wire default_grp_log_select_pulse;
797wire default_grp_int_en_select_pulse;
798wire default_grp_en_err_select;
799wire default_grp_err_select_pulse;
800wire default_grp_flta_select_pulse;
801wire default_grp_flts_select_pulse;
802wire default_grp_prfc_select_pulse;
803wire default_grp_prf0_select_pulse;
804wire default_grp_prf1_select_pulse;
805wire default_grp_vtb_select;
806wire default_grp_ptb_select;
807wire default_grp_tdb_select;
808wire default_grp_dev2iotsb_select;
809wire default_grp_IotsbDesc_select;
810
811dmu_mmu_csr_default_grp dmu_mmu_csr_default_grp
812 (
813 .clk (clk),
814 .ctl_spares_hw_write (ctl_spares_hw_write),
815 .ctl_paq_hw_write (ctl_paq_hw_write),
816 .ctl_vaq_hw_write (ctl_vaq_hw_write),
817 .ctl_tpl_hw_write (ctl_tpl_hw_write),
818 .ctl_tip_hw_write (ctl_tip_hw_write),
819 .ctl_tcm_hw_write (ctl_tcm_hw_write),
820 .ctl_sparec_hw_read (ctl_sparec_hw_read),
821 .ctl_pd_hw_read (ctl_pd_hw_read),
822 .ctl_se_hw_read (ctl_se_hw_read),
823 .ctl_cm_hw_read (ctl_cm_hw_read),
824 .ctl_busid_sel_hw_read (ctl_busid_sel_hw_read),
825 .ctl_sun4v_en_hw_read (ctl_sun4v_en_hw_read),
826 .ctl_be_hw_read (ctl_be_hw_read),
827 .ctl_te_hw_read (ctl_te_hw_read),
828 .ctl_select_pulse (default_grp_ctl_select_pulse),
829 .tsb_tb_hw_read (tsb_tb_hw_read),
830 .tsb_ps_hw_read (tsb_ps_hw_read),
831 .tsb_ts_hw_read (tsb_ts_hw_read),
832 .tsb_select_pulse (default_grp_tsb_select_pulse),
833 .fsh_select_pulse (default_grp_fsh_select_pulse),
834 .inv_ext_select (inv_ext_select),
835 .inv_select (default_grp_inv_select),
836 .log_en_hw_read (log_en_hw_read),
837 .log_select_pulse (default_grp_log_select_pulse),
838 .int_en_hw_read (int_en_hw_read),
839 .int_en_select_pulse (default_grp_int_en_select_pulse),
840 .en_err_select (default_grp_en_err_select),
841 .en_err_ext_read_data
842 (
843 {
844 11'b0,
845 en_err_err_s_ext_read_data,
846 11'b0,
847 en_err_err_p_ext_read_data
848 }),
849 .err_hw_set (err_hw_set),
850 .err_hw_read (err_hw_read),
851 .err_select_pulse (default_grp_err_select_pulse),
852 .flta_va_hw_ld (flta_va_hw_ld),
853 .flta_va_hw_write (flta_va_hw_write),
854 .flta_select_pulse (default_grp_flta_select_pulse),
855 .flts_entry_hw_ld (flts_entry_hw_ld),
856 .flts_entry_hw_write (flts_entry_hw_write),
857 .flts_type_hw_ld (flts_type_hw_ld),
858 .flts_type_hw_write (flts_type_hw_write),
859 .flts_id_hw_ld (flts_id_hw_ld),
860 .flts_id_hw_write (flts_id_hw_write),
861 .flts_select_pulse (default_grp_flts_select_pulse),
862 .prfc_sel1_hw_read (prfc_sel1_hw_read),
863 .prfc_sel0_hw_read (prfc_sel0_hw_read),
864 .prfc_select_pulse (default_grp_prfc_select_pulse),
865 .prf0_cnt_hw_write (prf0_cnt_hw_write),
866 .prf0_cnt_hw_read (prf0_cnt_hw_read),
867 .prf0_select_pulse (default_grp_prf0_select_pulse),
868 .prf1_cnt_hw_write (prf1_cnt_hw_write),
869 .prf1_cnt_hw_read (prf1_cnt_hw_read),
870 .prf1_select_pulse (default_grp_prf1_select_pulse),
871 .vtb_ext_select (vtb_ext_select),
872 .vtb_select (default_grp_vtb_select),
873 .vtb_ext_read_data (vtb_ext_read_data),
874 .ptb_ext_select (ptb_ext_select),
875 .ptb_select (default_grp_ptb_select),
876 .ptb_ext_read_data (ptb_ext_read_data),
877 .tdb_ext_select (tdb_ext_select),
878 .tdb_select (default_grp_tdb_select),
879 .tdb_ext_read_data (tdb_ext_read_data),
880 .dev2iotsb_ext_select (dev2iotsb_ext_select),
881 .dev2iotsb_select (default_grp_dev2iotsb_select),
882 .dev2iotsb_ext_read_data (dev2iotsb_ext_read_data),
883 .dev2iotsb_ext_done (dev2iotsb_ext_done),
884 .IotsbDesc_ext_select (IotsbDesc_ext_select),
885 .IotsbDesc_select (default_grp_IotsbDesc_select),
886 .IotsbDesc_ext_read_data (IotsbDesc_ext_read_data),
887 .IotsbDesc_ext_done (IotsbDesc_ext_done),
888 .err_rw1c_alias (stage_2_default_grp_err_rw1c_alias),
889 .err_rw1s_alias (stage_2_default_grp_err_rw1s_alias),
890 .rst_l (stage_2_default_grp_rst_l),
891 .por_l (stage_2_default_grp_por_l),
892 .daemon_csrbus_wr_in (stage_2_default_grp_daemon_csrbus_wr),
893 .daemon_csrbus_wr_out (ext_wr),
894 .daemon_csrbus_wr_data_in (stage_2_default_grp_daemon_csrbus_wr_data),
895 .daemon_csrbus_wr_data_out (ext_wr_data),
896 .ext_addr_in (stage_2_default_grp_ext_addr[8:0]),
897 .ext_addr_out (ext_addr),
898 .read_data_0_out (default_grp_read_data_0_out),
899 .read_data_1_out (default_grp_read_data_1_out),
900 .ext_done_0_out (default_grp_ext_done_0_out)
901 );
902
903//----- Stage: 2 / Grp: stage_2_default_grp (2 inputs / 1 outputs)
904wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_2_default_grp_read_data_0_out;
905wire stage_2_default_grp_ext_done_0_out;
906wire stage_2_default_grp_ctl_select_pulse;
907wire stage_2_default_grp_tsb_select_pulse;
908wire stage_2_default_grp_fsh_select_pulse;
909wire stage_2_default_grp_inv_select;
910wire stage_2_default_grp_log_select_pulse;
911wire stage_2_default_grp_int_en_select_pulse;
912wire stage_2_default_grp_en_err_select;
913wire stage_2_default_grp_err_select_pulse;
914wire stage_2_default_grp_flta_select_pulse;
915wire stage_2_default_grp_flts_select_pulse;
916wire stage_2_default_grp_prfc_select_pulse;
917wire stage_2_default_grp_prf0_select_pulse;
918wire stage_2_default_grp_prf1_select_pulse;
919wire stage_2_default_grp_vtb_select;
920wire stage_2_default_grp_ptb_select;
921wire stage_2_default_grp_tdb_select;
922wire stage_2_default_grp_dev2iotsb_select;
923wire stage_2_default_grp_IotsbDesc_select;
924
925dmu_mmu_csr_stage_2_default_grp dmu_mmu_csr_stage_2_default_grp
926 (
927 .clk (clk),
928 .read_data_0 (default_grp_read_data_0_out),
929 .read_data_1 (default_grp_read_data_1_out),
930 .ext_done_0 (default_grp_ext_done_0_out),
931 .ctl_select_pulse (stage_2_default_grp_ctl_select_pulse),
932 .ctl_select_pulse_out (default_grp_ctl_select_pulse),
933 .tsb_select_pulse (stage_2_default_grp_tsb_select_pulse),
934 .tsb_select_pulse_out (default_grp_tsb_select_pulse),
935 .fsh_select_pulse (stage_2_default_grp_fsh_select_pulse),
936 .fsh_select_pulse_out (default_grp_fsh_select_pulse),
937 .inv_select (stage_2_default_grp_inv_select),
938 .inv_select_out (default_grp_inv_select),
939 .log_select_pulse (stage_2_default_grp_log_select_pulse),
940 .log_select_pulse_out (default_grp_log_select_pulse),
941 .int_en_select_pulse (stage_2_default_grp_int_en_select_pulse),
942 .int_en_select_pulse_out (default_grp_int_en_select_pulse),
943 .en_err_select (stage_2_default_grp_en_err_select),
944 .en_err_select_out (default_grp_en_err_select),
945 .err_select_pulse (stage_2_default_grp_err_select_pulse),
946 .err_select_pulse_out (default_grp_err_select_pulse),
947 .flta_select_pulse (stage_2_default_grp_flta_select_pulse),
948 .flta_select_pulse_out (default_grp_flta_select_pulse),
949 .flts_select_pulse (stage_2_default_grp_flts_select_pulse),
950 .flts_select_pulse_out (default_grp_flts_select_pulse),
951 .prfc_select_pulse (stage_2_default_grp_prfc_select_pulse),
952 .prfc_select_pulse_out (default_grp_prfc_select_pulse),
953 .prf0_select_pulse (stage_2_default_grp_prf0_select_pulse),
954 .prf0_select_pulse_out (default_grp_prf0_select_pulse),
955 .prf1_select_pulse (stage_2_default_grp_prf1_select_pulse),
956 .prf1_select_pulse_out (default_grp_prf1_select_pulse),
957 .vtb_select (stage_2_default_grp_vtb_select),
958 .vtb_select_out (default_grp_vtb_select),
959 .ptb_select (stage_2_default_grp_ptb_select),
960 .ptb_select_out (default_grp_ptb_select),
961 .tdb_select (stage_2_default_grp_tdb_select),
962 .tdb_select_out (default_grp_tdb_select),
963 .dev2iotsb_select (stage_2_default_grp_dev2iotsb_select),
964 .dev2iotsb_select_out (default_grp_dev2iotsb_select),
965 .IotsbDesc_select (stage_2_default_grp_IotsbDesc_select),
966 .IotsbDesc_select_out (default_grp_IotsbDesc_select),
967 .err_rw1c_alias (stage_mux_only_err_rw1c_alias),
968 .err_rw1c_alias_out (stage_2_default_grp_err_rw1c_alias),
969 .err_rw1s_alias (stage_mux_only_err_rw1s_alias),
970 .err_rw1s_alias_out (stage_2_default_grp_err_rw1s_alias),
971 .rst_l (stage_mux_only_rst_l),
972 .rst_l_out (stage_2_default_grp_rst_l),
973 .por_l (stage_mux_only_por_l),
974 .por_l_out (stage_2_default_grp_por_l),
975 .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr),
976 .daemon_csrbus_wr_out (stage_2_default_grp_daemon_csrbus_wr),
977 .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data),
978 .daemon_csrbus_wr_data_out (stage_2_default_grp_daemon_csrbus_wr_data),
979 .ext_addr_in (stage_mux_only_ext_addr[8:0]),
980 .ext_addr_out (stage_2_default_grp_ext_addr),
981 .read_data_0_out (stage_2_default_grp_read_data_0_out),
982 .ext_done_0_out (stage_2_default_grp_ext_done_0_out)
983 );
984
985//----- Stage: 3 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only)
986wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out;
987
988dmu_mmu_csr_stage_mux_only dmu_mmu_csr_stage_mux_only
989 (
990 .clk (clk),
991 .read_data_0 (stage_2_default_grp_read_data_0_out),
992 .ext_done_0 (stage_2_default_grp_ext_done_0_out),
993 .ctl_select_pulse (ctl_select_pulse),
994 .ctl_select_pulse_out (stage_2_default_grp_ctl_select_pulse),
995 .tsb_select_pulse (tsb_select_pulse),
996 .tsb_select_pulse_out (stage_2_default_grp_tsb_select_pulse),
997 .fsh_select_pulse (fsh_select_pulse),
998 .fsh_select_pulse_out (stage_2_default_grp_fsh_select_pulse),
999 .inv_select (inv_select),
1000 .inv_select_out (stage_2_default_grp_inv_select),
1001 .log_select_pulse (log_select_pulse),
1002 .log_select_pulse_out (stage_2_default_grp_log_select_pulse),
1003 .int_en_select_pulse (int_en_select_pulse),
1004 .int_en_select_pulse_out (stage_2_default_grp_int_en_select_pulse),
1005 .en_err_select (en_err_select),
1006 .en_err_select_out (stage_2_default_grp_en_err_select),
1007 .err_select_pulse (err_select_pulse),
1008 .err_select_pulse_out (stage_2_default_grp_err_select_pulse),
1009 .flta_select_pulse (flta_select_pulse),
1010 .flta_select_pulse_out (stage_2_default_grp_flta_select_pulse),
1011 .flts_select_pulse (flts_select_pulse),
1012 .flts_select_pulse_out (stage_2_default_grp_flts_select_pulse),
1013 .prfc_select_pulse (prfc_select_pulse),
1014 .prfc_select_pulse_out (stage_2_default_grp_prfc_select_pulse),
1015 .prf0_select_pulse (prf0_select_pulse),
1016 .prf0_select_pulse_out (stage_2_default_grp_prf0_select_pulse),
1017 .prf1_select_pulse (prf1_select_pulse),
1018 .prf1_select_pulse_out (stage_2_default_grp_prf1_select_pulse),
1019 .vtb_select (vtb_select),
1020 .vtb_select_out (stage_2_default_grp_vtb_select),
1021 .ptb_select (ptb_select),
1022 .ptb_select_out (stage_2_default_grp_ptb_select),
1023 .tdb_select (tdb_select),
1024 .tdb_select_out (stage_2_default_grp_tdb_select),
1025 .dev2iotsb_select (dev2iotsb_select),
1026 .dev2iotsb_select_out (stage_2_default_grp_dev2iotsb_select),
1027 .IotsbDesc_select (IotsbDesc_select),
1028 .IotsbDesc_select_out (stage_2_default_grp_IotsbDesc_select),
1029 .err_rw1c_alias (err_rw1c_alias),
1030 .err_rw1c_alias_out (stage_mux_only_err_rw1c_alias),
1031 .err_rw1s_alias (err_rw1s_alias),
1032 .err_rw1s_alias_out (stage_mux_only_err_rw1s_alias),
1033 .daemon_csrbus_wr_in (daemon_csrbus_wr),
1034 .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr),
1035 .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data),
1036 .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data),
1037 .ext_addr_in (daemon_csrbus_addr[8:0]),
1038 .ext_addr_out (stage_mux_only_ext_addr),
1039 .read_data_0_out (stage_mux_only_read_data_0_out),
1040 .ext_done_0_out (stage_mux_only_ext_done_0_out),
1041 .rst_l (rst_l),
1042 .rst_l_out (stage_mux_only_rst_l),
1043 .por_l (por_l),
1044 .por_l_out (stage_mux_only_por_l)
1045 );
1046
1047//----- OUTPUT: csrbus_read_data
1048assign csrbus_read_data = stage_mux_only_read_data_0_out;
1049
1050endmodule // dmu_mmu_csr_csr
Full OpenSPARC design & verification tarball including full HDL.