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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_ctl | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | ctl_w_ld, | |
40 | csrbus_wr_data, | |
41 | ctl_csrbus_read_data, | |
42 | ctl_spares_hw_write, | |
43 | ctl_paq_hw_write, | |
44 | ctl_vaq_hw_write, | |
45 | ctl_tpl_hw_write, | |
46 | ctl_tip_hw_write, | |
47 | ctl_tcm_hw_write, | |
48 | ctl_sparec_hw_read, | |
49 | ctl_pd_hw_read, | |
50 | ctl_se_hw_read, | |
51 | ctl_cm_hw_read, | |
52 | ctl_busid_sel_hw_read, | |
53 | ctl_sun4v_en_hw_read, | |
54 | ctl_be_hw_read, | |
55 | ctl_te_hw_read | |
56 | ); | |
57 | ||
58 | //==================================================================== | |
59 | // Polarity declarations | |
60 | //==================================================================== | |
61 | input clk; // Clock | |
62 | input rst_l; // Reset signal | |
63 | input ctl_w_ld; // SW load bus | |
64 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
65 | output [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // SW read data | |
66 | input [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write; | |
67 | // data bus for hw loading of ctl_spares. | |
68 | input ctl_paq_hw_write; // data bus for hw loading of ctl_paq. | |
69 | input ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq. | |
70 | input ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl. | |
71 | input ctl_tip_hw_write; // data bus for hw loading of ctl_tip. | |
72 | input [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw | |
73 | // loading of | |
74 | // ctl_tcm. | |
75 | output [`FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC] ctl_sparec_hw_read; | |
76 | // This signal provides the current value of ctl_sparec. | |
77 | output ctl_pd_hw_read; // This signal provides the current value of ctl_pd. | |
78 | output ctl_se_hw_read; // This signal provides the current value of ctl_se. | |
79 | output [`FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC] ctl_cm_hw_read; // This signal | |
80 | // provides the | |
81 | // current value of | |
82 | // ctl_cm. | |
83 | output ctl_busid_sel_hw_read; // This signal provides the current value of | |
84 | // ctl_busid_sel. | |
85 | output ctl_sun4v_en_hw_read; // This signal provides the current value of | |
86 | // ctl_sun4v_en. | |
87 | output ctl_be_hw_read; // This signal provides the current value of ctl_be. | |
88 | output ctl_te_hw_read; // This signal provides the current value of ctl_te. | |
89 | ||
90 | //==================================================================== | |
91 | // Type declarations | |
92 | //==================================================================== | |
93 | wire clk; // Clock | |
94 | wire rst_l; // Reset signal | |
95 | wire ctl_w_ld; // SW load bus | |
96 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
97 | wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // SW read data | |
98 | wire [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write; // data bus | |
99 | // for hw | |
100 | // loading of | |
101 | // ctl_spares. | |
102 | wire ctl_paq_hw_write; // data bus for hw loading of ctl_paq. | |
103 | wire ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq. | |
104 | wire ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl. | |
105 | wire ctl_tip_hw_write; // data bus for hw loading of ctl_tip. | |
106 | wire [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw | |
107 | // loading of | |
108 | // ctl_tcm. | |
109 | wire [`FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC] ctl_sparec_hw_read; // This signal | |
110 | // provides the | |
111 | // current | |
112 | // value of | |
113 | // ctl_sparec. | |
114 | wire ctl_pd_hw_read; // This signal provides the current value of ctl_pd. | |
115 | wire ctl_se_hw_read; // This signal provides the current value of ctl_se. | |
116 | wire [`FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC] ctl_cm_hw_read; // This signal provides | |
117 | // the current value of | |
118 | // ctl_cm. | |
119 | wire ctl_busid_sel_hw_read; // This signal provides the current value of | |
120 | // ctl_busid_sel. | |
121 | wire ctl_sun4v_en_hw_read; // This signal provides the current value of | |
122 | // ctl_sun4v_en. | |
123 | wire ctl_be_hw_read; // This signal provides the current value of ctl_be. | |
124 | wire ctl_te_hw_read; // This signal provides the current value of ctl_te. | |
125 | ||
126 | //==================================================================== | |
127 | // Logic | |
128 | //==================================================================== | |
129 | ||
130 | // synopsys translate_off | |
131 | // verilint 123 off | |
132 | // verilint 498 off | |
133 | reg omni_ld; | |
134 | reg [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] omni_data; | |
135 | ||
136 | // vlint flag_unsynthesizable_initial off | |
137 | initial | |
138 | begin | |
139 | omni_ld = 1'b0; | |
140 | omni_data = `FIRE_DLC_MMU_CSR_CTL_WIDTH'b0; | |
141 | end// vlint flag_unsynthesizable_initial on | |
142 | ||
143 | // verilint 123 on | |
144 | // verilint 498 on | |
145 | // synopsys translate_on | |
146 | ||
147 | //----- Hardware Data Out Mux Assignments | |
148 | assign ctl_sparec_hw_read= | |
149 | ctl_csrbus_read_data | |
150 | [`FIRE_DLC_MMU_CSR_CTL_SPAREC_SLC]; | |
151 | assign ctl_pd_hw_read= | |
152 | ctl_csrbus_read_data [12]; | |
153 | assign ctl_se_hw_read= | |
154 | ctl_csrbus_read_data [10]; | |
155 | assign ctl_cm_hw_read= | |
156 | ctl_csrbus_read_data | |
157 | [`FIRE_DLC_MMU_CSR_CTL_CM_SLC]; | |
158 | assign ctl_busid_sel_hw_read= | |
159 | ctl_csrbus_read_data [3]; | |
160 | assign ctl_sun4v_en_hw_read= | |
161 | ctl_csrbus_read_data [2]; | |
162 | assign ctl_be_hw_read= | |
163 | ctl_csrbus_read_data [1]; | |
164 | assign ctl_te_hw_read= | |
165 | ctl_csrbus_read_data [0]; | |
166 | ||
167 | //==================================================================== | |
168 | // Instantiation of entries | |
169 | //==================================================================== | |
170 | ||
171 | //----- Entry 0 | |
172 | dmu_mmu_csr_ctl_entry ctl_0 | |
173 | ( | |
174 | // synopsys translate_off | |
175 | .omni_ld (omni_ld), | |
176 | .omni_data (omni_data), | |
177 | // synopsys translate_on | |
178 | .clk (clk), | |
179 | .rst_l (rst_l), | |
180 | .w_ld (ctl_w_ld), | |
181 | .csrbus_wr_data (csrbus_wr_data), | |
182 | .ctl_csrbus_read_data (ctl_csrbus_read_data), | |
183 | .ctl_spares_hw_write (ctl_spares_hw_write), | |
184 | .ctl_paq_hw_write (ctl_paq_hw_write), | |
185 | .ctl_vaq_hw_write (ctl_vaq_hw_write), | |
186 | .ctl_tpl_hw_write (ctl_tpl_hw_write), | |
187 | .ctl_tip_hw_write (ctl_tip_hw_write), | |
188 | .ctl_tcm_hw_write (ctl_tcm_hw_write) | |
189 | ); | |
190 | ||
191 | endmodule // dmu_mmu_csr_ctl |