[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_ctl_entry.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_mmu_csr_ctl_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
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// ========== Copyright Header End ============================================
module dmu_mmu_csr_ctl_entry 
	(
	// synopsys translate_off
	  omni_ld,
	  omni_data,
	// synopsys translate_on
	clk,
	rst_l,
	w_ld,
	csrbus_wr_data,
	ctl_csrbus_read_data,
	ctl_spares_hw_write,
	ctl_paq_hw_write,
	ctl_vaq_hw_write,
	ctl_tpl_hw_write,
	ctl_tip_hw_write,
	ctl_tcm_hw_write
	);

//====================================================================
//     Polarity declarations
//====================================================================
// synopsys translate_off
  input  omni_ld;  // Omni load
// vlint flag_input_port_not_connected off
  input  [`FIRE_DLC_MMU_CSR_CTL_WIDTH - 1:0] omni_data;  // Omni write data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input  clk;  // Clock signal
input  rst_l;  // Reset signal
input  w_ld;  // SW load
// vlint flag_input_port_not_connected off
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data;  // SW read data
input  [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write;
    // data bus for hw loading of ctl_spares.
input  ctl_paq_hw_write;  // data bus for hw loading of ctl_paq.
input  ctl_vaq_hw_write;  // data bus for hw loading of ctl_vaq.
input  ctl_tpl_hw_write;  // data bus for hw loading of ctl_tpl.
input  ctl_tip_hw_write;  // data bus for hw loading of ctl_tip.
input  [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write;  // data bus for hw
                                                              // loading of
                                                              // ctl_tcm.

//====================================================================
//     Type declarations
//====================================================================
// synopsys translate_off
  wire omni_ld;  // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
  wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH - 1:0] omni_data;  // Omni write data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk;  // Clock signal
wire rst_l;  // Reset signal
wire w_ld;  // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data;  // SW read data
wire [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write;  // data bus
                                                                  // for hw
                                                                  // loading of
                                                                  // ctl_spares.
wire ctl_paq_hw_write;  // data bus for hw loading of ctl_paq.
wire ctl_vaq_hw_write;  // data bus for hw loading of ctl_vaq.
wire ctl_tpl_hw_write;  // data bus for hw loading of ctl_tpl.
wire ctl_tip_hw_write;  // data bus for hw loading of ctl_tip.
wire [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write;  // data bus for hw
                                                            // loading of
                                                            // ctl_tcm.

//====================================================================
//     Logic     
//====================================================================

//----- Reset values
// verilint 531 off
wire [3:0] reset_spares = 4'h0;
wire [0:0] reset_paq = 1'h0;
wire [0:0] reset_vaq = 1'h0;
wire [0:0] reset_tpl = 1'h0;
wire [0:0] reset_tip = 1'h0;
wire [1:0] reset_tcm = 2'h0;
wire [3:0] reset_sparec = 4'h0;
wire [0:0] reset_pd = 1'h0;
wire [0:0] reset_se = 1'h0;
wire [1:0] reset_cm = 2'h0;
wire [0:0] reset_busid_sel = 1'h0;
wire [0:0] reset_sun4v_en = 1'h0;
wire [0:0] reset_be = 1'h0;
wire [0:0] reset_te = 1'h0;
// verilint 531 on

//----- Active high reset wires 
wire rst_l_active_high = ~rst_l;

//====================================================
//     Instantiation of flops
//====================================================

// bit 0
csr_sw csr_sw_0
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[0]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_te[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[0]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[0])
	);

// bit 1
csr_sw csr_sw_1
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[1]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_be[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[1]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[1])
	);

// bit 2
csr_sw csr_sw_2
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[2]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sun4v_en[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[2]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[2])
	);

// bit 3
csr_sw csr_sw_3
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[3]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_busid_sel[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[3]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[3])
	);

assign  ctl_csrbus_read_data[4] = 1'b0;  // bit 4
assign  ctl_csrbus_read_data[5] = 1'b0;  // bit 5
assign  ctl_csrbus_read_data[6] = 1'b0;  // bit 6
assign  ctl_csrbus_read_data[7] = 1'b0;  // bit 7
// bit 8
csr_sw csr_sw_8
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[8]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_cm[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[8]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[8])
	);

// bit 9
csr_sw csr_sw_9
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[9]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_cm[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[9]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[9])
	);

// bit 10
csr_sw csr_sw_10
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[10]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_se[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[10]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[10])
	);

assign  ctl_csrbus_read_data[11] = 1'b0;  // bit 11
// bit 12
csr_sw csr_sw_12
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[12]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_pd[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[12]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[12])
	);

assign  ctl_csrbus_read_data[13] = 1'b0;  // bit 13
assign  ctl_csrbus_read_data[14] = 1'b0;  // bit 14
assign  ctl_csrbus_read_data[15] = 1'b0;  // bit 15
// bit 16
csr_sw csr_sw_16
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[16]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sparec[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[16]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[16])
	);

// bit 17
csr_sw csr_sw_17
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[17]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sparec[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[17]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[17])
	);

// bit 18
csr_sw csr_sw_18
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[18]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sparec[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[18]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[18])
	);

// bit 19
csr_sw csr_sw_19
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[19]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_sparec[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[19]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[19])
	);

assign  ctl_csrbus_read_data[20] = 1'b0;  // bit 20
assign  ctl_csrbus_read_data[21] = 1'b0;  // bit 21
assign  ctl_csrbus_read_data[22] = 1'b0;  // bit 22
assign  ctl_csrbus_read_data[23] = 1'b0;  // bit 23
assign  ctl_csrbus_read_data[24] = 1'b0;  // bit 24
assign  ctl_csrbus_read_data[25] = 1'b0;  // bit 25
assign  ctl_csrbus_read_data[26] = 1'b0;  // bit 26
assign  ctl_csrbus_read_data[27] = 1'b0;  // bit 27
assign  ctl_csrbus_read_data[28] = 1'b0;  // bit 28
assign  ctl_csrbus_read_data[29] = 1'b0;  // bit 29
assign  ctl_csrbus_read_data[30] = 1'b0;  // bit 30
assign  ctl_csrbus_read_data[31] = 1'b0;  // bit 31
assign  ctl_csrbus_read_data[32] = 1'b0;  // bit 32
assign  ctl_csrbus_read_data[33] = 1'b0;  // bit 33
assign  ctl_csrbus_read_data[34] = 1'b0;  // bit 34
assign  ctl_csrbus_read_data[35] = 1'b0;  // bit 35
assign  ctl_csrbus_read_data[36] = 1'b0;  // bit 36
assign  ctl_csrbus_read_data[37] = 1'b0;  // bit 37
assign  ctl_csrbus_read_data[38] = 1'b0;  // bit 38
assign  ctl_csrbus_read_data[39] = 1'b0;  // bit 39
// bit 40
csr_sw csr_sw_40
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_tcm[0]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_tcm_hw_write[0]),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[40])
	);

// bit 41
csr_sw csr_sw_41
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_tcm[1]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_tcm_hw_write[1]),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[41])
	);

// bit 42
csr_sw csr_sw_42
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_tip[0]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_tip_hw_write),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[42])
	);

// bit 43
csr_sw csr_sw_43
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_tpl[0]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_tpl_hw_write),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[43])
	);

// bit 44
csr_sw csr_sw_44
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_vaq[0]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_vaq_hw_write),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[44])
	);

// bit 45
csr_sw csr_sw_45
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_paq[0]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_paq_hw_write),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[45])
	);

assign  ctl_csrbus_read_data[46] = 1'b0;  // bit 46
assign  ctl_csrbus_read_data[47] = 1'b0;  // bit 47
// bit 48
csr_sw csr_sw_48
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_spares[0]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_spares_hw_write[0]),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[48])
	);

// bit 49
csr_sw csr_sw_49
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_spares[1]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_spares_hw_write[1]),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[49])
	);

// bit 50
csr_sw csr_sw_50
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_spares[2]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_spares_hw_write[2]),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[50])
	);

// bit 51
csr_sw csr_sw_51
	(
	// synopsys translate_off
	  .omni_ld         (1'b0),
	  .omni_data       (1'b0),
	  .omni_rw_alias   (1'b0),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (rst_l_active_high),
	.rst_val        (reset_spares[3]),
	.csr_ld         (1'b0),
	.csr_data       (1'b0),
	.rw_alias       (1'b0),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b1),
	.hw_data        (ctl_spares_hw_write[3]),
	.cp             (clk),
	.q              (ctl_csrbus_read_data[51])
	);

assign  ctl_csrbus_read_data[52] = 1'b0;  // bit 52
assign  ctl_csrbus_read_data[53] = 1'b0;  // bit 53
assign  ctl_csrbus_read_data[54] = 1'b0;  // bit 54
assign  ctl_csrbus_read_data[55] = 1'b0;  // bit 55
assign  ctl_csrbus_read_data[56] = 1'b0;  // bit 56
assign  ctl_csrbus_read_data[57] = 1'b0;  // bit 57
assign  ctl_csrbus_read_data[58] = 1'b0;  // bit 58
assign  ctl_csrbus_read_data[59] = 1'b0;  // bit 59
assign  ctl_csrbus_read_data[60] = 1'b0;  // bit 60
assign  ctl_csrbus_read_data[61] = 1'b0;  // bit 61
assign  ctl_csrbus_read_data[62] = 1'b0;  // bit 62
assign  ctl_csrbus_read_data[63] = 1'b0;  // bit 63

endmodule // dmu_mmu_csr_ctl_entry
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_mmu_csr_ctl_entry.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_mmu_csr_ctl_entry
	36	(
	37	// synopsys translate_off
	38	omni_ld,
	39	omni_data,
	40	// synopsys translate_on
	41	clk,
	42	rst_l,
	43	w_ld,
	44	csrbus_wr_data,
	45	ctl_csrbus_read_data,
	46	ctl_spares_hw_write,
	47	ctl_paq_hw_write,
	48	ctl_vaq_hw_write,
	49	ctl_tpl_hw_write,
	50	ctl_tip_hw_write,
	51	ctl_tcm_hw_write
	52	);
	53
	54	//====================================================================
	55	// Polarity declarations
	56	//====================================================================
	57	// synopsys translate_off
	58	input omni_ld; // Omni load
	59	// vlint flag_input_port_not_connected off
	60	input [`FIRE_DLC_MMU_CSR_CTL_WIDTH - 1:0] omni_data; // Omni write data
	61	// synopsys translate_on
	62	// vlint flag_input_port_not_connected on
	63	input clk; // Clock signal
	64	input rst_l; // Reset signal
65	input w_ld; // SW load
66	// vlint flag_input_port_not_connected off
67	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
68	// vlint flag_input_port_not_connected on
69	output [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // SW read data
70	input [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write;
71	// data bus for hw loading of ctl_spares.
72	input ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
73	input ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
74	input ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
75	input ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
76	input [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
77	// loading of
78	// ctl_tcm.
79
80	//====================================================================
81	// Type declarations
82	//====================================================================
83	// synopsys translate_off
84	wire omni_ld; // Omni load
85	// vlint flag_dangling_net_within_module off
86	// vlint flag_net_has_no_load off
87	wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH - 1:0] omni_data; // Omni write data
88	// synopsys translate_on
89	// vlint flag_dangling_net_within_module on
90	// vlint flag_net_has_no_load on
91	wire clk; // Clock signal
92	wire rst_l; // Reset signal
93	wire w_ld; // SW load
94	// vlint flag_dangling_net_within_module off
95	// vlint flag_net_has_no_load off
96	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
97	// vlint flag_dangling_net_within_module on
98	// vlint flag_net_has_no_load on
99	wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // SW read data
100	wire [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write; // data bus
101	// for hw
102	// loading of
103	// ctl_spares.
104	wire ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
105	wire ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
106	wire ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
107	wire ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
108	wire [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
109	// loading of
110	// ctl_tcm.
111
112	//====================================================================
113	// Logic
114	//====================================================================
115
116	//----- Reset values
117	// verilint 531 off
118	wire [3:0] reset_spares = 4'h0;
119	wire [0:0] reset_paq = 1'h0;
120	wire [0:0] reset_vaq = 1'h0;
121	wire [0:0] reset_tpl = 1'h0;
122	wire [0:0] reset_tip = 1'h0;
123	wire [1:0] reset_tcm = 2'h0;
124	wire [3:0] reset_sparec = 4'h0;
125	wire [0:0] reset_pd = 1'h0;
126	wire [0:0] reset_se = 1'h0;
127	wire [1:0] reset_cm = 2'h0;
128	wire [0:0] reset_busid_sel = 1'h0;
129	wire [0:0] reset_sun4v_en = 1'h0;
130	wire [0:0] reset_be = 1'h0;
131	wire [0:0] reset_te = 1'h0;
132	// verilint 531 on
133
134	//----- Active high reset wires
135	wire rst_l_active_high = ~rst_l;
136
137	//====================================================
138	// Instantiation of flops
139	//====================================================
140
141	// bit 0
142	csr_sw csr_sw_0
143	(
144	// synopsys translate_off
145	.omni_ld (omni_ld),
146	.omni_data (omni_data[0]),
147	.omni_rw_alias (1'b1),
148	.omni_rw1c_alias (1'b0),
149	.omni_rw1s_alias (1'b0),
150	// synopsys translate_on
151	.rst (rst_l_active_high),
152	.rst_val (reset_te[0]),
153	.csr_ld (w_ld),
154	.csr_data (csrbus_wr_data[0]),
155	.rw_alias (1'b1),
156	.rw1c_alias (1'b0),
157	.rw1s_alias (1'b0),
158	.hw_ld (1'b0),
159	.hw_data (1'b0),
160	.cp (clk),
161	.q (ctl_csrbus_read_data[0])
162	);
163
164	// bit 1
165	csr_sw csr_sw_1
166	(
167	// synopsys translate_off
168	.omni_ld (omni_ld),
169	.omni_data (omni_data[1]),
170	.omni_rw_alias (1'b1),
171	.omni_rw1c_alias (1'b0),
172	.omni_rw1s_alias (1'b0),
173	// synopsys translate_on
174	.rst (rst_l_active_high),
175	.rst_val (reset_be[0]),
176	.csr_ld (w_ld),
177	.csr_data (csrbus_wr_data[1]),
178	.rw_alias (1'b1),
179	.rw1c_alias (1'b0),
180	.rw1s_alias (1'b0),
181	.hw_ld (1'b0),
182	.hw_data (1'b0),
183	.cp (clk),
184	.q (ctl_csrbus_read_data[1])
185	);
186
187	// bit 2
188	csr_sw csr_sw_2
189	(
190	// synopsys translate_off
191	.omni_ld (omni_ld),
192	.omni_data (omni_data[2]),
193	.omni_rw_alias (1'b1),
194	.omni_rw1c_alias (1'b0),
195	.omni_rw1s_alias (1'b0),
196	// synopsys translate_on
197	.rst (rst_l_active_high),
198	.rst_val (reset_sun4v_en[0]),
199	.csr_ld (w_ld),
200	.csr_data (csrbus_wr_data[2]),
201	.rw_alias (1'b1),
202	.rw1c_alias (1'b0),
203	.rw1s_alias (1'b0),
204	.hw_ld (1'b0),
205	.hw_data (1'b0),
206	.cp (clk),
207	.q (ctl_csrbus_read_data[2])
208	);
209
210	// bit 3
211	csr_sw csr_sw_3
212	(
213	// synopsys translate_off
214	.omni_ld (omni_ld),
215	.omni_data (omni_data[3]),
216	.omni_rw_alias (1'b1),
217	.omni_rw1c_alias (1'b0),
218	.omni_rw1s_alias (1'b0),
219	// synopsys translate_on
220	.rst (rst_l_active_high),
221	.rst_val (reset_busid_sel[0]),
222	.csr_ld (w_ld),
223	.csr_data (csrbus_wr_data[3]),
224	.rw_alias (1'b1),
225	.rw1c_alias (1'b0),
226	.rw1s_alias (1'b0),
227	.hw_ld (1'b0),
228	.hw_data (1'b0),
229	.cp (clk),
230	.q (ctl_csrbus_read_data[3])
231	);
232
233	assign ctl_csrbus_read_data[4] = 1'b0; // bit 4
234	assign ctl_csrbus_read_data[5] = 1'b0; // bit 5
235	assign ctl_csrbus_read_data[6] = 1'b0; // bit 6
236	assign ctl_csrbus_read_data[7] = 1'b0; // bit 7
237	// bit 8
238	csr_sw csr_sw_8
239	(
240	// synopsys translate_off
241	.omni_ld (omni_ld),
242	.omni_data (omni_data[8]),
243	.omni_rw_alias (1'b1),
244	.omni_rw1c_alias (1'b0),
245	.omni_rw1s_alias (1'b0),
246	// synopsys translate_on
247	.rst (rst_l_active_high),
248	.rst_val (reset_cm[0]),
249	.csr_ld (w_ld),
250	.csr_data (csrbus_wr_data[8]),
251	.rw_alias (1'b1),
252	.rw1c_alias (1'b0),
253	.rw1s_alias (1'b0),
254	.hw_ld (1'b0),
255	.hw_data (1'b0),
256	.cp (clk),
257	.q (ctl_csrbus_read_data[8])
258	);
259
260	// bit 9
261	csr_sw csr_sw_9
262	(
263	// synopsys translate_off
264	.omni_ld (omni_ld),
265	.omni_data (omni_data[9]),
266	.omni_rw_alias (1'b1),
267	.omni_rw1c_alias (1'b0),
268	.omni_rw1s_alias (1'b0),
269	// synopsys translate_on
270	.rst (rst_l_active_high),
271	.rst_val (reset_cm[1]),
272	.csr_ld (w_ld),
273	.csr_data (csrbus_wr_data[9]),
274	.rw_alias (1'b1),
275	.rw1c_alias (1'b0),
276	.rw1s_alias (1'b0),
277	.hw_ld (1'b0),
278	.hw_data (1'b0),
279	.cp (clk),
280	.q (ctl_csrbus_read_data[9])
281	);
282
283	// bit 10
284	csr_sw csr_sw_10
285	(
286	// synopsys translate_off
287	.omni_ld (omni_ld),
288	.omni_data (omni_data[10]),
289	.omni_rw_alias (1'b1),
290	.omni_rw1c_alias (1'b0),
291	.omni_rw1s_alias (1'b0),
292	// synopsys translate_on
293	.rst (rst_l_active_high),
294	.rst_val (reset_se[0]),
295	.csr_ld (w_ld),
296	.csr_data (csrbus_wr_data[10]),
297	.rw_alias (1'b1),
298	.rw1c_alias (1'b0),
299	.rw1s_alias (1'b0),
300	.hw_ld (1'b0),
301	.hw_data (1'b0),
302	.cp (clk),
303	.q (ctl_csrbus_read_data[10])
304	);
305
306	assign ctl_csrbus_read_data[11] = 1'b0; // bit 11
307	// bit 12
308	csr_sw csr_sw_12
309	(
310	// synopsys translate_off
311	.omni_ld (omni_ld),
312	.omni_data (omni_data[12]),
313	.omni_rw_alias (1'b1),
314	.omni_rw1c_alias (1'b0),
315	.omni_rw1s_alias (1'b0),
316	// synopsys translate_on
317	.rst (rst_l_active_high),
318	.rst_val (reset_pd[0]),
319	.csr_ld (w_ld),
320	.csr_data (csrbus_wr_data[12]),
321	.rw_alias (1'b1),
322	.rw1c_alias (1'b0),
323	.rw1s_alias (1'b0),
324	.hw_ld (1'b0),
325	.hw_data (1'b0),
326	.cp (clk),
327	.q (ctl_csrbus_read_data[12])
328	);
329
330	assign ctl_csrbus_read_data[13] = 1'b0; // bit 13
331	assign ctl_csrbus_read_data[14] = 1'b0; // bit 14
332	assign ctl_csrbus_read_data[15] = 1'b0; // bit 15
333	// bit 16
334	csr_sw csr_sw_16
335	(
336	// synopsys translate_off
337	.omni_ld (omni_ld),
338	.omni_data (omni_data[16]),
339	.omni_rw_alias (1'b1),
340	.omni_rw1c_alias (1'b0),
341	.omni_rw1s_alias (1'b0),
342	// synopsys translate_on
343	.rst (rst_l_active_high),
344	.rst_val (reset_sparec[0]),
345	.csr_ld (w_ld),
346	.csr_data (csrbus_wr_data[16]),
347	.rw_alias (1'b1),
348	.rw1c_alias (1'b0),
349	.rw1s_alias (1'b0),
350	.hw_ld (1'b0),
351	.hw_data (1'b0),
352	.cp (clk),
353	.q (ctl_csrbus_read_data[16])
354	);
355
356	// bit 17
357	csr_sw csr_sw_17
358	(
359	// synopsys translate_off
360	.omni_ld (omni_ld),
361	.omni_data (omni_data[17]),
362	.omni_rw_alias (1'b1),
363	.omni_rw1c_alias (1'b0),
364	.omni_rw1s_alias (1'b0),
365	// synopsys translate_on
366	.rst (rst_l_active_high),
367	.rst_val (reset_sparec[1]),
368	.csr_ld (w_ld),
369	.csr_data (csrbus_wr_data[17]),
370	.rw_alias (1'b1),
371	.rw1c_alias (1'b0),
372	.rw1s_alias (1'b0),
373	.hw_ld (1'b0),
374	.hw_data (1'b0),
375	.cp (clk),
376	.q (ctl_csrbus_read_data[17])
377	);
378
379	// bit 18
380	csr_sw csr_sw_18
381	(
382	// synopsys translate_off
383	.omni_ld (omni_ld),
384	.omni_data (omni_data[18]),
385	.omni_rw_alias (1'b1),
386	.omni_rw1c_alias (1'b0),
387	.omni_rw1s_alias (1'b0),
388	// synopsys translate_on
389	.rst (rst_l_active_high),
390	.rst_val (reset_sparec[2]),
391	.csr_ld (w_ld),
392	.csr_data (csrbus_wr_data[18]),
393	.rw_alias (1'b1),
394	.rw1c_alias (1'b0),
395	.rw1s_alias (1'b0),
396	.hw_ld (1'b0),
397	.hw_data (1'b0),
398	.cp (clk),
399	.q (ctl_csrbus_read_data[18])
400	);
401
402	// bit 19
403	csr_sw csr_sw_19
404	(
405	// synopsys translate_off
406	.omni_ld (omni_ld),
407	.omni_data (omni_data[19]),
408	.omni_rw_alias (1'b1),
409	.omni_rw1c_alias (1'b0),
410	.omni_rw1s_alias (1'b0),
411	// synopsys translate_on
412	.rst (rst_l_active_high),
413	.rst_val (reset_sparec[3]),
414	.csr_ld (w_ld),
415	.csr_data (csrbus_wr_data[19]),
416	.rw_alias (1'b1),
417	.rw1c_alias (1'b0),
418	.rw1s_alias (1'b0),
419	.hw_ld (1'b0),
420	.hw_data (1'b0),
421	.cp (clk),
422	.q (ctl_csrbus_read_data[19])
423	);
424
425	assign ctl_csrbus_read_data[20] = 1'b0; // bit 20
426	assign ctl_csrbus_read_data[21] = 1'b0; // bit 21
427	assign ctl_csrbus_read_data[22] = 1'b0; // bit 22
428	assign ctl_csrbus_read_data[23] = 1'b0; // bit 23
429	assign ctl_csrbus_read_data[24] = 1'b0; // bit 24
430	assign ctl_csrbus_read_data[25] = 1'b0; // bit 25
431	assign ctl_csrbus_read_data[26] = 1'b0; // bit 26
432	assign ctl_csrbus_read_data[27] = 1'b0; // bit 27
433	assign ctl_csrbus_read_data[28] = 1'b0; // bit 28
434	assign ctl_csrbus_read_data[29] = 1'b0; // bit 29
435	assign ctl_csrbus_read_data[30] = 1'b0; // bit 30
436	assign ctl_csrbus_read_data[31] = 1'b0; // bit 31
437	assign ctl_csrbus_read_data[32] = 1'b0; // bit 32
438	assign ctl_csrbus_read_data[33] = 1'b0; // bit 33
439	assign ctl_csrbus_read_data[34] = 1'b0; // bit 34
440	assign ctl_csrbus_read_data[35] = 1'b0; // bit 35
441	assign ctl_csrbus_read_data[36] = 1'b0; // bit 36
442	assign ctl_csrbus_read_data[37] = 1'b0; // bit 37
443	assign ctl_csrbus_read_data[38] = 1'b0; // bit 38
444	assign ctl_csrbus_read_data[39] = 1'b0; // bit 39
445	// bit 40
446	csr_sw csr_sw_40
447	(
448	// synopsys translate_off
449	.omni_ld (1'b0),
450	.omni_data (1'b0),
451	.omni_rw_alias (1'b0),
452	.omni_rw1c_alias (1'b0),
453	.omni_rw1s_alias (1'b0),
454	// synopsys translate_on
455	.rst (rst_l_active_high),
456	.rst_val (reset_tcm[0]),
457	.csr_ld (1'b0),
458	.csr_data (1'b0),
459	.rw_alias (1'b0),
460	.rw1c_alias (1'b0),
461	.rw1s_alias (1'b0),
462	.hw_ld (1'b1),
463	.hw_data (ctl_tcm_hw_write[0]),
464	.cp (clk),
465	.q (ctl_csrbus_read_data[40])
466	);
467
468	// bit 41
469	csr_sw csr_sw_41
470	(
471	// synopsys translate_off
472	.omni_ld (1'b0),
473	.omni_data (1'b0),
474	.omni_rw_alias (1'b0),
475	.omni_rw1c_alias (1'b0),
476	.omni_rw1s_alias (1'b0),
477	// synopsys translate_on
478	.rst (rst_l_active_high),
479	.rst_val (reset_tcm[1]),
480	.csr_ld (1'b0),
481	.csr_data (1'b0),
482	.rw_alias (1'b0),
483	.rw1c_alias (1'b0),
484	.rw1s_alias (1'b0),
485	.hw_ld (1'b1),
486	.hw_data (ctl_tcm_hw_write[1]),
487	.cp (clk),
488	.q (ctl_csrbus_read_data[41])
489	);
490
491	// bit 42
492	csr_sw csr_sw_42
493	(
494	// synopsys translate_off
495	.omni_ld (1'b0),
496	.omni_data (1'b0),
497	.omni_rw_alias (1'b0),
498	.omni_rw1c_alias (1'b0),
499	.omni_rw1s_alias (1'b0),
500	// synopsys translate_on
501	.rst (rst_l_active_high),
502	.rst_val (reset_tip[0]),
503	.csr_ld (1'b0),
504	.csr_data (1'b0),
505	.rw_alias (1'b0),
506	.rw1c_alias (1'b0),
507	.rw1s_alias (1'b0),
508	.hw_ld (1'b1),
509	.hw_data (ctl_tip_hw_write),
510	.cp (clk),
511	.q (ctl_csrbus_read_data[42])
512	);
513
514	// bit 43
515	csr_sw csr_sw_43
516	(
517	// synopsys translate_off
518	.omni_ld (1'b0),
519	.omni_data (1'b0),
520	.omni_rw_alias (1'b0),
521	.omni_rw1c_alias (1'b0),
522	.omni_rw1s_alias (1'b0),
523	// synopsys translate_on
524	.rst (rst_l_active_high),
525	.rst_val (reset_tpl[0]),
526	.csr_ld (1'b0),
527	.csr_data (1'b0),
528	.rw_alias (1'b0),
529	.rw1c_alias (1'b0),
530	.rw1s_alias (1'b0),
531	.hw_ld (1'b1),
532	.hw_data (ctl_tpl_hw_write),
533	.cp (clk),
534	.q (ctl_csrbus_read_data[43])
535	);
536
537	// bit 44
538	csr_sw csr_sw_44
539	(
540	// synopsys translate_off
541	.omni_ld (1'b0),
542	.omni_data (1'b0),
543	.omni_rw_alias (1'b0),
544	.omni_rw1c_alias (1'b0),
545	.omni_rw1s_alias (1'b0),
546	// synopsys translate_on
547	.rst (rst_l_active_high),
548	.rst_val (reset_vaq[0]),
549	.csr_ld (1'b0),
550	.csr_data (1'b0),
551	.rw_alias (1'b0),
552	.rw1c_alias (1'b0),
553	.rw1s_alias (1'b0),
554	.hw_ld (1'b1),
555	.hw_data (ctl_vaq_hw_write),
556	.cp (clk),
557	.q (ctl_csrbus_read_data[44])
558	);
559
560	// bit 45
561	csr_sw csr_sw_45
562	(
563	// synopsys translate_off
564	.omni_ld (1'b0),
565	.omni_data (1'b0),
566	.omni_rw_alias (1'b0),
567	.omni_rw1c_alias (1'b0),
568	.omni_rw1s_alias (1'b0),
569	// synopsys translate_on
570	.rst (rst_l_active_high),
571	.rst_val (reset_paq[0]),
572	.csr_ld (1'b0),
573	.csr_data (1'b0),
574	.rw_alias (1'b0),
575	.rw1c_alias (1'b0),
576	.rw1s_alias (1'b0),
577	.hw_ld (1'b1),
578	.hw_data (ctl_paq_hw_write),
579	.cp (clk),
580	.q (ctl_csrbus_read_data[45])
581	);
582
583	assign ctl_csrbus_read_data[46] = 1'b0; // bit 46
584	assign ctl_csrbus_read_data[47] = 1'b0; // bit 47
585	// bit 48
586	csr_sw csr_sw_48
587	(
588	// synopsys translate_off
589	.omni_ld (1'b0),
590	.omni_data (1'b0),
591	.omni_rw_alias (1'b0),
592	.omni_rw1c_alias (1'b0),
593	.omni_rw1s_alias (1'b0),
594	// synopsys translate_on
595	.rst (rst_l_active_high),
596	.rst_val (reset_spares[0]),
597	.csr_ld (1'b0),
598	.csr_data (1'b0),
599	.rw_alias (1'b0),
600	.rw1c_alias (1'b0),
601	.rw1s_alias (1'b0),
602	.hw_ld (1'b1),
603	.hw_data (ctl_spares_hw_write[0]),
604	.cp (clk),
605	.q (ctl_csrbus_read_data[48])
606	);
607
608	// bit 49
609	csr_sw csr_sw_49
610	(
611	// synopsys translate_off
612	.omni_ld (1'b0),
613	.omni_data (1'b0),
614	.omni_rw_alias (1'b0),
615	.omni_rw1c_alias (1'b0),
616	.omni_rw1s_alias (1'b0),
617	// synopsys translate_on
618	.rst (rst_l_active_high),
619	.rst_val (reset_spares[1]),
620	.csr_ld (1'b0),
621	.csr_data (1'b0),
622	.rw_alias (1'b0),
623	.rw1c_alias (1'b0),
624	.rw1s_alias (1'b0),
625	.hw_ld (1'b1),
626	.hw_data (ctl_spares_hw_write[1]),
627	.cp (clk),
628	.q (ctl_csrbus_read_data[49])
629	);
630
631	// bit 50
632	csr_sw csr_sw_50
633	(
634	// synopsys translate_off
635	.omni_ld (1'b0),
636	.omni_data (1'b0),
637	.omni_rw_alias (1'b0),
638	.omni_rw1c_alias (1'b0),
639	.omni_rw1s_alias (1'b0),
640	// synopsys translate_on
641	.rst (rst_l_active_high),
642	.rst_val (reset_spares[2]),
643	.csr_ld (1'b0),
644	.csr_data (1'b0),
645	.rw_alias (1'b0),
646	.rw1c_alias (1'b0),
647	.rw1s_alias (1'b0),
648	.hw_ld (1'b1),
649	.hw_data (ctl_spares_hw_write[2]),
650	.cp (clk),
651	.q (ctl_csrbus_read_data[50])
652	);
653
654	// bit 51
655	csr_sw csr_sw_51
656	(
657	// synopsys translate_off
658	.omni_ld (1'b0),
659	.omni_data (1'b0),
660	.omni_rw_alias (1'b0),
661	.omni_rw1c_alias (1'b0),
662	.omni_rw1s_alias (1'b0),
663	// synopsys translate_on
664	.rst (rst_l_active_high),
665	.rst_val (reset_spares[3]),
666	.csr_ld (1'b0),
667	.csr_data (1'b0),
668	.rw_alias (1'b0),
669	.rw1c_alias (1'b0),
670	.rw1s_alias (1'b0),
671	.hw_ld (1'b1),
672	.hw_data (ctl_spares_hw_write[3]),
673	.cp (clk),
674	.q (ctl_csrbus_read_data[51])
675	);
676
677	assign ctl_csrbus_read_data[52] = 1'b0; // bit 52
678	assign ctl_csrbus_read_data[53] = 1'b0; // bit 53
679	assign ctl_csrbus_read_data[54] = 1'b0; // bit 54
680	assign ctl_csrbus_read_data[55] = 1'b0; // bit 55
681	assign ctl_csrbus_read_data[56] = 1'b0; // bit 56
682	assign ctl_csrbus_read_data[57] = 1'b0; // bit 57
683	assign ctl_csrbus_read_data[58] = 1'b0; // bit 58
684	assign ctl_csrbus_read_data[59] = 1'b0; // bit 59
685	assign ctl_csrbus_read_data[60] = 1'b0; // bit 60
686	assign ctl_csrbus_read_data[61] = 1'b0; // bit 61
687	assign ctl_csrbus_read_data[62] = 1'b0; // bit 62
688	assign ctl_csrbus_read_data[63] = 1'b0; // bit 63
689
690	endmodule // dmu_mmu_csr_ctl_entry