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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_default_grp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_mmu_csr_default_grp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_mmu_csr_default_grp
36 (
37 clk,
38 ctl_spares_hw_write,
39 ctl_paq_hw_write,
40 ctl_vaq_hw_write,
41 ctl_tpl_hw_write,
42 ctl_tip_hw_write,
43 ctl_tcm_hw_write,
44 ctl_sparec_hw_read,
45 ctl_pd_hw_read,
46 ctl_se_hw_read,
47 ctl_cm_hw_read,
48 ctl_busid_sel_hw_read,
49 ctl_sun4v_en_hw_read,
50 ctl_be_hw_read,
51 ctl_te_hw_read,
52 ctl_select_pulse,
53 tsb_tb_hw_read,
54 tsb_ps_hw_read,
55 tsb_ts_hw_read,
56 tsb_select_pulse,
57 fsh_select_pulse,
58 inv_ext_select,
59 inv_select,
60 log_en_hw_read,
61 log_select_pulse,
62 int_en_hw_read,
63 int_en_select_pulse,
64 en_err_select,
65 en_err_ext_read_data,
66 err_hw_set,
67 err_hw_read,
68 err_select_pulse,
69 flta_va_hw_ld,
70 flta_va_hw_write,
71 flta_select_pulse,
72 flts_entry_hw_ld,
73 flts_entry_hw_write,
74 flts_type_hw_ld,
75 flts_type_hw_write,
76 flts_id_hw_ld,
77 flts_id_hw_write,
78 flts_select_pulse,
79 prfc_sel1_hw_read,
80 prfc_sel0_hw_read,
81 prfc_select_pulse,
82 prf0_cnt_hw_write,
83 prf0_cnt_hw_read,
84 prf0_select_pulse,
85 prf1_cnt_hw_write,
86 prf1_cnt_hw_read,
87 prf1_select_pulse,
88 vtb_ext_select,
89 vtb_select,
90 vtb_ext_read_data,
91 ptb_ext_select,
92 ptb_select,
93 ptb_ext_read_data,
94 tdb_ext_select,
95 tdb_select,
96 tdb_ext_read_data,
97 dev2iotsb_ext_select,
98 dev2iotsb_select,
99 dev2iotsb_ext_read_data,
100 dev2iotsb_ext_done,
101 IotsbDesc_ext_select,
102 IotsbDesc_select,
103 IotsbDesc_ext_read_data,
104 IotsbDesc_ext_done,
105 err_rw1c_alias,
106 err_rw1s_alias,
107 rst_l,
108 por_l,
109 daemon_csrbus_wr_in,
110 daemon_csrbus_wr_out,
111 daemon_csrbus_wr_data_in,
112 daemon_csrbus_wr_data_out,
113 ext_addr_in,
114 ext_addr_out,
115 read_data_0_out,
116 read_data_1_out,
117 ext_done_0_out
118 );
119
120//====================================================
121// Polarity declarations
122//====================================================
123input clk; // Clock signal
124input [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write;
125 // data bus for hw loading of ctl_spares.
126input ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
127input ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
128input ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
129input ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
130input [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
131 // loading of
132 // ctl_tcm.
133output [`FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC] ctl_sparec_hw_read;
134 // This signal provides the current value of ctl_sparec.
135output ctl_pd_hw_read; // This signal provides the current value of ctl_pd.
136output ctl_se_hw_read; // This signal provides the current value of ctl_se.
137output [`FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC] ctl_cm_hw_read; // This signal
138 // provides the
139 // current value of
140 // ctl_cm.
141output ctl_busid_sel_hw_read; // This signal provides the current value of
142 // ctl_busid_sel.
143output ctl_sun4v_en_hw_read; // This signal provides the current value of
144 // ctl_sun4v_en.
145output ctl_be_hw_read; // This signal provides the current value of ctl_be.
146output ctl_te_hw_read; // This signal provides the current value of ctl_te.
147input ctl_select_pulse; // select
148output [`FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC] tsb_tb_hw_read; // This signal
149 // provides the
150 // current value of
151 // tsb_tb.
152output tsb_ps_hw_read; // This signal provides the current value of tsb_ps.
153output [`FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC] tsb_ts_hw_read; // This signal
154 // provides the
155 // current value of
156 // tsb_ts.
157input tsb_select_pulse; // select
158input fsh_select_pulse; // select
159output inv_ext_select; // When set, register inv is selected. This signal is a
160 // pulse.
161input inv_select; // select
162output [`FIRE_DLC_MMU_CSR_LOG_EN_INT_SLC] log_en_hw_read; // This signal
163 // provides the
164 // current value of
165 // log_en.
166input log_select_pulse; // select
167output [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_hw_read; // This signal
168 // provides the
169 // current value of
170 // int_en.
171input int_en_select_pulse; // select
172input en_err_select; // select
173input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] en_err_ext_read_data; // Read Data
174input [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_set; // Hardware set
175 // signal for
176 // err. When
177 // set err will
178 // be set to
179 // one.
180output [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_read; // This signal
181 // provides
182 // the current
183 // value of
184 // err.
185input err_select_pulse; // select
186input flta_va_hw_ld; // Hardware load enable for flta_va. When set, <hw write
187 // signal> will be loaded into flta.
188input [`FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC] flta_va_hw_write; // data bus for hw
189 // loading of
190 // flta_va.
191input flta_select_pulse; // select
192input flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw
193 // write signal> will be loaded into flts.
194input [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write;
195 // data bus for hw loading of flts_entry.
196input flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw
197 // write signal> will be loaded into flts.
198input [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus
199 // for hw
200 // loading of
201 // flts_type.
202input flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write
203 // signal> will be loaded into flts.
204input [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw
205 // loading of
206 // flts_id.
207input flts_select_pulse; // select
208output [`FIRE_DLC_MMU_CSR_PRFC_SEL1_INT_SLC] prfc_sel1_hw_read; // This signal
209 // provides the
210 // current
211 // value of
212 // prfc_sel1.
213output [`FIRE_DLC_MMU_CSR_PRFC_SEL0_INT_SLC] prfc_sel0_hw_read; // This signal
214 // provides the
215 // current
216 // value of
217 // prfc_sel0.
218input prfc_select_pulse; // select
219input [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_write; // data bus for
220 // hw loading of
221 // prf0_cnt.
222output [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_read; // This signal
223 // provides the
224 // current value
225 // of prf0_cnt.
226input prf0_select_pulse; // select
227input [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_write; // data bus for
228 // hw loading of
229 // prf1_cnt.
230output [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_read; // This signal
231 // provides the
232 // current value
233 // of prf1_cnt.
234input prf1_select_pulse; // select
235output vtb_ext_select; // When set, register vtb is selected. This signal is a
236 // pulse.
237input vtb_select; // select
238input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] vtb_ext_read_data; // Read Data
239output ptb_ext_select; // When set, register ptb is selected. This signal is a
240 // pulse.
241input ptb_select; // select
242input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] ptb_ext_read_data; // Read Data
243output tdb_ext_select; // When set, register tdb is selected. This signal is a
244 // pulse.
245input tdb_select; // select
246input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] tdb_ext_read_data; // Read Data
247output dev2iotsb_ext_select; // When set, register dev2iotsb is selected. This
248 // signal is a pulse.
249input dev2iotsb_select; // select
250input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] dev2iotsb_ext_read_data; // Read Data
251input dev2iotsb_ext_done; // ExtDone
252output IotsbDesc_ext_select; // When set, register IotsbDesc is selected. This
253 // signal is a pulse.
254input IotsbDesc_select; // select
255input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] IotsbDesc_ext_read_data; // Read Data
256input IotsbDesc_ext_done; // ExtDone
257input err_rw1c_alias; // SW load
258input err_rw1s_alias; // SW load
259input rst_l; // HW reset
260input por_l; // HW reset
261input daemon_csrbus_wr_in; // csrbus_wr
262output daemon_csrbus_wr_out; // csrbus_wr
263input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
264output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write
265 // data
266input [8:0] ext_addr_in; // Ext addr
267output [8:0] ext_addr_out; // Ext addr
268output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
269output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1_out; // Read Data
270output ext_done_0_out; // Ext Done
271
272//====================================================
273// Type declarations
274//====================================================
275wire clk; // Clock signal
276wire [`FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC] ctl_spares_hw_write; // data bus
277 // for hw
278 // loading of
279 // ctl_spares.
280wire ctl_paq_hw_write; // data bus for hw loading of ctl_paq.
281wire ctl_vaq_hw_write; // data bus for hw loading of ctl_vaq.
282wire ctl_tpl_hw_write; // data bus for hw loading of ctl_tpl.
283wire ctl_tip_hw_write; // data bus for hw loading of ctl_tip.
284wire [`FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC] ctl_tcm_hw_write; // data bus for hw
285 // loading of
286 // ctl_tcm.
287wire [`FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC] ctl_sparec_hw_read; // This signal
288 // provides the
289 // current
290 // value of
291 // ctl_sparec.
292wire ctl_pd_hw_read; // This signal provides the current value of ctl_pd.
293wire ctl_se_hw_read; // This signal provides the current value of ctl_se.
294wire [`FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC] ctl_cm_hw_read; // This signal provides
295 // the current value of
296 // ctl_cm.
297wire ctl_busid_sel_hw_read; // This signal provides the current value of
298 // ctl_busid_sel.
299wire ctl_sun4v_en_hw_read; // This signal provides the current value of
300 // ctl_sun4v_en.
301wire ctl_be_hw_read; // This signal provides the current value of ctl_be.
302wire ctl_te_hw_read; // This signal provides the current value of ctl_te.
303wire ctl_select_pulse; // select
304wire [`FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC] tsb_tb_hw_read; // This signal provides
305 // the current value of
306 // tsb_tb.
307wire tsb_ps_hw_read; // This signal provides the current value of tsb_ps.
308wire [`FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC] tsb_ts_hw_read; // This signal provides
309 // the current value of
310 // tsb_ts.
311wire tsb_select_pulse; // select
312wire fsh_select_pulse; // select
313wire inv_ext_select; // When set, register inv is selected. This signal is a
314 // pulse.
315wire inv_select; // select
316wire [`FIRE_DLC_MMU_CSR_LOG_EN_INT_SLC] log_en_hw_read; // This signal provides
317 // the current value of
318 // log_en.
319wire log_select_pulse; // select
320wire [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_hw_read; // This signal
321 // provides the
322 // current value of
323 // int_en.
324wire int_en_select_pulse; // select
325wire en_err_select; // select
326wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] en_err_ext_read_data; // Read Data
327wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_set; // Hardware set
328 // signal for
329 // err. When set
330 // err will be
331 // set to one.
332wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_read; // This signal
333 // provides the
334 // current value
335 // of err.
336wire err_select_pulse; // select
337wire flta_va_hw_ld; // Hardware load enable for flta_va. When set, <hw write
338 // signal> will be loaded into flta.
339wire [`FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC] flta_va_hw_write; // data bus for hw
340 // loading of
341 // flta_va.
342wire flta_select_pulse; // select
343wire flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw
344 // write signal> will be loaded into flts.
345wire [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; // data bus
346 // for hw
347 // loading of
348 // flts_entry.
349wire flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw
350 // write signal> will be loaded into flts.
351wire [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus for
352 // hw loading of
353 // flts_type.
354wire flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write
355 // signal> will be loaded into flts.
356wire [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw
357 // loading of
358 // flts_id.
359wire flts_select_pulse; // select
360wire [`FIRE_DLC_MMU_CSR_PRFC_SEL1_INT_SLC] prfc_sel1_hw_read; // This signal
361 // provides the
362 // current value
363 // of prfc_sel1.
364wire [`FIRE_DLC_MMU_CSR_PRFC_SEL0_INT_SLC] prfc_sel0_hw_read; // This signal
365 // provides the
366 // current value
367 // of prfc_sel0.
368wire prfc_select_pulse; // select
369wire [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_write; // data bus for hw
370 // loading of
371 // prf0_cnt.
372wire [`FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC] prf0_cnt_hw_read; // This signal
373 // provides the
374 // current value of
375 // prf0_cnt.
376wire prf0_select_pulse; // select
377wire [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_write; // data bus for hw
378 // loading of
379 // prf1_cnt.
380wire [`FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC] prf1_cnt_hw_read; // This signal
381 // provides the
382 // current value of
383 // prf1_cnt.
384wire prf1_select_pulse; // select
385wire vtb_ext_select; // When set, register vtb is selected. This signal is a
386 // pulse.
387wire vtb_select; // select
388wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] vtb_ext_read_data; // Read Data
389wire ptb_ext_select; // When set, register ptb is selected. This signal is a
390 // pulse.
391wire ptb_select; // select
392wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] ptb_ext_read_data; // Read Data
393wire tdb_ext_select; // When set, register tdb is selected. This signal is a
394 // pulse.
395wire tdb_select; // select
396wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] tdb_ext_read_data; // Read Data
397wire dev2iotsb_ext_select; // When set, register dev2iotsb is selected. This
398 // signal is a pulse.
399wire dev2iotsb_select; // select
400wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] dev2iotsb_ext_read_data; // Read Data
401wire dev2iotsb_ext_done; // ExtDone
402wire IotsbDesc_ext_select; // When set, register IotsbDesc is selected. This
403 // signal is a pulse.
404wire IotsbDesc_select; // select
405wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] IotsbDesc_ext_read_data; // Read Data
406wire IotsbDesc_ext_done; // ExtDone
407wire err_rw1c_alias; // SW load
408wire err_rw1s_alias; // SW load
409wire rst_l; // HW reset
410wire por_l; // HW reset
411wire daemon_csrbus_wr_in; // csrbus_wr
412wire daemon_csrbus_wr_out; // csrbus_wr
413wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
414wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data
415wire [8:0] ext_addr_in; // Ext addr
416wire [8:0] ext_addr_out; // Ext addr
417wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
418wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1_out; // Read Data
419reg ext_done_0_out; // Ext Done
420
421
422//====================================================
423// Local signals
424//====================================================
425//----- For CSR register: ctl
426wire [`FIRE_DLC_MMU_CSR_CTL_WIDTH-1:0] ctl_csrbus_read_data; // Entry Based
427 // Read Data
428
429//----- For CSR register: tsb
430wire [`FIRE_DLC_MMU_CSR_TSB_WIDTH-1:0] tsb_csrbus_read_data; // Entry Based
431 // Read Data
432
433//----- For CSR register: fsh
434wire [`FIRE_DLC_MMU_CSR_FSH_WIDTH-1:0] fsh_csrbus_read_data; // Entry Based
435 // Read Data
436
437//----- For CSR register: log
438wire [`FIRE_DLC_MMU_CSR_LOG_WIDTH-1:0] log_csrbus_read_data; // Entry Based
439 // Read Data
440
441//----- For CSR register: int_en
442wire [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_csrbus_read_data;
443 // Entry Based Read Data
444
445//----- For CSR register: err
446wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_csrbus_read_data;
447 // Entry Based Read Data
448
449//----- For CSR register: flta
450wire [`FIRE_DLC_MMU_CSR_FLTA_WIDTH-1:0] flta_csrbus_read_data; // Entry Based
451 // Read Data
452
453//----- For CSR register: flts
454wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // Entry Based
455 // Read Data
456
457//----- For CSR register: prfc
458wire [`FIRE_DLC_MMU_CSR_PRFC_WIDTH-1:0] prfc_csrbus_read_data; // Entry Based
459 // Read Data
460
461//----- For CSR register: prf0
462wire [`FIRE_DLC_MMU_CSR_PRF0_WIDTH-1:0] prf0_csrbus_read_data; // Entry Based
463 // Read Data
464
465//----- For CSR register: prf1
466wire [`FIRE_DLC_MMU_CSR_PRF1_WIDTH-1:0] prf1_csrbus_read_data; // Entry Based
467 // Read Data
468
469
470//====================================================
471// Pipelining (First stage)
472//====================================================
473//----- delayed select for ext_select
474reg inv_select_piped;
475reg inv_select_piped_delayed;
476reg vtb_select_piped;
477reg vtb_select_piped_delayed;
478reg ptb_select_piped;
479reg ptb_select_piped_delayed;
480reg tdb_select_piped;
481reg tdb_select_piped_delayed;
482reg dev2iotsb_select_piped;
483reg dev2iotsb_select_piped_delayed;
484reg IotsbDesc_select_piped;
485reg IotsbDesc_select_piped_delayed;
486
487always @(posedge clk)
488 begin
489 if(~rst_l)
490 begin
491 ext_done_0_out <= 1'b0;
492 inv_select_piped <= 1'b0;
493 inv_select_piped_delayed <= 1'b0;
494 vtb_select_piped <= 1'b0;
495 vtb_select_piped_delayed <= 1'b0;
496 ptb_select_piped <= 1'b0;
497 ptb_select_piped_delayed <= 1'b0;
498 tdb_select_piped <= 1'b0;
499 tdb_select_piped_delayed <= 1'b0;
500 dev2iotsb_select_piped <= 1'b0;
501 dev2iotsb_select_piped_delayed <= 1'b0;
502 IotsbDesc_select_piped <= 1'b0;
503 IotsbDesc_select_piped_delayed <= 1'b0;
504 end
505 else
506 begin
507 ext_done_0_out <=
508 dev2iotsb_ext_done |
509 IotsbDesc_ext_done;
510
511 inv_select_piped <= inv_select;
512 inv_select_piped_delayed <= inv_select_piped;
513 vtb_select_piped <= vtb_select;
514 vtb_select_piped_delayed <= vtb_select_piped;
515 ptb_select_piped <= ptb_select;
516 ptb_select_piped_delayed <= ptb_select_piped;
517 tdb_select_piped <= tdb_select;
518 tdb_select_piped_delayed <= tdb_select_piped;
519 dev2iotsb_select_piped <= dev2iotsb_select;
520 dev2iotsb_select_piped_delayed <= dev2iotsb_select_piped;
521 IotsbDesc_select_piped <= IotsbDesc_select;
522 IotsbDesc_select_piped_delayed <= IotsbDesc_select_piped;
523 end
524 end
525
526//====================================================
527// Assignments only (first stage)
528//====================================================
529wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in;
530wire daemon_csrbus_wr = daemon_csrbus_wr_in;
531assign daemon_csrbus_wr_out = daemon_csrbus_wr_in;
532assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in;
533assign ext_addr_out = ext_addr_in;
534
535//====================================================
536// Automatic hw_ld / hw_write
537//====================================================
538
539//====================================================
540// Extern select
541//====================================================
542assign inv_ext_select =
543 inv_select_piped&
544 ~inv_select_piped_delayed;
545
546// inv_ext_select is a pulse
547/* 0in assert_timer -name inv_ext_select_pulse
548 -var inv_ext_select -max 1
549 -message "inv_ext_select pulse length is not 1"
550 -clock clk
551*/
552
553assign vtb_ext_select =
554 vtb_select_piped&
555 ~vtb_select_piped_delayed;
556
557// vtb_ext_select is a pulse
558/* 0in assert_timer -name vtb_ext_select_pulse
559 -var vtb_ext_select -max 1
560 -message "vtb_ext_select pulse length is not 1"
561 -clock clk
562*/
563
564assign ptb_ext_select =
565 ptb_select_piped&
566 ~ptb_select_piped_delayed;
567
568// ptb_ext_select is a pulse
569/* 0in assert_timer -name ptb_ext_select_pulse
570 -var ptb_ext_select -max 1
571 -message "ptb_ext_select pulse length is not 1"
572 -clock clk
573*/
574
575assign tdb_ext_select =
576 tdb_select_piped&
577 ~tdb_select_piped_delayed;
578
579// tdb_ext_select is a pulse
580/* 0in assert_timer -name tdb_ext_select_pulse
581 -var tdb_ext_select -max 1
582 -message "tdb_ext_select pulse length is not 1"
583 -clock clk
584*/
585
586assign dev2iotsb_ext_select =
587 dev2iotsb_select_piped&
588 ~dev2iotsb_select_piped_delayed;
589
590// dev2iotsb_ext_select is a pulse
591/* 0in assert_timer -name dev2iotsb_ext_select_pulse
592 -var dev2iotsb_ext_select -max 1
593 -message "dev2iotsb_ext_select pulse length is not 1"
594 -clock clk
595*/
596
597assign IotsbDesc_ext_select =
598 IotsbDesc_select_piped&
599 ~IotsbDesc_select_piped_delayed;
600
601// IotsbDesc_ext_select is a pulse
602/* 0in assert_timer -name IotsbDesc_ext_select_pulse
603 -var IotsbDesc_ext_select -max 1
604 -message "IotsbDesc_ext_select pulse length is not 1"
605 -clock clk
606*/
607
608
609//=====================================================
610// OUTPUT: read_data_out
611//=====================================================
612dmu_mmu_csr_csrpipe_15 dmu_mmu_csr_csrpipe_15_inst_1
613 (
614 .clk (clk),
615 .rst_l (rst_l),
616 .reg_in (1'b1),
617 .reg_out (1'b1),
618 .data0 (ctl_csrbus_read_data),
619 .sel0 (ctl_select_pulse),
620 .data1 (tsb_csrbus_read_data),
621 .sel1 (tsb_select_pulse),
622 .data2 (fsh_csrbus_read_data),
623 .sel2 (fsh_select_pulse),
624 .data3 (log_csrbus_read_data),
625 .sel3 (log_select_pulse),
626 .data4 (int_en_csrbus_read_data),
627 .sel4 (int_en_select_pulse),
628 .data5 (en_err_ext_read_data),
629 .sel5 (en_err_select),
630 .data6 (err_csrbus_read_data),
631 .sel6 (err_select_pulse),
632 .data7 (flta_csrbus_read_data),
633 .sel7 (flta_select_pulse),
634 .data8 (flts_csrbus_read_data),
635 .sel8 (flts_select_pulse),
636 .data9 (prfc_csrbus_read_data),
637 .sel9 (prfc_select_pulse),
638 .data10 (prf0_csrbus_read_data),
639 .sel10 (prf0_select_pulse),
640 .data11 (prf1_csrbus_read_data),
641 .sel11 (prf1_select_pulse),
642 .data12 (vtb_ext_read_data),
643 .sel12 (vtb_select),
644 .data13 (ptb_ext_read_data),
645 .sel13 (ptb_select),
646 .data14 (tdb_ext_read_data),
647 .sel14 (tdb_select),
648 .out (read_data_0_out)
649 );
650
651dmu_mmu_csr_csrpipe_15 dmu_mmu_csr_csrpipe_15_inst_2
652 (
653 .clk (clk),
654 .rst_l (rst_l),
655 .reg_in (1'b1),
656 .reg_out (1'b1),
657 .data0 (dev2iotsb_ext_read_data),
658 .sel0 (dev2iotsb_select),
659 .data1 (IotsbDesc_ext_read_data),
660 .sel1 (IotsbDesc_select),
661 .data2 (64'b0),
662 .sel2 (1'b1),
663 .data3 (64'b0),
664 .sel3 (1'b1),
665 .data4 (64'b0),
666 .sel4 (1'b1),
667 .data5 (64'b0),
668 .sel5 (1'b1),
669 .data6 (64'b0),
670 .sel6 (1'b1),
671 .data7 (64'b0),
672 .sel7 (1'b1),
673 .data8 (64'b0),
674 .sel8 (1'b1),
675 .data9 (64'b0),
676 .sel9 (1'b1),
677 .data10 (64'b0),
678 .sel10 (1'b1),
679 .data11 (64'b0),
680 .sel11 (1'b1),
681 .data12 (64'b0),
682 .sel12 (1'b1),
683 .data13 (64'b0),
684 .sel13 (1'b1),
685 .data14 (64'b0),
686 .sel14 (1'b1),
687 .out (read_data_1_out)
688 );
689
690
691//====================================================
692// Instantiation of registers
693//====================================================
694
695wire ctl_w_ld =ctl_select_pulse & daemon_csrbus_wr;
696
697dmu_mmu_csr_ctl ctl
698 (
699 .clk (clk),
700 .rst_l (rst_l),
701 .ctl_w_ld (ctl_w_ld),
702 .csrbus_wr_data (daemon_csrbus_wr_data),
703 .ctl_csrbus_read_data (ctl_csrbus_read_data),
704 .ctl_spares_hw_write (ctl_spares_hw_write),
705 .ctl_paq_hw_write (ctl_paq_hw_write),
706 .ctl_vaq_hw_write (ctl_vaq_hw_write),
707 .ctl_tpl_hw_write (ctl_tpl_hw_write),
708 .ctl_tip_hw_write (ctl_tip_hw_write),
709 .ctl_tcm_hw_write (ctl_tcm_hw_write),
710 .ctl_sparec_hw_read (ctl_sparec_hw_read),
711 .ctl_pd_hw_read (ctl_pd_hw_read),
712 .ctl_se_hw_read (ctl_se_hw_read),
713 .ctl_cm_hw_read (ctl_cm_hw_read),
714 .ctl_busid_sel_hw_read (ctl_busid_sel_hw_read),
715 .ctl_sun4v_en_hw_read (ctl_sun4v_en_hw_read),
716 .ctl_be_hw_read (ctl_be_hw_read),
717 .ctl_te_hw_read (ctl_te_hw_read)
718 );
719
720wire tsb_w_ld =tsb_select_pulse & daemon_csrbus_wr;
721
722dmu_mmu_csr_tsb tsb
723 (
724 .clk (clk),
725 .rst_l (rst_l),
726 .tsb_w_ld (tsb_w_ld),
727 .csrbus_wr_data (daemon_csrbus_wr_data),
728 .tsb_csrbus_read_data (tsb_csrbus_read_data),
729 .tsb_tb_hw_read (tsb_tb_hw_read),
730 .tsb_ps_hw_read (tsb_ps_hw_read),
731 .tsb_ts_hw_read (tsb_ts_hw_read)
732 );
733
734wire fsh_w_ld =fsh_select_pulse & daemon_csrbus_wr;
735
736dmu_mmu_csr_fsh fsh
737 (
738 .clk (clk),
739 .rst_l (rst_l),
740 .fsh_w_ld (fsh_w_ld),
741 .csrbus_wr_data (daemon_csrbus_wr_data),
742 .fsh_csrbus_read_data (fsh_csrbus_read_data)
743 );
744
745wire log_w_ld =log_select_pulse & daemon_csrbus_wr;
746
747dmu_mmu_csr_log log
748 (
749 .clk (clk),
750 .por_l (por_l),
751 .log_w_ld (log_w_ld),
752 .csrbus_wr_data (daemon_csrbus_wr_data),
753 .log_csrbus_read_data (log_csrbus_read_data),
754 .log_en_hw_read (log_en_hw_read)
755 );
756
757wire int_en_w_ld =int_en_select_pulse & daemon_csrbus_wr;
758
759dmu_mmu_csr_int_en int_en
760 (
761 .clk (clk),
762 .rst_l (rst_l),
763 .int_en_w_ld (int_en_w_ld),
764 .csrbus_wr_data (daemon_csrbus_wr_data),
765 .int_en_csrbus_read_data (int_en_csrbus_read_data),
766 .int_en_hw_read (int_en_hw_read)
767 );
768
769wire err_w_ld =err_select_pulse & daemon_csrbus_wr;
770
771dmu_mmu_csr_err err
772 (
773 .clk (clk),
774 .por_l (por_l),
775 .err_w_ld (err_w_ld),
776 .csrbus_wr_data (daemon_csrbus_wr_data),
777 .rw1c_alias (err_rw1c_alias),
778 .rw1s_alias (err_rw1s_alias),
779 .err_csrbus_read_data (err_csrbus_read_data),
780 .err_hw_set (err_hw_set),
781 .err_hw_read (err_hw_read)
782 );
783
784wire flta_w_ld =flta_select_pulse & daemon_csrbus_wr;
785
786dmu_mmu_csr_flta flta
787 (
788 .clk (clk),
789 .por_l (por_l),
790 .flta_w_ld (flta_w_ld),
791 .csrbus_wr_data (daemon_csrbus_wr_data),
792 .flta_csrbus_read_data (flta_csrbus_read_data),
793 .flta_va_hw_ld (flta_va_hw_ld),
794 .flta_va_hw_write (flta_va_hw_write)
795 );
796
797wire flts_w_ld =flts_select_pulse & daemon_csrbus_wr;
798
799dmu_mmu_csr_flts flts
800 (
801 .clk (clk),
802 .por_l (por_l),
803 .flts_w_ld (flts_w_ld),
804 .csrbus_wr_data (daemon_csrbus_wr_data),
805 .flts_csrbus_read_data (flts_csrbus_read_data),
806 .flts_entry_hw_ld (flts_entry_hw_ld),
807 .flts_entry_hw_write (flts_entry_hw_write),
808 .flts_type_hw_ld (flts_type_hw_ld),
809 .flts_type_hw_write (flts_type_hw_write),
810 .flts_id_hw_ld (flts_id_hw_ld),
811 .flts_id_hw_write (flts_id_hw_write)
812 );
813
814wire prfc_w_ld =prfc_select_pulse & daemon_csrbus_wr;
815
816dmu_mmu_csr_prfc prfc
817 (
818 .clk (clk),
819 .rst_l (rst_l),
820 .prfc_w_ld (prfc_w_ld),
821 .csrbus_wr_data (daemon_csrbus_wr_data),
822 .prfc_csrbus_read_data (prfc_csrbus_read_data),
823 .prfc_sel1_hw_read (prfc_sel1_hw_read),
824 .prfc_sel0_hw_read (prfc_sel0_hw_read)
825 );
826
827wire prf0_w_ld =prf0_select_pulse & daemon_csrbus_wr;
828
829dmu_mmu_csr_prf0 prf0
830 (
831 .clk (clk),
832 .rst_l (rst_l),
833 .prf0_w_ld (prf0_w_ld),
834 .csrbus_wr_data (daemon_csrbus_wr_data),
835 .prf0_csrbus_read_data (prf0_csrbus_read_data),
836 .prf0_cnt_hw_write (prf0_cnt_hw_write),
837 .prf0_cnt_hw_read (prf0_cnt_hw_read)
838 );
839
840wire prf1_w_ld =prf1_select_pulse & daemon_csrbus_wr;
841
842dmu_mmu_csr_prf1 prf1
843 (
844 .clk (clk),
845 .rst_l (rst_l),
846 .prf1_w_ld (prf1_w_ld),
847 .csrbus_wr_data (daemon_csrbus_wr_data),
848 .prf1_csrbus_read_data (prf1_csrbus_read_data),
849 .prf1_cnt_hw_write (prf1_cnt_hw_write),
850 .prf1_cnt_hw_read (prf1_cnt_hw_read)
851 );
852
853endmodule // dmu_mmu_csr_default_grp
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