Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_err.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_mmu_csr_err.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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module dmu_mmu_csr_err 
	(
	clk,
	por_l,
	err_w_ld,
	csrbus_wr_data,
	rw1c_alias,
	rw1s_alias,
	err_csrbus_read_data,
	err_hw_set,
	err_hw_read
	);

//====================================================================
//     Polarity declarations
//====================================================================
input  clk;  // Clock
input  por_l;  // Reset signal
input  err_w_ld;  // SW load bus
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
input  rw1c_alias;  // SW load type: write-one-to-clear
input  rw1s_alias;  // SW load type: write-one-to-set
output [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_csrbus_read_data;
    // SW read data
input  [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_set;  // Hardware set
                                                                 // signal for
                                                                 // err. When
                                                                 // set err will
                                                                 // be set to
                                                                 // one.
output [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_read;  // This signal
                                                                  // provides
                                                                  // the current
                                                                  // value of
                                                                  // err.

//====================================================================
//     Type declarations
//====================================================================
wire clk;  // Clock
wire por_l;  // Reset signal
wire err_w_ld;  // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
wire rw1c_alias;  // SW load type: write-one-to-clear
wire rw1s_alias;  // SW load type: write-one-to-set
wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_csrbus_read_data;
    // SW read data
wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_set;  // Hardware set
                                                               // signal for
                                                               // err. When set
                                                               // err will be
                                                               // set to one.
wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_hw_read;  // This signal
                                                                // provides the
                                                                // current value
                                                                // of err.

//====================================================================
//     Logic     
//====================================================================

// synopsys translate_off
// verilint 123 off
// verilint 498 off
reg omni_ld;
reg [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] omni_data;
reg omni_rw1c_alias;
reg omni_rw1s_alias;

// vlint flag_unsynthesizable_initial off
initial
  begin
     omni_ld         = 1'b0;
     omni_data       = `FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH'b0;
     omni_rw1c_alias   = 1'b0;
     omni_rw1s_alias   = 1'b0;
  end// vlint flag_unsynthesizable_initial on

// verilint 123 on
// verilint 498 on
// synopsys translate_on

//----- Hardware Data Out Mux Assignments
assign err_hw_read=
           err_csrbus_read_data
               [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0];

//====================================================================
//     Instantiation of entries
//====================================================================

//----- Entry 0
dmu_mmu_csr_err_entry err_0
	(
	// synopsys translate_off
	  .omni_ld	(omni_ld),
	  .omni_data	(omni_data),
	  .omni_rw1c_alias	(omni_rw1c_alias),
	  .omni_rw1s_alias	(omni_rw1s_alias),
	// synopsys translate_on
	.clk	(clk),
	.por_l	(por_l),
	.w_ld	(err_w_ld),
	.csrbus_wr_data	(csrbus_wr_data),
	.rw1c_alias	(rw1c_alias),
	.rw1s_alias	(rw1s_alias),
	.err_csrbus_read_data	(err_csrbus_read_data),
	.err_hw_set	(err_hw_set)
	);

endmodule // dmu_mmu_csr_err