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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_flts_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_flts_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | por_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | flts_csrbus_read_data, | |
46 | flts_entry_hw_ld, | |
47 | flts_entry_hw_write, | |
48 | flts_type_hw_ld, | |
49 | flts_type_hw_write, | |
50 | flts_id_hw_ld, | |
51 | flts_id_hw_write | |
52 | ); | |
53 | ||
54 | //==================================================================== | |
55 | // Polarity declarations | |
56 | //==================================================================== | |
57 | // synopsys translate_off | |
58 | input omni_ld; // Omni load | |
59 | // vlint flag_input_port_not_connected off | |
60 | input [`FIRE_DLC_MMU_CSR_FLTS_WIDTH - 1:0] omni_data; // Omni write data | |
61 | // synopsys translate_on | |
62 | // vlint flag_input_port_not_connected on | |
63 | input clk; // Clock signal | |
64 | input por_l; // Reset signal | |
65 | input w_ld; // SW load | |
66 | // vlint flag_input_port_not_connected off | |
67 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
68 | // vlint flag_input_port_not_connected on | |
69 | output [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // SW read | |
70 | // data | |
71 | input flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw | |
72 | // write signal> will be loaded into flts. | |
73 | input [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; | |
74 | // data bus for hw loading of flts_entry. | |
75 | input flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw | |
76 | // write signal> will be loaded into flts. | |
77 | input [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus | |
78 | // for hw | |
79 | // loading of | |
80 | // flts_type. | |
81 | input flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write | |
82 | // signal> will be loaded into flts. | |
83 | input [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw | |
84 | // loading of | |
85 | // flts_id. | |
86 | ||
87 | //==================================================================== | |
88 | // Type declarations | |
89 | //==================================================================== | |
90 | // synopsys translate_off | |
91 | wire omni_ld; // Omni load | |
92 | // vlint flag_dangling_net_within_module off | |
93 | // vlint flag_net_has_no_load off | |
94 | wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH - 1:0] omni_data; // Omni write data | |
95 | // synopsys translate_on | |
96 | // vlint flag_dangling_net_within_module on | |
97 | // vlint flag_net_has_no_load on | |
98 | wire clk; // Clock signal | |
99 | wire por_l; // Reset signal | |
100 | wire w_ld; // SW load | |
101 | // vlint flag_dangling_net_within_module off | |
102 | // vlint flag_net_has_no_load off | |
103 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
104 | // vlint flag_dangling_net_within_module on | |
105 | // vlint flag_net_has_no_load on | |
106 | wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // SW read data | |
107 | wire flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw | |
108 | // write signal> will be loaded into flts. | |
109 | wire [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; // data bus | |
110 | // for hw | |
111 | // loading of | |
112 | // flts_entry. | |
113 | wire flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw | |
114 | // write signal> will be loaded into flts. | |
115 | wire [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus for | |
116 | // hw loading of | |
117 | // flts_type. | |
118 | wire flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write | |
119 | // signal> will be loaded into flts. | |
120 | wire [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw | |
121 | // loading of | |
122 | // flts_id. | |
123 | ||
124 | //==================================================================== | |
125 | // Logic | |
126 | //==================================================================== | |
127 | ||
128 | //----- Reset values | |
129 | // verilint 531 off | |
130 | wire [8:0] reset_entry = 9'b0; | |
131 | wire [6:0] reset_type = 7'b0; | |
132 | wire [15:0] reset_id = 16'b0; | |
133 | // verilint 531 on | |
134 | ||
135 | //----- Active high reset wires | |
136 | wire por_l_active_high = ~por_l; | |
137 | ||
138 | //==================================================== | |
139 | // Instantiation of flops | |
140 | //==================================================== | |
141 | ||
142 | // bit 0 | |
143 | csr_sw csr_sw_0 | |
144 | ( | |
145 | // synopsys translate_off | |
146 | .omni_ld (omni_ld), | |
147 | .omni_data (omni_data[0]), | |
148 | .omni_rw_alias (1'b1), | |
149 | .omni_rw1c_alias (1'b0), | |
150 | .omni_rw1s_alias (1'b0), | |
151 | // synopsys translate_on | |
152 | .rst (por_l_active_high), | |
153 | .rst_val (reset_id[0]), | |
154 | .csr_ld (w_ld), | |
155 | .csr_data (csrbus_wr_data[0]), | |
156 | .rw_alias (1'b1), | |
157 | .rw1c_alias (1'b0), | |
158 | .rw1s_alias (1'b0), | |
159 | .hw_ld (flts_id_hw_ld), | |
160 | .hw_data (flts_id_hw_write[0]), | |
161 | .cp (clk), | |
162 | .q (flts_csrbus_read_data[0]) | |
163 | ); | |
164 | ||
165 | // bit 1 | |
166 | csr_sw csr_sw_1 | |
167 | ( | |
168 | // synopsys translate_off | |
169 | .omni_ld (omni_ld), | |
170 | .omni_data (omni_data[1]), | |
171 | .omni_rw_alias (1'b1), | |
172 | .omni_rw1c_alias (1'b0), | |
173 | .omni_rw1s_alias (1'b0), | |
174 | // synopsys translate_on | |
175 | .rst (por_l_active_high), | |
176 | .rst_val (reset_id[1]), | |
177 | .csr_ld (w_ld), | |
178 | .csr_data (csrbus_wr_data[1]), | |
179 | .rw_alias (1'b1), | |
180 | .rw1c_alias (1'b0), | |
181 | .rw1s_alias (1'b0), | |
182 | .hw_ld (flts_id_hw_ld), | |
183 | .hw_data (flts_id_hw_write[1]), | |
184 | .cp (clk), | |
185 | .q (flts_csrbus_read_data[1]) | |
186 | ); | |
187 | ||
188 | // bit 2 | |
189 | csr_sw csr_sw_2 | |
190 | ( | |
191 | // synopsys translate_off | |
192 | .omni_ld (omni_ld), | |
193 | .omni_data (omni_data[2]), | |
194 | .omni_rw_alias (1'b1), | |
195 | .omni_rw1c_alias (1'b0), | |
196 | .omni_rw1s_alias (1'b0), | |
197 | // synopsys translate_on | |
198 | .rst (por_l_active_high), | |
199 | .rst_val (reset_id[2]), | |
200 | .csr_ld (w_ld), | |
201 | .csr_data (csrbus_wr_data[2]), | |
202 | .rw_alias (1'b1), | |
203 | .rw1c_alias (1'b0), | |
204 | .rw1s_alias (1'b0), | |
205 | .hw_ld (flts_id_hw_ld), | |
206 | .hw_data (flts_id_hw_write[2]), | |
207 | .cp (clk), | |
208 | .q (flts_csrbus_read_data[2]) | |
209 | ); | |
210 | ||
211 | // bit 3 | |
212 | csr_sw csr_sw_3 | |
213 | ( | |
214 | // synopsys translate_off | |
215 | .omni_ld (omni_ld), | |
216 | .omni_data (omni_data[3]), | |
217 | .omni_rw_alias (1'b1), | |
218 | .omni_rw1c_alias (1'b0), | |
219 | .omni_rw1s_alias (1'b0), | |
220 | // synopsys translate_on | |
221 | .rst (por_l_active_high), | |
222 | .rst_val (reset_id[3]), | |
223 | .csr_ld (w_ld), | |
224 | .csr_data (csrbus_wr_data[3]), | |
225 | .rw_alias (1'b1), | |
226 | .rw1c_alias (1'b0), | |
227 | .rw1s_alias (1'b0), | |
228 | .hw_ld (flts_id_hw_ld), | |
229 | .hw_data (flts_id_hw_write[3]), | |
230 | .cp (clk), | |
231 | .q (flts_csrbus_read_data[3]) | |
232 | ); | |
233 | ||
234 | // bit 4 | |
235 | csr_sw csr_sw_4 | |
236 | ( | |
237 | // synopsys translate_off | |
238 | .omni_ld (omni_ld), | |
239 | .omni_data (omni_data[4]), | |
240 | .omni_rw_alias (1'b1), | |
241 | .omni_rw1c_alias (1'b0), | |
242 | .omni_rw1s_alias (1'b0), | |
243 | // synopsys translate_on | |
244 | .rst (por_l_active_high), | |
245 | .rst_val (reset_id[4]), | |
246 | .csr_ld (w_ld), | |
247 | .csr_data (csrbus_wr_data[4]), | |
248 | .rw_alias (1'b1), | |
249 | .rw1c_alias (1'b0), | |
250 | .rw1s_alias (1'b0), | |
251 | .hw_ld (flts_id_hw_ld), | |
252 | .hw_data (flts_id_hw_write[4]), | |
253 | .cp (clk), | |
254 | .q (flts_csrbus_read_data[4]) | |
255 | ); | |
256 | ||
257 | // bit 5 | |
258 | csr_sw csr_sw_5 | |
259 | ( | |
260 | // synopsys translate_off | |
261 | .omni_ld (omni_ld), | |
262 | .omni_data (omni_data[5]), | |
263 | .omni_rw_alias (1'b1), | |
264 | .omni_rw1c_alias (1'b0), | |
265 | .omni_rw1s_alias (1'b0), | |
266 | // synopsys translate_on | |
267 | .rst (por_l_active_high), | |
268 | .rst_val (reset_id[5]), | |
269 | .csr_ld (w_ld), | |
270 | .csr_data (csrbus_wr_data[5]), | |
271 | .rw_alias (1'b1), | |
272 | .rw1c_alias (1'b0), | |
273 | .rw1s_alias (1'b0), | |
274 | .hw_ld (flts_id_hw_ld), | |
275 | .hw_data (flts_id_hw_write[5]), | |
276 | .cp (clk), | |
277 | .q (flts_csrbus_read_data[5]) | |
278 | ); | |
279 | ||
280 | // bit 6 | |
281 | csr_sw csr_sw_6 | |
282 | ( | |
283 | // synopsys translate_off | |
284 | .omni_ld (omni_ld), | |
285 | .omni_data (omni_data[6]), | |
286 | .omni_rw_alias (1'b1), | |
287 | .omni_rw1c_alias (1'b0), | |
288 | .omni_rw1s_alias (1'b0), | |
289 | // synopsys translate_on | |
290 | .rst (por_l_active_high), | |
291 | .rst_val (reset_id[6]), | |
292 | .csr_ld (w_ld), | |
293 | .csr_data (csrbus_wr_data[6]), | |
294 | .rw_alias (1'b1), | |
295 | .rw1c_alias (1'b0), | |
296 | .rw1s_alias (1'b0), | |
297 | .hw_ld (flts_id_hw_ld), | |
298 | .hw_data (flts_id_hw_write[6]), | |
299 | .cp (clk), | |
300 | .q (flts_csrbus_read_data[6]) | |
301 | ); | |
302 | ||
303 | // bit 7 | |
304 | csr_sw csr_sw_7 | |
305 | ( | |
306 | // synopsys translate_off | |
307 | .omni_ld (omni_ld), | |
308 | .omni_data (omni_data[7]), | |
309 | .omni_rw_alias (1'b1), | |
310 | .omni_rw1c_alias (1'b0), | |
311 | .omni_rw1s_alias (1'b0), | |
312 | // synopsys translate_on | |
313 | .rst (por_l_active_high), | |
314 | .rst_val (reset_id[7]), | |
315 | .csr_ld (w_ld), | |
316 | .csr_data (csrbus_wr_data[7]), | |
317 | .rw_alias (1'b1), | |
318 | .rw1c_alias (1'b0), | |
319 | .rw1s_alias (1'b0), | |
320 | .hw_ld (flts_id_hw_ld), | |
321 | .hw_data (flts_id_hw_write[7]), | |
322 | .cp (clk), | |
323 | .q (flts_csrbus_read_data[7]) | |
324 | ); | |
325 | ||
326 | // bit 8 | |
327 | csr_sw csr_sw_8 | |
328 | ( | |
329 | // synopsys translate_off | |
330 | .omni_ld (omni_ld), | |
331 | .omni_data (omni_data[8]), | |
332 | .omni_rw_alias (1'b1), | |
333 | .omni_rw1c_alias (1'b0), | |
334 | .omni_rw1s_alias (1'b0), | |
335 | // synopsys translate_on | |
336 | .rst (por_l_active_high), | |
337 | .rst_val (reset_id[8]), | |
338 | .csr_ld (w_ld), | |
339 | .csr_data (csrbus_wr_data[8]), | |
340 | .rw_alias (1'b1), | |
341 | .rw1c_alias (1'b0), | |
342 | .rw1s_alias (1'b0), | |
343 | .hw_ld (flts_id_hw_ld), | |
344 | .hw_data (flts_id_hw_write[8]), | |
345 | .cp (clk), | |
346 | .q (flts_csrbus_read_data[8]) | |
347 | ); | |
348 | ||
349 | // bit 9 | |
350 | csr_sw csr_sw_9 | |
351 | ( | |
352 | // synopsys translate_off | |
353 | .omni_ld (omni_ld), | |
354 | .omni_data (omni_data[9]), | |
355 | .omni_rw_alias (1'b1), | |
356 | .omni_rw1c_alias (1'b0), | |
357 | .omni_rw1s_alias (1'b0), | |
358 | // synopsys translate_on | |
359 | .rst (por_l_active_high), | |
360 | .rst_val (reset_id[9]), | |
361 | .csr_ld (w_ld), | |
362 | .csr_data (csrbus_wr_data[9]), | |
363 | .rw_alias (1'b1), | |
364 | .rw1c_alias (1'b0), | |
365 | .rw1s_alias (1'b0), | |
366 | .hw_ld (flts_id_hw_ld), | |
367 | .hw_data (flts_id_hw_write[9]), | |
368 | .cp (clk), | |
369 | .q (flts_csrbus_read_data[9]) | |
370 | ); | |
371 | ||
372 | // bit 10 | |
373 | csr_sw csr_sw_10 | |
374 | ( | |
375 | // synopsys translate_off | |
376 | .omni_ld (omni_ld), | |
377 | .omni_data (omni_data[10]), | |
378 | .omni_rw_alias (1'b1), | |
379 | .omni_rw1c_alias (1'b0), | |
380 | .omni_rw1s_alias (1'b0), | |
381 | // synopsys translate_on | |
382 | .rst (por_l_active_high), | |
383 | .rst_val (reset_id[10]), | |
384 | .csr_ld (w_ld), | |
385 | .csr_data (csrbus_wr_data[10]), | |
386 | .rw_alias (1'b1), | |
387 | .rw1c_alias (1'b0), | |
388 | .rw1s_alias (1'b0), | |
389 | .hw_ld (flts_id_hw_ld), | |
390 | .hw_data (flts_id_hw_write[10]), | |
391 | .cp (clk), | |
392 | .q (flts_csrbus_read_data[10]) | |
393 | ); | |
394 | ||
395 | // bit 11 | |
396 | csr_sw csr_sw_11 | |
397 | ( | |
398 | // synopsys translate_off | |
399 | .omni_ld (omni_ld), | |
400 | .omni_data (omni_data[11]), | |
401 | .omni_rw_alias (1'b1), | |
402 | .omni_rw1c_alias (1'b0), | |
403 | .omni_rw1s_alias (1'b0), | |
404 | // synopsys translate_on | |
405 | .rst (por_l_active_high), | |
406 | .rst_val (reset_id[11]), | |
407 | .csr_ld (w_ld), | |
408 | .csr_data (csrbus_wr_data[11]), | |
409 | .rw_alias (1'b1), | |
410 | .rw1c_alias (1'b0), | |
411 | .rw1s_alias (1'b0), | |
412 | .hw_ld (flts_id_hw_ld), | |
413 | .hw_data (flts_id_hw_write[11]), | |
414 | .cp (clk), | |
415 | .q (flts_csrbus_read_data[11]) | |
416 | ); | |
417 | ||
418 | // bit 12 | |
419 | csr_sw csr_sw_12 | |
420 | ( | |
421 | // synopsys translate_off | |
422 | .omni_ld (omni_ld), | |
423 | .omni_data (omni_data[12]), | |
424 | .omni_rw_alias (1'b1), | |
425 | .omni_rw1c_alias (1'b0), | |
426 | .omni_rw1s_alias (1'b0), | |
427 | // synopsys translate_on | |
428 | .rst (por_l_active_high), | |
429 | .rst_val (reset_id[12]), | |
430 | .csr_ld (w_ld), | |
431 | .csr_data (csrbus_wr_data[12]), | |
432 | .rw_alias (1'b1), | |
433 | .rw1c_alias (1'b0), | |
434 | .rw1s_alias (1'b0), | |
435 | .hw_ld (flts_id_hw_ld), | |
436 | .hw_data (flts_id_hw_write[12]), | |
437 | .cp (clk), | |
438 | .q (flts_csrbus_read_data[12]) | |
439 | ); | |
440 | ||
441 | // bit 13 | |
442 | csr_sw csr_sw_13 | |
443 | ( | |
444 | // synopsys translate_off | |
445 | .omni_ld (omni_ld), | |
446 | .omni_data (omni_data[13]), | |
447 | .omni_rw_alias (1'b1), | |
448 | .omni_rw1c_alias (1'b0), | |
449 | .omni_rw1s_alias (1'b0), | |
450 | // synopsys translate_on | |
451 | .rst (por_l_active_high), | |
452 | .rst_val (reset_id[13]), | |
453 | .csr_ld (w_ld), | |
454 | .csr_data (csrbus_wr_data[13]), | |
455 | .rw_alias (1'b1), | |
456 | .rw1c_alias (1'b0), | |
457 | .rw1s_alias (1'b0), | |
458 | .hw_ld (flts_id_hw_ld), | |
459 | .hw_data (flts_id_hw_write[13]), | |
460 | .cp (clk), | |
461 | .q (flts_csrbus_read_data[13]) | |
462 | ); | |
463 | ||
464 | // bit 14 | |
465 | csr_sw csr_sw_14 | |
466 | ( | |
467 | // synopsys translate_off | |
468 | .omni_ld (omni_ld), | |
469 | .omni_data (omni_data[14]), | |
470 | .omni_rw_alias (1'b1), | |
471 | .omni_rw1c_alias (1'b0), | |
472 | .omni_rw1s_alias (1'b0), | |
473 | // synopsys translate_on | |
474 | .rst (por_l_active_high), | |
475 | .rst_val (reset_id[14]), | |
476 | .csr_ld (w_ld), | |
477 | .csr_data (csrbus_wr_data[14]), | |
478 | .rw_alias (1'b1), | |
479 | .rw1c_alias (1'b0), | |
480 | .rw1s_alias (1'b0), | |
481 | .hw_ld (flts_id_hw_ld), | |
482 | .hw_data (flts_id_hw_write[14]), | |
483 | .cp (clk), | |
484 | .q (flts_csrbus_read_data[14]) | |
485 | ); | |
486 | ||
487 | // bit 15 | |
488 | csr_sw csr_sw_15 | |
489 | ( | |
490 | // synopsys translate_off | |
491 | .omni_ld (omni_ld), | |
492 | .omni_data (omni_data[15]), | |
493 | .omni_rw_alias (1'b1), | |
494 | .omni_rw1c_alias (1'b0), | |
495 | .omni_rw1s_alias (1'b0), | |
496 | // synopsys translate_on | |
497 | .rst (por_l_active_high), | |
498 | .rst_val (reset_id[15]), | |
499 | .csr_ld (w_ld), | |
500 | .csr_data (csrbus_wr_data[15]), | |
501 | .rw_alias (1'b1), | |
502 | .rw1c_alias (1'b0), | |
503 | .rw1s_alias (1'b0), | |
504 | .hw_ld (flts_id_hw_ld), | |
505 | .hw_data (flts_id_hw_write[15]), | |
506 | .cp (clk), | |
507 | .q (flts_csrbus_read_data[15]) | |
508 | ); | |
509 | ||
510 | // bit 16 | |
511 | csr_sw csr_sw_16 | |
512 | ( | |
513 | // synopsys translate_off | |
514 | .omni_ld (omni_ld), | |
515 | .omni_data (omni_data[16]), | |
516 | .omni_rw_alias (1'b1), | |
517 | .omni_rw1c_alias (1'b0), | |
518 | .omni_rw1s_alias (1'b0), | |
519 | // synopsys translate_on | |
520 | .rst (por_l_active_high), | |
521 | .rst_val (reset_type[0]), | |
522 | .csr_ld (w_ld), | |
523 | .csr_data (csrbus_wr_data[16]), | |
524 | .rw_alias (1'b1), | |
525 | .rw1c_alias (1'b0), | |
526 | .rw1s_alias (1'b0), | |
527 | .hw_ld (flts_type_hw_ld), | |
528 | .hw_data (flts_type_hw_write[0]), | |
529 | .cp (clk), | |
530 | .q (flts_csrbus_read_data[16]) | |
531 | ); | |
532 | ||
533 | // bit 17 | |
534 | csr_sw csr_sw_17 | |
535 | ( | |
536 | // synopsys translate_off | |
537 | .omni_ld (omni_ld), | |
538 | .omni_data (omni_data[17]), | |
539 | .omni_rw_alias (1'b1), | |
540 | .omni_rw1c_alias (1'b0), | |
541 | .omni_rw1s_alias (1'b0), | |
542 | // synopsys translate_on | |
543 | .rst (por_l_active_high), | |
544 | .rst_val (reset_type[1]), | |
545 | .csr_ld (w_ld), | |
546 | .csr_data (csrbus_wr_data[17]), | |
547 | .rw_alias (1'b1), | |
548 | .rw1c_alias (1'b0), | |
549 | .rw1s_alias (1'b0), | |
550 | .hw_ld (flts_type_hw_ld), | |
551 | .hw_data (flts_type_hw_write[1]), | |
552 | .cp (clk), | |
553 | .q (flts_csrbus_read_data[17]) | |
554 | ); | |
555 | ||
556 | // bit 18 | |
557 | csr_sw csr_sw_18 | |
558 | ( | |
559 | // synopsys translate_off | |
560 | .omni_ld (omni_ld), | |
561 | .omni_data (omni_data[18]), | |
562 | .omni_rw_alias (1'b1), | |
563 | .omni_rw1c_alias (1'b0), | |
564 | .omni_rw1s_alias (1'b0), | |
565 | // synopsys translate_on | |
566 | .rst (por_l_active_high), | |
567 | .rst_val (reset_type[2]), | |
568 | .csr_ld (w_ld), | |
569 | .csr_data (csrbus_wr_data[18]), | |
570 | .rw_alias (1'b1), | |
571 | .rw1c_alias (1'b0), | |
572 | .rw1s_alias (1'b0), | |
573 | .hw_ld (flts_type_hw_ld), | |
574 | .hw_data (flts_type_hw_write[2]), | |
575 | .cp (clk), | |
576 | .q (flts_csrbus_read_data[18]) | |
577 | ); | |
578 | ||
579 | // bit 19 | |
580 | csr_sw csr_sw_19 | |
581 | ( | |
582 | // synopsys translate_off | |
583 | .omni_ld (omni_ld), | |
584 | .omni_data (omni_data[19]), | |
585 | .omni_rw_alias (1'b1), | |
586 | .omni_rw1c_alias (1'b0), | |
587 | .omni_rw1s_alias (1'b0), | |
588 | // synopsys translate_on | |
589 | .rst (por_l_active_high), | |
590 | .rst_val (reset_type[3]), | |
591 | .csr_ld (w_ld), | |
592 | .csr_data (csrbus_wr_data[19]), | |
593 | .rw_alias (1'b1), | |
594 | .rw1c_alias (1'b0), | |
595 | .rw1s_alias (1'b0), | |
596 | .hw_ld (flts_type_hw_ld), | |
597 | .hw_data (flts_type_hw_write[3]), | |
598 | .cp (clk), | |
599 | .q (flts_csrbus_read_data[19]) | |
600 | ); | |
601 | ||
602 | // bit 20 | |
603 | csr_sw csr_sw_20 | |
604 | ( | |
605 | // synopsys translate_off | |
606 | .omni_ld (omni_ld), | |
607 | .omni_data (omni_data[20]), | |
608 | .omni_rw_alias (1'b1), | |
609 | .omni_rw1c_alias (1'b0), | |
610 | .omni_rw1s_alias (1'b0), | |
611 | // synopsys translate_on | |
612 | .rst (por_l_active_high), | |
613 | .rst_val (reset_type[4]), | |
614 | .csr_ld (w_ld), | |
615 | .csr_data (csrbus_wr_data[20]), | |
616 | .rw_alias (1'b1), | |
617 | .rw1c_alias (1'b0), | |
618 | .rw1s_alias (1'b0), | |
619 | .hw_ld (flts_type_hw_ld), | |
620 | .hw_data (flts_type_hw_write[4]), | |
621 | .cp (clk), | |
622 | .q (flts_csrbus_read_data[20]) | |
623 | ); | |
624 | ||
625 | // bit 21 | |
626 | csr_sw csr_sw_21 | |
627 | ( | |
628 | // synopsys translate_off | |
629 | .omni_ld (omni_ld), | |
630 | .omni_data (omni_data[21]), | |
631 | .omni_rw_alias (1'b1), | |
632 | .omni_rw1c_alias (1'b0), | |
633 | .omni_rw1s_alias (1'b0), | |
634 | // synopsys translate_on | |
635 | .rst (por_l_active_high), | |
636 | .rst_val (reset_type[5]), | |
637 | .csr_ld (w_ld), | |
638 | .csr_data (csrbus_wr_data[21]), | |
639 | .rw_alias (1'b1), | |
640 | .rw1c_alias (1'b0), | |
641 | .rw1s_alias (1'b0), | |
642 | .hw_ld (flts_type_hw_ld), | |
643 | .hw_data (flts_type_hw_write[5]), | |
644 | .cp (clk), | |
645 | .q (flts_csrbus_read_data[21]) | |
646 | ); | |
647 | ||
648 | // bit 22 | |
649 | csr_sw csr_sw_22 | |
650 | ( | |
651 | // synopsys translate_off | |
652 | .omni_ld (omni_ld), | |
653 | .omni_data (omni_data[22]), | |
654 | .omni_rw_alias (1'b1), | |
655 | .omni_rw1c_alias (1'b0), | |
656 | .omni_rw1s_alias (1'b0), | |
657 | // synopsys translate_on | |
658 | .rst (por_l_active_high), | |
659 | .rst_val (reset_type[6]), | |
660 | .csr_ld (w_ld), | |
661 | .csr_data (csrbus_wr_data[22]), | |
662 | .rw_alias (1'b1), | |
663 | .rw1c_alias (1'b0), | |
664 | .rw1s_alias (1'b0), | |
665 | .hw_ld (flts_type_hw_ld), | |
666 | .hw_data (flts_type_hw_write[6]), | |
667 | .cp (clk), | |
668 | .q (flts_csrbus_read_data[22]) | |
669 | ); | |
670 | ||
671 | assign flts_csrbus_read_data[23] = 1'b0; // bit 23 | |
672 | assign flts_csrbus_read_data[24] = 1'b0; // bit 24 | |
673 | assign flts_csrbus_read_data[25] = 1'b0; // bit 25 | |
674 | assign flts_csrbus_read_data[26] = 1'b0; // bit 26 | |
675 | assign flts_csrbus_read_data[27] = 1'b0; // bit 27 | |
676 | assign flts_csrbus_read_data[28] = 1'b0; // bit 28 | |
677 | assign flts_csrbus_read_data[29] = 1'b0; // bit 29 | |
678 | assign flts_csrbus_read_data[30] = 1'b0; // bit 30 | |
679 | assign flts_csrbus_read_data[31] = 1'b0; // bit 31 | |
680 | // bit 32 | |
681 | csr_sw csr_sw_32 | |
682 | ( | |
683 | // synopsys translate_off | |
684 | .omni_ld (omni_ld), | |
685 | .omni_data (omni_data[32]), | |
686 | .omni_rw_alias (1'b1), | |
687 | .omni_rw1c_alias (1'b0), | |
688 | .omni_rw1s_alias (1'b0), | |
689 | // synopsys translate_on | |
690 | .rst (por_l_active_high), | |
691 | .rst_val (reset_entry[0]), | |
692 | .csr_ld (w_ld), | |
693 | .csr_data (csrbus_wr_data[32]), | |
694 | .rw_alias (1'b1), | |
695 | .rw1c_alias (1'b0), | |
696 | .rw1s_alias (1'b0), | |
697 | .hw_ld (flts_entry_hw_ld), | |
698 | .hw_data (flts_entry_hw_write[0]), | |
699 | .cp (clk), | |
700 | .q (flts_csrbus_read_data[32]) | |
701 | ); | |
702 | ||
703 | // bit 33 | |
704 | csr_sw csr_sw_33 | |
705 | ( | |
706 | // synopsys translate_off | |
707 | .omni_ld (omni_ld), | |
708 | .omni_data (omni_data[33]), | |
709 | .omni_rw_alias (1'b1), | |
710 | .omni_rw1c_alias (1'b0), | |
711 | .omni_rw1s_alias (1'b0), | |
712 | // synopsys translate_on | |
713 | .rst (por_l_active_high), | |
714 | .rst_val (reset_entry[1]), | |
715 | .csr_ld (w_ld), | |
716 | .csr_data (csrbus_wr_data[33]), | |
717 | .rw_alias (1'b1), | |
718 | .rw1c_alias (1'b0), | |
719 | .rw1s_alias (1'b0), | |
720 | .hw_ld (flts_entry_hw_ld), | |
721 | .hw_data (flts_entry_hw_write[1]), | |
722 | .cp (clk), | |
723 | .q (flts_csrbus_read_data[33]) | |
724 | ); | |
725 | ||
726 | // bit 34 | |
727 | csr_sw csr_sw_34 | |
728 | ( | |
729 | // synopsys translate_off | |
730 | .omni_ld (omni_ld), | |
731 | .omni_data (omni_data[34]), | |
732 | .omni_rw_alias (1'b1), | |
733 | .omni_rw1c_alias (1'b0), | |
734 | .omni_rw1s_alias (1'b0), | |
735 | // synopsys translate_on | |
736 | .rst (por_l_active_high), | |
737 | .rst_val (reset_entry[2]), | |
738 | .csr_ld (w_ld), | |
739 | .csr_data (csrbus_wr_data[34]), | |
740 | .rw_alias (1'b1), | |
741 | .rw1c_alias (1'b0), | |
742 | .rw1s_alias (1'b0), | |
743 | .hw_ld (flts_entry_hw_ld), | |
744 | .hw_data (flts_entry_hw_write[2]), | |
745 | .cp (clk), | |
746 | .q (flts_csrbus_read_data[34]) | |
747 | ); | |
748 | ||
749 | // bit 35 | |
750 | csr_sw csr_sw_35 | |
751 | ( | |
752 | // synopsys translate_off | |
753 | .omni_ld (omni_ld), | |
754 | .omni_data (omni_data[35]), | |
755 | .omni_rw_alias (1'b1), | |
756 | .omni_rw1c_alias (1'b0), | |
757 | .omni_rw1s_alias (1'b0), | |
758 | // synopsys translate_on | |
759 | .rst (por_l_active_high), | |
760 | .rst_val (reset_entry[3]), | |
761 | .csr_ld (w_ld), | |
762 | .csr_data (csrbus_wr_data[35]), | |
763 | .rw_alias (1'b1), | |
764 | .rw1c_alias (1'b0), | |
765 | .rw1s_alias (1'b0), | |
766 | .hw_ld (flts_entry_hw_ld), | |
767 | .hw_data (flts_entry_hw_write[3]), | |
768 | .cp (clk), | |
769 | .q (flts_csrbus_read_data[35]) | |
770 | ); | |
771 | ||
772 | // bit 36 | |
773 | csr_sw csr_sw_36 | |
774 | ( | |
775 | // synopsys translate_off | |
776 | .omni_ld (omni_ld), | |
777 | .omni_data (omni_data[36]), | |
778 | .omni_rw_alias (1'b1), | |
779 | .omni_rw1c_alias (1'b0), | |
780 | .omni_rw1s_alias (1'b0), | |
781 | // synopsys translate_on | |
782 | .rst (por_l_active_high), | |
783 | .rst_val (reset_entry[4]), | |
784 | .csr_ld (w_ld), | |
785 | .csr_data (csrbus_wr_data[36]), | |
786 | .rw_alias (1'b1), | |
787 | .rw1c_alias (1'b0), | |
788 | .rw1s_alias (1'b0), | |
789 | .hw_ld (flts_entry_hw_ld), | |
790 | .hw_data (flts_entry_hw_write[4]), | |
791 | .cp (clk), | |
792 | .q (flts_csrbus_read_data[36]) | |
793 | ); | |
794 | ||
795 | // bit 37 | |
796 | csr_sw csr_sw_37 | |
797 | ( | |
798 | // synopsys translate_off | |
799 | .omni_ld (omni_ld), | |
800 | .omni_data (omni_data[37]), | |
801 | .omni_rw_alias (1'b1), | |
802 | .omni_rw1c_alias (1'b0), | |
803 | .omni_rw1s_alias (1'b0), | |
804 | // synopsys translate_on | |
805 | .rst (por_l_active_high), | |
806 | .rst_val (reset_entry[5]), | |
807 | .csr_ld (w_ld), | |
808 | .csr_data (csrbus_wr_data[37]), | |
809 | .rw_alias (1'b1), | |
810 | .rw1c_alias (1'b0), | |
811 | .rw1s_alias (1'b0), | |
812 | .hw_ld (flts_entry_hw_ld), | |
813 | .hw_data (flts_entry_hw_write[5]), | |
814 | .cp (clk), | |
815 | .q (flts_csrbus_read_data[37]) | |
816 | ); | |
817 | ||
818 | // bit 38 | |
819 | csr_sw csr_sw_38 | |
820 | ( | |
821 | // synopsys translate_off | |
822 | .omni_ld (omni_ld), | |
823 | .omni_data (omni_data[38]), | |
824 | .omni_rw_alias (1'b1), | |
825 | .omni_rw1c_alias (1'b0), | |
826 | .omni_rw1s_alias (1'b0), | |
827 | // synopsys translate_on | |
828 | .rst (por_l_active_high), | |
829 | .rst_val (reset_entry[6]), | |
830 | .csr_ld (w_ld), | |
831 | .csr_data (csrbus_wr_data[38]), | |
832 | .rw_alias (1'b1), | |
833 | .rw1c_alias (1'b0), | |
834 | .rw1s_alias (1'b0), | |
835 | .hw_ld (flts_entry_hw_ld), | |
836 | .hw_data (flts_entry_hw_write[6]), | |
837 | .cp (clk), | |
838 | .q (flts_csrbus_read_data[38]) | |
839 | ); | |
840 | ||
841 | // bit 39 | |
842 | csr_sw csr_sw_39 | |
843 | ( | |
844 | // synopsys translate_off | |
845 | .omni_ld (omni_ld), | |
846 | .omni_data (omni_data[39]), | |
847 | .omni_rw_alias (1'b1), | |
848 | .omni_rw1c_alias (1'b0), | |
849 | .omni_rw1s_alias (1'b0), | |
850 | // synopsys translate_on | |
851 | .rst (por_l_active_high), | |
852 | .rst_val (reset_entry[7]), | |
853 | .csr_ld (w_ld), | |
854 | .csr_data (csrbus_wr_data[39]), | |
855 | .rw_alias (1'b1), | |
856 | .rw1c_alias (1'b0), | |
857 | .rw1s_alias (1'b0), | |
858 | .hw_ld (flts_entry_hw_ld), | |
859 | .hw_data (flts_entry_hw_write[7]), | |
860 | .cp (clk), | |
861 | .q (flts_csrbus_read_data[39]) | |
862 | ); | |
863 | ||
864 | // bit 40 | |
865 | csr_sw csr_sw_40 | |
866 | ( | |
867 | // synopsys translate_off | |
868 | .omni_ld (omni_ld), | |
869 | .omni_data (omni_data[40]), | |
870 | .omni_rw_alias (1'b1), | |
871 | .omni_rw1c_alias (1'b0), | |
872 | .omni_rw1s_alias (1'b0), | |
873 | // synopsys translate_on | |
874 | .rst (por_l_active_high), | |
875 | .rst_val (reset_entry[8]), | |
876 | .csr_ld (w_ld), | |
877 | .csr_data (csrbus_wr_data[40]), | |
878 | .rw_alias (1'b1), | |
879 | .rw1c_alias (1'b0), | |
880 | .rw1s_alias (1'b0), | |
881 | .hw_ld (flts_entry_hw_ld), | |
882 | .hw_data (flts_entry_hw_write[8]), | |
883 | .cp (clk), | |
884 | .q (flts_csrbus_read_data[40]) | |
885 | ); | |
886 | ||
887 | assign flts_csrbus_read_data[41] = 1'b0; // bit 41 | |
888 | assign flts_csrbus_read_data[42] = 1'b0; // bit 42 | |
889 | assign flts_csrbus_read_data[43] = 1'b0; // bit 43 | |
890 | assign flts_csrbus_read_data[44] = 1'b0; // bit 44 | |
891 | assign flts_csrbus_read_data[45] = 1'b0; // bit 45 | |
892 | assign flts_csrbus_read_data[46] = 1'b0; // bit 46 | |
893 | assign flts_csrbus_read_data[47] = 1'b0; // bit 47 | |
894 | assign flts_csrbus_read_data[48] = 1'b0; // bit 48 | |
895 | assign flts_csrbus_read_data[49] = 1'b0; // bit 49 | |
896 | assign flts_csrbus_read_data[50] = 1'b0; // bit 50 | |
897 | assign flts_csrbus_read_data[51] = 1'b0; // bit 51 | |
898 | assign flts_csrbus_read_data[52] = 1'b0; // bit 52 | |
899 | assign flts_csrbus_read_data[53] = 1'b0; // bit 53 | |
900 | assign flts_csrbus_read_data[54] = 1'b0; // bit 54 | |
901 | assign flts_csrbus_read_data[55] = 1'b0; // bit 55 | |
902 | assign flts_csrbus_read_data[56] = 1'b0; // bit 56 | |
903 | assign flts_csrbus_read_data[57] = 1'b0; // bit 57 | |
904 | assign flts_csrbus_read_data[58] = 1'b0; // bit 58 | |
905 | assign flts_csrbus_read_data[59] = 1'b0; // bit 59 | |
906 | assign flts_csrbus_read_data[60] = 1'b0; // bit 60 | |
907 | assign flts_csrbus_read_data[61] = 1'b0; // bit 61 | |
908 | assign flts_csrbus_read_data[62] = 1'b0; // bit 62 | |
909 | assign flts_csrbus_read_data[63] = 1'b0; // bit 63 | |
910 | ||
911 | endmodule // dmu_mmu_csr_flts_entry |